19.08.2019. 08.30, "David Gibson" је
написао/ла:
>
> On Sun, Aug 18, 2019 at 10:59:01PM +0200, Aleksandar Markovic wrote:
> > 18.08.2019. 10.10, "Richard Henderson" је
> > написао/ла:
> > >
> > > On 8/16/19 11:59 PM, Aleksandar Markovic wrote:
> > > >> From: "Paul A. Clarke"
> > > ...
> > > >>
On 15/08/2019 22:21, Eddie James wrote:
>
> On 8/15/19 3:13 PM, Eddie James wrote:
>>
>> On 8/15/19 3:05 AM, Cédric Le Goater wrote:
>>> Hello Eddie,
>>>
>>> On 14/08/2019 22:27, Eddie James wrote:
+ sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;
+ break;
+
On 15/08/2019 22:13, Eddie James wrote:
>
> On 8/15/19 3:05 AM, Cédric Le Goater wrote:
>> Hello Eddie,
>>
>> On 14/08/2019 22:27, Eddie James wrote:
>>> The Aspeed SOCs have two SD/MMC controllers. Add a device that
>>> encapsulates both of these controllers and models the Aspeed-specific
>>> reg
On Mon, Aug 19, 2019 at 05:32:14AM +, Zeng, Star wrote:
>
>
>> -Original Message-
>> From: Wei Yang [mailto:richardw.y...@linux.intel.com]
>> Sent: Monday, August 19, 2019 10:39 AM
>> To: David Hildenbrand
>> Cc: Wei Yang ; Zeng, Star
>> ; imamm...@redhat.com; qemu-devel@nongnu.org;
>>
On Sun, Aug 18, 2019 at 10:59:01PM +0200, Aleksandar Markovic wrote:
> 18.08.2019. 10.10, "Richard Henderson" је
> написао/ла:
> >
> > On 8/16/19 11:59 PM, Aleksandar Markovic wrote:
> > >> From: "Paul A. Clarke"
> > ...
> > >> ISA 3.0B has xscvdpspn leaving its result in word 1 of the target
>
On Fri, Aug 16, 2019 at 02:27:49PM -0500, Paul A. Clarke wrote:
> From: "Paul A. Clarke"
>
> - target/ppc/fpu_helper.c:
> - helper_todouble() was not properly converting INFINITY from 32 bit
> float to 64 bit double.
> - helper_todouble() was not properly converting any denormalized
> 32
On Mon, Aug 19, 2019 at 02:38:09AM +0200, BALATON Zoltan wrote:
> Hello,
>
> I know about the possibility to set the option ROM of a PCIDevice with the
> romfile property (that we can set on command line or in a device's init
> method) but is there a way to set it depending on the machine that use
All pages, either partially sent or partially dirty, will be discarded in
postcopy_send_discard_bm_ram(), since we update the unsentmap to be
unsentmap = unsentmap | dirty in ram_postcopy_send_discard_bitmap().
This is not necessary to do discard when canonicalizing bitmap. And by
doing so, we sep
This is a cleanup for previous removal of unsentmap.
The sent parameter is not necessary now.
Signed-off-by: Wei Yang
---
migration/ram.c| 2 +-
migration/trace-events | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index 066eb475
Three patches to cleanup postcopy:
[1]: split canonicalize bitmap and discard page
[2]: remove unsentmap since it is not necessary
[3]: cleanup the get_queued_page_not_dirty
Wei Yang (3):
migration/postcopy: not necessary to do discard when canonicalizing
bitmap
migration/postcopy: unsent
Commit f3f491fcd6dd594ba695 ('Postcopy: Maintain unsentmap') introduced
unsentmap to track not yet sent pages.
This is not necessary since:
* unsentmap is a sub-set of bmap before postcopy start
* unsentmap is the summation of bmap and unsentmap after canonicalizing
This patch just remov
On Wed, Aug 14, 2019 at 5:46 PM Bin Meng wrote:
>
> Hi Palmer,
>
> On Sat, Aug 10, 2019 at 9:49 AM Alistair Francis wrote:
> >
> > On Wed, Aug 7, 2019 at 7:50 PM Bin Meng wrote:
> > >
> > > For RV32, the root page table's PPN has 22 bits hence its address
> > > bits could be larger than the maxi
On Wed, Aug 14, 2019 at 11:33 PM Bin Meng wrote:
>
> This adds 'info mem' command for RISC-V, to show virtual memory
> mappings that aids debugging.
>
> Rather than showing every valid PTE, the command compacts the
> output by merging all contiguous physical address mappings into
> one block and o
On 2019/8/19 下午1:24, Bin Meng wrote:
> On Sat, Aug 10, 2019 at 9:58 AM Alistair Francis wrote:
>> On Fri, Aug 9, 2019 at 12:26 AM Bin Meng wrote:
>>> When CADENCE_GEM_ERR_DEBUG is turned on, there are several
>>> compilation errors in DB_PRINT(). Fix them.
>>>
>>> While we are here, update to u
With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.
Signed-off-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 409
> -Original Message-
> From: Wei Yang [mailto:richardw.y...@linux.intel.com]
> Sent: Monday, August 19, 2019 10:39 AM
> To: David Hildenbrand
> Cc: Wei Yang ; Zeng, Star
> ; imamm...@redhat.com; qemu-devel@nongnu.org;
> m...@redhat.com
> Subject: Re: [Qemu-devel] [PATCH v2 1/2] memory-d
At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.
Not like other GEM variants, the FU540-specific GEM has a management
block to control 10/100/1000M
Hi!
I've googled: "usb" "designware" "otg" "datasheet"
I think this is the kernel driver for this device:
https://github.com/torvalds/linux/tree/master/drivers/usb/dwc3
Maybe it should be possible to use this as a reference? Maybe try to
redirect the proprietary drivers system calls? I don't kno
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
---
Changes in v4: None
Changes in v3:
- update IRQ numbers of both UARTs to match hardware as well
Changes in v2: N
In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.
Signed-off-by: Bin Meng
--
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 5 +++--
1 file ch
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
---
Changes in v4:
- prefix all macros/variables/functions with SIFIVE_U/sifive_u
in the sifive_u_prci driver
Changes in v3: None
Ch
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 23 +++
include/hw/riscv/s
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 21 -
include/hw/riscv/sifive_u.h | 1 +
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.
Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.
Signed
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to f
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/hw/riscv/sifive_cpu.h | 31 +++
include/hw
On Sat, Aug 10, 2019 at 9:58 AM Alistair Francis wrote:
>
> On Fri, Aug 9, 2019 at 12:26 AM Bin Meng wrote:
> >
> > When CADENCE_GEM_ERR_DEBUG is turned on, there are several
> > compilation errors in DB_PRINT(). Fix them.
> >
> > While we are here, update to use appropriate modifiers in
> > the
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 7
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by: Bin Meng
Reviewe
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c |
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw
Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create homogeneous harts. Exact the
hart realize to a separate routine in preparation for supporting
multiple hart arrays.
Note the file header say
This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.
Signed-off-by: Bin Meng
---
Changes in v4:
- prefix all macros/vari
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v4: None
Changes in v3:
- use management cpu count + 1 for the min_cpus
Changes in v2:
- update the file header to indicate at least 2 harts are created
hw/riscv/sifive_
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng
---
Changes in v4:
- new patch to remove executable attribute of opensbi images
Changes in v3: None
Changes in v2: None
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/o
As of today, the QEMU 'sifive_u' machine is a special target that does
not boot the upstream OpenSBI/U-Boot firmware images built for the real
SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
"qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced
in the OpenSB
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
Changes in v4:
- change create_fdt() to return void in sifive_u.c too, afte
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_e_prci.c
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Reviewed-by: Alistair Francis
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- keep the PLIC compatible string unchanged as OpenSBI
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 18 +-
hw/riscv/vir
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v4:
- remove 2 more "linux,phandle" instances in sifive_u.c and spike.c
after rebasing on Palmer's QEMU RISC-V
On Fri, Jun 21, 2019 at 10:27:39PM +0800, Wei Yang wrote:
>No functional change. Add default case to fix warning.
>
Hi, David & Juan
Do you like this?
>Signed-off-by: Wei Yang
>---
> migration/migration.c | 8 +++-
> migration/migration.h | 6 +++---
> 2 files changed, 10 insertions(+), 4 del
During migration, there are several places to iterate on
savevm.handlers. And on each iteration, we need to check its ops and
related callbacks before invoke it.
Generally, ops is the first element to check, and it is only necessary
to check it once.
This patch clean all the related part in savev
On 2019/8/19 上午5:38, Philippe Mathieu-Daudé wrote:
> Hi Jason,
>
> On 8/8/19 4:34 PM, Philippe Mathieu-Daudé wrote:
>> This is a preparatory cleanup series.
>>
>> Commit 75020a70215 introduced 4 very equivalent structures:
>> - tcp_header and tcp_hdr,
>> - udp_header and udp_hdr.
>>
>> Choose the
On Thu, Mar 21, 2019 at 04:25:49PM +0800, Wei Yang wrote:
>This serial refine exec a little.
>
Ping again.
>Wei Yang (6):
> exec.c: replace hwaddr with uint64_t for better understanding
> exec.c: remove an unnecessary assert on PHYS_MAP_NODE_NIL in
>phys_map_node_alloc()
> exec.c: get node
On Thu, Aug 08, 2019 at 09:06:21AM +0200, David Hildenbrand wrote:
>On 08.08.19 04:38, Wei Yang wrote:
>> On Thu, Aug 08, 2019 at 02:30:02AM +, Zeng, Star wrote:
-Original Message-
From: Wei Yang [mailto:richardw.y...@linux.intel.com]
Sent: Thursday, August 8, 2019 10:13
On Wed, Jul 31, 2019 at 10:42:23PM +0800, Wei Yang wrote:
>Two cleanup:
>
>Patch #1 make code consistent on calling add_to_iovec
>Patch #2 refine the code to handle the case when buf already flushed
>
Ping~
>Wei Yang (2):
> migration/qemu-file: remove check on writev_buffer in
>qemu_put_comp
On Fri, Jul 19, 2019 at 06:54:00PM +0100, Dr. David Alan Gilbert wrote:
>* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> Since the start addr is already checked, to make sure the range is
>> aligned, checking the length is enough.
>>
>> Signed-off-by: Wei Yang
>> ---
>> exec.c | 7 +++
>
Hi,
On 2019-08-19 01:25, Philippe Mathieu-Daudé wrote:
> Hi Zoltán,
>
> On 8/19/19 1:06 AM, Kővágó, Zoltán wrote:
>> Signed-off-by: Kővágó, Zoltán
>> ---
>> audio/audio.c | 6 ++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/audio/audio.c b/audio/audio.c
>> index 924dddf2e7..9b28abc
On 2019/8/16 21:49, Eduardo Habkost wrote:
On Fri, Aug 16, 2019 at 09:04:16AM +0800, Like Xu wrote:
Hi,
On 2019/8/16 2:38, Eduardo Habkost wrote:
The error message for die-id range validation is incorrect. Example:
$ qemu-system-x86_64 -smp 1,sockets=6,maxcpus=6 \
-device qemu64-x8
Hello,
I know about the possibility to set the option ROM of a PCIDevice with the
romfile property (that we can set on command line or in a device's init
method) but is there a way to set it depending on the machine that uses
the device? If this is not currently possible what would be needed t
Patchew URL:
https://patchew.org/QEMU/cover.1566168923.git.dirty.ice...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v4 00/14] Multiple simultaneous audio backends
Message-id: cover.156616
Hi Zoltán,
On 8/19/19 1:06 AM, Kővágó, Zoltán wrote:
> Signed-off-by: Kővágó, Zoltán
> ---
> audio/audio.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/audio/audio.c b/audio/audio.c
> index 924dddf2e7..9b28abca14 100644
> --- a/audio/audio.c
> +++ b/audio/audio.c
> @@ -1343,6
Update to environment variables of our Docker image to closely
reproduce the builds run by the Travis-CI service.
Default variables from:
https://docs.travis-ci.com/user/environment-variables/#default-environment-variables
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/travi
Add a runner script to be able to run acceptance tests within
Docker images. We can now reproduce Travis CI builds locally (and
debug them!).
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/test-acceptance | 21 +
1 file changed, 21 insertions(+)
create mode 100755 t
Use one package per line to improve readability. This also
helps while reviewing patches.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/travis.docker | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/tests/docker/dockerfiles/travis.docker
b/tests
Signed-off-by: Kővágó, Zoltán
---
Notes:
Changes from v3:
* (Hopefully) fix windows build
audio/audio.h | 4 +-
audio/audio_int.h | 26 +++
audio/audio_template.h | 14 ++--
audio/mixeng.h | 9 +--
audio/rate_template.h | 2 +-
include/sysemu
Since commit aa983ff67c3, Travis CI runs acceptance tests using
the Avocado framework. Since Avocado requires Python 3, update
our Docker image to be able to run these tests locally.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/travis.docker | 2 ++
1 file changed, 2 insert
This series adds a 'test-acceptance' Docker target, so we can
run 'make docker-test-acceptance@travis' similarly to how the
Travis-CI service runs its builds.
This is particularly useful to debug Travis-CI failures locally.
Regards,
Phil.
Philippe Mathieu-Daudé (4):
tests/docker: Use one pack
They just called audio_pcm_sw_read/write anyway, so it makes no sense
to have them too. (The noaudio's read is the only exception, but it
should work with the generic code too.)
Signed-off-by: Kővágó, Zoltán
---
audio/audio_int.h | 5 -
audio/alsaaudio.c | 12
audio/audio.
Signed-off-by: Kővágó, Zoltán
---
audio/audio.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/audio/audio.c b/audio/audio.c
index 924dddf2e7..9b28abca14 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -1343,6 +1343,12 @@ static void free_audio_state(AudioState *s)
qapi_free
Pulseaudio normally assumes that when the server wants it, the client
can generate the audio samples and send it right away. Unfortunately
this is not the case with QEMU -- it's up to the emulated system when
does it generate the samples. Buffering the samples and sending them
from a background t
Unless we disable stream moving, pulseaudio can easily move the stream
on connect, effectively ignoring the source/sink specified by the user.
Signed-off-by: Kővágó, Zoltán
Reviewed-by: Marc-André Lureau
---
audio/paaudio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/audio/paaudio.
Have a pool of refcounted connections per server, so if the user creates
multiple audiodevs to the same pa server, it will use a single connection. (It
will still create different streams, so the user can manage those streams
separately in pulseaudio.)
Signed-off-by: Kővágó, Zoltán
---
audio/pa
There's already a MIN and MAX macro in include/qemu/osdep.h, use them
instead.
Signed-off-by: Kővágó, Zoltán
Reviewed-by: Marc-André Lureau
---
audio/audio.h | 17 -
audio/alsaaudio.c | 6 +++---
audio/audio.c | 20 ++--
audio/cor
audio_run is called manually by alsa and oss backends when polling.
In this case only the requesting backend should be run, not all of them.
Signed-off-by: Kővágó, Zoltán
Reviewed-by: Marc-André Lureau
---
audio/audio_int.h | 2 +-
audio/alsaaudio.c | 7 +--
audio/audio.c | 14 +--
Audio functions no longer access glob_audio_state, instead they get an
AudioState as a parameter. This is required in order to support
multiple backends.
glob_audio_state is also gone, and replaced with a tailq so we can store
more than one states.
Signed-off-by: Kővágó, Zoltán
---
Notes:
Finally add audiodev= options to audio frontends so users can specify
which backend to use when multiple backends exist. Not specifying an
audiodev= option currently causes the first audiodev to be used, this is
fixed in the next commit.
Example usage: -audiodev pa,id=foo -device AC97,audiodev=fo
Currently this needs a workaround due to bug #247 in pulseaudio.
Signed-off-by: Kővágó, Zoltán
Reviewed-by: Marc-André Lureau
---
audio/paaudio.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/audio/paaudio.c b/audio/paaudio.c
index 24d98b344a..1d
This means you should probably stop using -soundhw (as it doesn't allow
you to specify any options) and add the device manually with -device.
The exception is pcspk, it's currently not possible to manually add it.
To use it with audiodev, use something like this:
-audiodev id=foo,... -global i
Signed-off-by: Kővágó, Zoltán
---
Notes:
Changes from v2:
* audiodev parameter for wavcapture is now mandatory.
* removed some unnecessary qdict_haskey calls from hmp_wavcapture
ui/vnc.h| 2 ++
monitor/misc.c | 22 +++---
ui/vnc.c| 15 +
Hello,
This is the v4 of my audio patches. This is a compile-fix revision, hopefully
fixing windows compile errors in "audio: use size_t where makes sense" and
compile errors introduced by changes on master in "audio: add audiodev
properties to frontends".
Regards,
Zoltan
Kővágó, Zoltán (14):
Remove glob_audio_state from functions, where possible without breaking
the API. This means that most static functions in audio.c now take an
AudioState pointer instead of implicitly using glob_audio_state. Also
included a pointer in SWVoice*, HWVoice* structs, so that functions
dealing them can
Pass the FWCfgState object by argument, this will
allow us to remove the PCMachineState argument later.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index
Extract all the functions that are not PC-machine specific into
the (arch-specific) fw_cfg.c file. This will allow other X86-machine
to reuse these functions.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
v4: rebased using MachineState argument with smbios_get_tables*()
Now that the pc_build_feature_control_file() function has been
refactored to not depend of PC specific types, rename it to a
more generic name.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --g
in real world, we deprecate AB-seg usage because they are vulnerable to smm
cache poison attack.
I assume cache poison is out of scope in the virtual world, or there is a way
to prevent ABseg cache poison.
thank you!
Yao, Jiewen
> 在 2019年8月19日，上午3:50，Paolo Bonzini 写道：
>
>> On 17/08/19 02:20
Now that the pc_build_smbios() function has been refactored to not
depend of PC specific types, rename it to a more generic name.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.
Let the pc_build_feature_control_file() function take a generic MachineState
argument.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 460f55fd09..e57468a
Let the pc_build_smbios() function take a generic MachineState
argument.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 63cb27ff18..0bd411de6e 100644
---
Pass the FWCfgState object by argument, this will
allow us to remove the PCMachineState argument later.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
in
Suggested-by: Samuel Ortiz
Reviewed-by: Li Qiang
Signed-off-by: Philippe Mathieu-Daudé
---
v3: KISS, do not use unsigned, do not add broken documentation
---
hw/i386/Makefile.objs| 2 +-
hw/i386/e820_memory_layout.c | 59 ++
hw/i386/e820_memory_layout.h
Pass the CPUArchIdList array by argument, this will
allow us to remove the PCMachineState argument later.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/hw/i386/pc.c b/hw/
Pass the apic_id_limit value by argument, this will
allow us to remove the PCMachineState argument later.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index
In the previous commit we removed the last access to PCMachineState.
It is now an unused argument, remove it from the function prototype.
Suggested-by: Christophe de Dinechin
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff
To be able to extract the e820* code out of this file (in the next
patch), access e820_entries with its correct helper.
Reviewed-by: Li Qiang
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
in
The boot_cpus is used once. Pass it by argument, this will
allow us to remove the PCMachineState argument later.
Suggested-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc
The address_space_memory variable is used once.
Use it in place and remove the argument.
Suggested-by: Samuel Ortiz
Reviewed-by: Li Qiang
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.
The bochs_bios_init() function is not restricted to the Bochs
BIOS and is useful to other BIOS.
Since it is not specific to the PC machine, and can be reused
by other machines of the X86 architecture, rename it as
fw_cfg_arch_create().
Suggested-by: Samuel Ortiz
Reviewed-by: Li Qiang
Signed-off-
Hi,
This is my take at salvaging some NEMU good work.
Samuel worked in adding the fw_cfg device to the x86-virt NEMU machine.
This series is inspired by NEMU's commit 3cb92d080835 [0] and adapted
to upstream style. The result makes the upstream codebase more
modularizable.
There are very little lo
Cc'ing Marc-André
On 8/16/19 11:10 PM, Shu-Chun Weng via Qemu-devel wrote:
> Add support for the memfd_create syscall. If the host does not have the
> libc wrapper, translate to a direct syscall with NC-macro.
>
> Buglink: https://bugs.launchpad.net/qemu/+bug/1734792
> Signed-off-by: Shu-Chun Wen
On 8/18/19 2:28 PM, Yuval Shaia wrote:
> On Thu, Aug 15, 2019 at 02:12:44PM +0200, Stephen Kitt wrote:
>> On Thu, 15 Aug 2019 13:57:05 +0300, Yuval Shaia
>> wrote:
>>
>>> On Sun, Aug 11, 2019 at 09:42:47PM +0200, Stephen Kitt wrote:
This was broken by the cherry-pick in 41dd30f. Fix by handli
On 8/18/19 8:39 AM, Richard Henderson wrote:
> Call this form a "parameter", returning a value extracted
> from the DisasContext.
>
> Signed-off-by: Richard Henderson
> ---
> docs/devel/decodetree.rst | 8 -
> scripts/decodetree.py | 49 ---
>
On 8/16/19 9:30 AM, tony.ngu...@bt.com wrote:
> Convert memory_region_dispatch_{read|write} operand "unsigned size"
> into a "MemOp op".
>
> Signed-off-by: Tony Nguyen
> Reviewed-by: Richard Henderson
> ---
> include/exec/memop.h | 20 ++--
> include/exec/memory.h | 9 +---
Hi Jason,
On 8/8/19 4:34 PM, Philippe Mathieu-Daudé wrote:
> This is a preparatory cleanup series.
>
> Commit 75020a70215 introduced 4 very equivalent structures:
> - tcp_header and tcp_hdr,
> - udp_header and udp_hdr.
>
> Choose the most widely use in the codebase, which happens to
> provide co
18.08.2019. 10.10, "Richard Henderson" је
написао/ла:
>
> On 8/16/19 11:59 PM, Aleksandar Markovic wrote:
> >> From: "Paul A. Clarke"
> ...
> >> ISA 3.0B has xscvdpspn leaving its result in word 1 of the target
> > register,
> >> and mffprwz expecting its input to come from word 0 of the sour
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