On Fri, Jun 14, 2019 at 10:39:27PM +0200, Max Reitz wrote:
> On 06.06.19 11:25, Klaus Birkelund Jensen wrote:
> > The device mistakenly reports that the Weighted Round Robin with Urgent
> > Priority Class arbitration mechanism is supported.
> >
> > It is not.
>
> I believe you based on the fact t
Hi,
> > Ok, given that seabios has no setup any manual configuration needs to be
> > done via qemu.
> >
> > But why do we need a new interface for that? IDE can pass the geometry
> > to the guest. virtio-blk has support too (VIRTIO_BLK_F_GEOMETRY).
> > Likewise scsi (MODE_PAGE_HD_GEOMETRY).
On Mon, 17 Jun 2019 at 13:24, Greg Kurz wrote:
>
> On Mon, 17 Jun 2019 10:14:30 +0800
> Yongji Xie wrote:
>
> > On Fri, 14 Jun 2019 at 19:45, Greg Kurz wrote:
> > >
> > > On Fri, 14 Jun 2019 17:31:17 +0800
> > > elohi...@gmail.com wrote:
> > >
> > > > From: Xie Yongji
> > > >
> > > > In order t
Hi,
Ken - I think all I said in comment #2 still applies (and likely won't change).
It really is a non-issue warning - and even if you e.g. have a zero-
warning-allowed policy then you can easily avoid that by using a CPU
type that doesn't enable it by default or switch it on/off as needed. In
lib
On Mon, 17 Jun 2019 10:14:30 +0800
Yongji Xie wrote:
> On Fri, 14 Jun 2019 at 19:45, Greg Kurz wrote:
> >
> > On Fri, 14 Jun 2019 17:31:17 +0800
> > elohi...@gmail.com wrote:
> >
> > > From: Xie Yongji
> > >
> > > In order to avoid migration issues, we introduce a "use-started"
> > > property
Hi Cleber,
On 5/11/18 4:27 PM, Cleber Rosa wrote:
> On 05/11/2018 09:55 AM, Eduardo Habkost wrote:
>> (CCing Cleber and avocado-devel in case they have suggestions)
>>
>> On Tue, May 08, 2018 at 12:47:52PM -0300, Philippe Mathieu-Daudé wrote:
>> [...]
>>> Ironically I have been using the Gumstix m
Hi Igor, Eduardo,
On 2/6/18 3:43 PM, Igor Mammedov wrote:
> On Mon, 5 Feb 2018 20:42:05 -0200
> Eduardo Habkost wrote:
>
>> On Mon, Feb 05, 2018 at 03:42:02PM +0100, Igor Mammedov wrote:
>>> On Mon, 5 Feb 2018 11:54:01 -0200
>>> Eduardo Habkost wrote:
>>>
On Mon, Feb 05, 2018 at 12:22:3
On 6/17/19 3:25 AM, Alexey Kardashevskiy wrote:
> On 14/06/2019 19:33, Stefan Hajnoczi wrote:
>> On Fri, Jun 14, 2019 at 10:13:04AM +1000, Alexey Kardashevskiy wrote:
>>>
>>>
>>> On 13/06/2019 23:08, Philippe Mathieu-Daudé wrote:
Hi Alexey,
On 6/13/19 7:09 AM, Alexey Kardashevskiy wr
Instead of fetching the prebuilt image from patchew download the install
iso and prepare the image locally. Install to disk, using the serial
console. Create qemu user, configure ssh login. Install packages
needed for qemu builds.
Signed-off-by: Gerd Hoffmann
---
tests/vm/openbsd | 159 ++
Instead of fetching the prebuilt image from patchew download the install
iso and prepare the image locally. Install to disk, using the serial
console. Create qemu user, configure ssh login. Install packages
needed for qemu builds.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Kamil Rytarowski
Tes
Instead of fetching the prebuilt image from patchew download the install
iso and prepare the image locally. Install to disk, using the serial
console. Create qemu user, configure ssh login. Install packages
needed for qemu builds.
Note that freebsd package downloads are delivered as non-cachabl
Add a bunch of helpers to talk to the guest using the
serial console.
Also drop the hard-coded -serial parameter for the vm
so QEMUMachine.set_console() actually works.
Signed-off-by: Gerd Hoffmann
Tested-by: Thomas Huth
---
tests/vm/basevm.py | 86 -
The build script doesn't shutdown the guest VMs properly,
which results in filesystem corruption and guest boot
failures sooner or later.
Use the --snapshot to run builds on a snapshot,
That way killing the VM doesn't corrupt the base image.
Signed-off-by: Gerd Hoffmann
Tested-by: Thomas Huth
-
This patch series changes the way virtual machines for test builds are
managed. They are created locally on the developer machine now. The
installer is booted on the serial console and the scripts walks through
the dialogs to install and configure the guest.
That takes the download.patchew.org s
Configure apt proxy so package downloads
can be cached and can pass firewalls.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Philippe Mathieu-Daudé
---
tests/vm/ubuntu.i386 | 4
1 file changed, 4 insertions(+)
diff --git a/tests/vm/ubuntu.i386 b/tests/vm/ubuntu.i386
index a22d137e76df..b869af
For testing/troubleshooting convinience.
make vm-boot-serial-
Boot guest, with the serial console on stdio.
make vm-boot-ssh-
Boot guest, login via ssh.
Signed-off-by: Gerd Hoffmann
Tested-by: Thomas Huth
---
tests/vm/Makefile.include | 19 +++
1 file changed, 19 insertion
Packages are fetched via proxy that way, if configured on the host.
That might be required to pass firewalls, and it allows to route
package downloads through a caching proxy server.
Needs AcceptEnv setup in sshd_config on the guest side to work.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Philipp
When not running in snapshot mode ask the guest to poweroff and wait for
this to finish instead of simply quitting qemu, so the guest can flush
pending updates to disk.
Signed-off-by: Gerd Hoffmann
Tested-by: Thomas Huth
---
tests/vm/basevm.py | 22 +++---
1 file changed, 15 ins
Allways ask ssh to run with a pseudo terminal.
Not having a terminal causes problems now and then.
Signed-off-by: Gerd Hoffmann
Tested-by: Thomas Huth
---
tests/vm/basevm.py | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/tests/vm/basevm.py b/tests/vm/basevm.py
Download the install iso and prepare the image locally. Install to
disk, using the serial console. Create qemu user, configure ssh login.
Install packages needed for qemu builds.
Yes, we have docker images for fedora. But for trouble-shooting it
might be helpful to have a vm too. When vm build
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1267520
Title:
Keyboard in
Hi, I found there is a bug in pr-helper:
We run pr-helper process in root, and drop all capabilities expect
CAP_SYS_RAWIO.
But the sock file which connect from qemu is owned by qemu group,
when pr-helper exit,
it will call “close_server_socket ->
object_unref(OBJECT(server_ioc))
On Fri, Jun 14, 2019 at 09:11:06AM -0700, Cosmin Marin wrote:
> During auto-convergence live migration, the configured throttling rate
> is not matched in practice. Experimental measurements of throughput for
> a memory-write intensive workload indicate disparities between expected
> and measured t
On 6/16/2019 11:35 PM, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index
E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.
This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
guest.
Co-deve
On 6/14/19 6:53 AM, vandersonmr wrote:
> Added -execfreq to enable execution frequency counting and dump
> all the TB's addresses and their execution frequency at the end
> of the execution.
>
> Signed-off-by: vandersonmr
> ---
> linux-user/exit.c | 5 +
> linux-user/main.c | 7 +++
> 2
On 6/14/19 6:53 AM, vandersonmr wrote:
> A new hash map was added to store the accumulated execution
> frequency of the TBs even after tb_flush events. A dump
> function was also added as a way to visualize these frequencies.
>
> Signed-off-by: vandersonmr
> ---
> accel/tcg/translate-all.c | 59
On Mon, 3 Jun 2019 at 18:54, Philippe Mathieu-Daudé wrote:
>
> Hi Hongbo, Ard.
>
> On 4/18/19 6:04 AM, Hongbo Zhang wrote:
> > Following the previous patch, this patch adds peripheral devices to the
> > newly introduced SBSA-ref machine.
> >
> > Signed-off-by: Hongbo Zhang
> > ---
> > hw/arm/sbs
On 6/14/19 6:53 AM, vandersonmr wrote:
> +void HELPER(inc_exec_freq)(void *ptr)
> +{
> +TranslationBlock* tb = (TranslationBlock*) ptr;
> +atomic_inc(&tb->exec_freq);
> +}
...
> +DEF_HELPER_FLAGS_1(inc_exec_freq, TCG_CALL_NO_RWG, void, ptr)
...
> uint32_t flags; /* flags defining in wh
On 6/14/19 10:11 AM, Alex Bennée wrote:
> start_exclusive();
> +cpu->in_exclusive_work_context = true;
> wi->func(cpu, wi->data);
> +cpu->in_exclusive_work_context = false;
> end_exclusive();
Is there a reason not to put those into sta
On Fri, 14 Jun 2019 at 19:45, Greg Kurz wrote:
>
> On Fri, 14 Jun 2019 17:31:17 +0800
> elohi...@gmail.com wrote:
>
> > From: Xie Yongji
> >
> > In order to avoid migration issues, we introduce a "use-started"
> > property to the base virtio device to indicate whether use
> > "started" flag or no
On 6/14/19 10:11 AM, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> Afterwise is "wise after the fact", as in "hindsight".
> Here we meant "afterwards" (as in "subsequently"). Fix it.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
> ---
> tcg/README | 2 +-
> 1 file changed, 1
On 6/14/19 10:11 AM, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> This will allow us to trace 16B-long memory accesses.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
> ---
> trace-events | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/trace-events b
On 6/16/19 5:37 AM, Mark Cave-Ayland wrote:
> Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
> registers are in host endian order" functions getVSR() and putVSR() which used
> to convert the VSR registers into host endian order are no longer required.
>
> Signed-off-by:
On 14/06/2019 19:33, Stefan Hajnoczi wrote:
> On Fri, Jun 14, 2019 at 10:13:04AM +1000, Alexey Kardashevskiy wrote:
>>
>>
>> On 13/06/2019 23:08, Philippe Mathieu-Daudé wrote:
>>> Hi Alexey,
>>>
>>> On 6/13/19 7:09 AM, Alexey Kardashevskiy wrote:
This adds a trace point which prints every l
On 6/16/19 5:37 AM, Mark Cave-Ayland wrote:
> Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
> registers are in host endian order" functions getVSR() and putVSR() which used
> to convert the VSR registers into host endian order are no longer required.
>
> Signed-off-by:
As expected files have been updated, make sure we
do not forget to remove them from the allowed
diff list.
Signed-off-by: Michael S. Tsirkin
---
tests/data/acpi/rebuild-expected-aml.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/data/acpi/rebuild-expected-aml.sh
b/tests/data/ac
update expected files and drop them from allowed diff list.
Fixes: 4a4418369d6 ("q35: fix mmconfig and PCI0._CRS")
Signed-off-by: Michael S. Tsirkin
---
tests/bios-tables-test-allowed-diff.h | 8
tests/data/acpi/q35/DSDT | Bin 7815 -> 7841 bytes
tests/data/acpi/q35/DSDT.
From: Li Hangjing
When a guest which doesn't support multiqueue is migrated with a multi queues
vhost-user-blk deivce, a crash will occur like:
0 qemu_memfd_alloc (name=, size=562949953421312,
seals=, fd=0x7f87171fe8b4, errp=0x7f87171fe8a8) at
util/memfd.c:153
1 0x7f883559d7cf in vhost_log
The following changes since commit f3d0bec9f80e4ed7796fffa834ba0a53f2094f7f:
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2019-06-14'
into staging (2019-06-14 14:46:13 +0100)
are available in the Git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/fo
At present we have a potential error in that helper_retaddr contains
data for handle_cpu_signal, but we have not ensured that those stores
will be scheduled properly before the operation that may fault.
The "proper" C11 function from for this is
atomic_signal_fence(). This expands to a compiler
These functions are not used, and are not usable in the
context of code generation, because we never have a helper
return address to pass in to them.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst_useronly_template.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --
Check page flags before letting an invalid pc cause a SIGSEGV.
Prepare for eventially validating PROT_EXEC. The current wrinkle being
that we have a problem with our implementation of signals. We should
be using a vdso like the kernel, but we instead put the trampoline on
the stack. In the mean
Patchew URL: https://patchew.org/QEMU/20190616191900.gh61...@hippo.sing.id.au/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
Type: series
Message-id: 20190616191900.gh61...@h
While working on a Go (www.golang.org) port for riscv, I've run
into issues with atomics (namely LR/SC) on qemu-system-riscv64.
There are several reproducers for this problem including one
using gcc builtin atomics:
https://gist.github.com/4a6f656c/8433032a3f70893a278259f8108aad90
And a version
On Wed, 8 May 2019 14:17:26 +0800
Tao Xu wrote:
> From: Liu Jingqi
>
> OSPM evaluates HMAT only during system initialization.
> Any changes to the HMAT state at runtime or information
> regarding HMAT for hot plug are communicated using _HMA method.
>
> _HMA is an optional object that enables
On Wed, 8 May 2019 14:17:24 +0800
Tao Xu wrote:
> From: Liu Jingqi
>
> Add -numa hmat-cache option to provide Memory Side Cache Information.
> These memory attributes help to build Memory Side Cache Information
> Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).
>
> Signed-off
On Mon, 10 Jun 2019 21:39:12 +0800
Tao Xu wrote:
> On 6/7/2019 12:45 AM, Igor Mammedov wrote:
> > On Thu, 6 Jun 2019 11:00:33 +0800
> > Tao Xu wrote:
> >
> ...
> >>
> >> But the kernel HMAT can read othe Memory Side Cache Information except
> >> SMBIOS entries and the host HMAT tables also ha
On Sun, 16 Jun 2019 08:18:18 -0700 (PDT)
no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
>
>
to fix MAINTAINERS warning, you can add new entry there at
the first patch that introduces new directory/file and get rid of 23/2
On Sun, 16 Jun 2019 23:28:33 +0900
Yoshinori Sato wrote:
> From: Philippe Mathieu-Daudé
>
> Some RX peripheral using 8bit and 16bit registers.
> Added 8bit and 16bit APIs.
probably should go before 13/24 (i.e. before actual users start using it)
this patch causes checkpatch errors but it uses
On Sun, 16 Jun 2019 23:28:29 +0900
Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato
> ---
> hw/rx/rx-virt.c | 22 ++
> target/rx/cpu.c | 22 --
> 2 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c
>
On Sun, 16 Jun 2019 23:28:17 +0900
Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato
THere is no point in sending it as separate patch,
If you'd merged this patch into 3/24 I'd ack it.
So pls merge it there.
> ---
> target/rx/cpu.c | 20 +++-
> 1 file changed, 3 insertions(
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Type: series
Message-id: 20190616142836.
On Sun, 16 Jun 2019 23:28:15 +0900
Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato
> Reviewed-by: Richard Henderson
> Message-Id: <20190607091116.49044-4-ys...@users.sourceforge.jp>
> Signed-off-by: Richard Henderson
> [PMD: Use newer QOM style, split cpu-qom.h, restrict access to
> ext
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190616142836.10614-1-ys...@users.sourceforge.jp
Type: series
Subject: [Qemu-devel] [PATCH v20
It turns out we can't fix this without also fixing
our implementation of signal trampolines.
** Changed in: qemu
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/1832916
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Type: series
Message-id: 20190616142836.
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Message-id: 20190616142836.10614-1-ys...
On Fri, 14 Jun 2019 17:31:18 +0800
elohi...@gmail.com wrote:
> From: Xie Yongji
>
> Besides virtio 1.0 transitional devices, we should also
> set "start_on_kick" flag for legacy devices (virtio 0.9).
>
> Signed-off-by: Xie Yongji
> ---
Reviewed-by: Greg Kurz
> hw/virtio/virtio.c |
Make kvmppc_xive_disconnect() able to undo the changes of a partial
execution of kvmppc_xive_connect() and use it to perform rollback.
Based-on: <20190614165920.12670-2-...@kaod.org>
Signed-off-by: Greg Kurz
---
hw/intc/spapr_xive_kvm.c | 48 --
1 fi
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Type: series
Message-id: 20190616142836.
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Message-id: 20190616142836.10614-1-ys...
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index
E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.
This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
guest.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingq
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
UMONITOR arms address monitoring hardware using an address. A store
to an address within the specified address range triggers the
monitoring hardware to wake up the processor waiting in umwait.
UMWAIT instructs the processor to ente
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
This patch adds support for user wait instructions in KVM. Availability
of the user wait instructions is indicated by the presence of the CPUID
feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. User wait instructions may
be executed at any
> Aleksandar: Can we use SEMIHOSTING on KVM MIPS?
>
You can assume the answer is no, we can't. But James Hogan, who maintains
MIPS KVM, may have different view, and his answer would override mine.
Yours,
Aleksandar
> For ARM Peter said:
>
> "semihosting hooks either SVC or HLT instructions, and
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Type: series
Message-id: 20190616142836.
Add cpu-param.h
Remove CPU_COMMON
Use env_cpu
Signed-off-by: Yoshinori Sato
---
target/rx/cpu-param.h | 31 +++
target/rx/cpu.h | 21 +
target/rx/cpu.c | 1 +
target/rx/op_helper.c | 6 +++---
4 files changed, 36 insertions(+), 23 del
This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-6-ys...@users.sourcefo
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-3-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
[PMD: Removed tlb_fill, extracted from patch of Yoshinori Sato
'Convert to CPUClass::tlb_fill']
Signed
This part only supported RXv1 instructions.
Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-2-ys...@users
rx62n - RX62N cpu.
rx-virt - RX QEMU virtual target.
Signed-off-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-9-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
[PMD: Use TYPE_RX62N_CPU, use #define for RX
From: Philippe Mathieu-Daudé
Add two tests for the rx-virt machine, based on the recommended test
setup from Yoshinori Sato:
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03586.html
- U-Boot prompt
- Linux kernel with Sash shell
These are very quick tests:
$ avocado run -t arch:rx
From: Richard Henderson
This has consistency with prt_ri(). It loads all data before
beginning output. It uses exactly one call to prt() to emit
the full instruction.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-5-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
include/disas/dis-asm.h |5 +
target/rx/disas.c | 1480 +
From: Philippe Mathieu-Daudé
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-11-ys...@users.sourceforge.jp>
Tested-by: Philippe Math
From: Richard Henderson
Collected, to be used in the next patch.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-23-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
From: Richard Henderson
Note that the ld == 3 case handled by prt_ldmi is decoded as
XCHG_rr and cannot appear here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-21-ys...@users.sourceforge.jp>
Tested-by: Philip
renesas_tmr: 8bit timer modules.
renesas_cmt: 16bit compare match timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philip
Hello.
This patch series is added Renesas RX target emulation.
Changes for v19.
Follow tcg changes.
Cleanup cpu.c.
simplify rx_cpu_class_by_name and rx_load_image move to rx-virt.
My git repository is bellow.
git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190616
Testing binaries
This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-8-ys...@users.sourcef
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-17-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
pick ed65c02993 target/rx: Add RX to SysEmuTarget
pick 01372568ae tests: Add rx to machine-none-t
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-10-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/bitops.h | 38 +
From: Richard Henderson
We were eliding all zero indexes. It is only ld==0 that does
not have an index in the instruction. This also allows us to
avoid breaking the final print into multiple pieces.
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-1
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-4-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
[PMD: Use newer QOM style, split cpu-qom.h, restrict access to
extable array, use rx_cpu_tlb_fill() extracted from patch of
Yoshinori Sa
From: Richard Henderson
Issue an error if no kernel, no bios, and not qtest'ing.
Fixes make check-qtest-rx: test/qom-test.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-16-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signe
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-virt.c | 22 ++
target/rx/cpu.c | 22 --
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c
index ed0a3a1da0..4cfe2e3123 100644
--- a/hw/rx/rx-virt.c
+++ b/hw/rx/rx-v
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-18-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 19 +++
1 file changed, 19 insertions(+)
diff --git a/MAINTAINER
From: Richard Henderson
Many of the multi-part prints have been eliminated by previous
patches. Eliminate the rest of them.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-22-ys...@users.sourceforge.jp>
Tested-by
From: Richard Henderson
There are so many different forms of each RX instruction
that it will be very useful to be able to look at the bytes
to see on which path a bug may lie.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <201906070
From: Philippe Mathieu-Daudé
While the VIRT machine can use different microcontrollers,
the RX62N microcontroller is tied to the RX62N CPU core.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-virt.c | 8
1 file changed, 8 insertions(+)
diff --git a/
On m68k there are two varities of stack pointers, USP with SSP or ISP/MSP.
Only the 68020/30/40 support the MSP register the stack swap helpers dont
support this feature.
This patch adds this support, as well as comments to CPUM68KState to
make it clear how stacks are handled
Signed-off-by: Luc
Signed-off-by: Yoshinori Sato
---
target/rx/cpu.c | 20 +++-
1 file changed, 3 insertions(+), 17 deletions(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index a6dde613ab..e3d76af55d 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -72,9 +72,8 @@ static void rx_cpu_reset(
The BUSCR/PCR CR defines were missing for 68060, and the move_to/from helper
functions were also missing a decode for the 68060 M68K_CR_CAAR CR register.
Added missing defines, and respective decodes for all three CR registers to
the helpers.
Although this patch defines them, the implementation i
Added more detailed comments to each case of m68k_move_to/from helpers to list
the supported CPUs for that CR as they were wrong in some cases, and
missing some cpu classes in other cases.
Signed-off-by: Lucien Murray-Pitts
---
target/m68k/helper.c | 41 +++--
Added "CPU class" m68k_feature to each CPU init func so MOVEC can detect wrong
CR (Control Register) access.
Added CPU class detection for each CR type in the m68k_move_to/from helpers,
so that it throws and exception if an unsupported register is requested
for that CPU class.
Reclassified MOVEC
The m680XX_cpu_initfn functions have been rearranged to cascade starting from
the base 68000, so that the 68010 then inherits from this, and so on until the
68060.
This makes it simpler to track features since in most cases the m68k were
product enhancements on each other, with only a few instruct
Improvement in comments for the instantiation functions.
This is to highlight what each cpu class, in the 68000 series, contains
in terms of instructions/features.
Signed-off-by: Lucien Murray-Pitts
---
target/m68k/cpu.c | 47 +++
target/m68k/cpu.h | 4
The 68000 does not support the MOVEC instruction, it was added with the 68010.
A new 68010 CPU class was created, and the MOVEC instruction moved to that
class.
Futher on the 68010, 68060 and CPU32 the ISP doesnt exist.
These CPUs only have SSP/USP.
(NOTE: ColdFire has a different MOVEC helper, t
Hello,
I am interested in understanding on how QEMU maps the user and kernel
pages of a guest OS to the host OS memory (working on 3.1.0 but any
version is acceptable with target x86-64 arch).
Since QEMU runs on user space, these pages will be also mapped on the
user space of the host machine. S
Patchew URL:
https://patchew.org/QEMU/20190616123751.781-1-mark.cave-ayl...@ilande.co.uk/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v3 00/15] target/ppc: remove getVSR()/putVSR() and
further tidy-up
Type: ser
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