On 2019/2/14 下午12:26, w...@redhat.com wrote:
From: Wei Xu
last_used_idx/wrap_counter should be equal to last_avail_idx/wrap_counter
after a successful flush.
Batching in vhost-net & dpdk testpmd is not equivalently supported in
userspace backend, but a chained descriptors for Rx is similarly
On 2019/2/14 下午12:26, w...@redhat.com wrote:
From: Wei Xu
Add packed ring headcount check.
Common part of split/packed ring are kept.
Signed-off-by: Wei Xu
---
hw/virtio/virtio.c | 197 -
1 file changed, 179 insertions(+), 18 deletions
It took a few days but last night the problem was reproduced.
This is the information from the log:
vdev 0x55f261d940f0 ("virtio-blk")
vq 0x55f261d9ee40 (idx 0)
inuse 128 vring.num 128
old_shadow_avail_idx 58874 last_avail_idx 58625 avail_idx 58874
avail 0x3d87a800 avail_idx (cache bypassed) 58625
On 2/18/19 12:37 AM, David Gibson wrote:
> On Fri, Feb 15, 2019 at 02:35:03PM +0100, Cédric Le Goater wrote:
>> On 2/15/19 2:18 PM, Greg Kurz wrote:
>>> On Fri, 15 Feb 2019 13:55:53 +0100
>>> Cédric Le Goater wrote:
>>>
On 2/15/19 12:40 PM, Greg Kurz wrote:
> The KVM ICP class isn't used
> From: Aleksandar Markovic [mailto:amarko...@wavecomp.com]
> > From: Pavel Dovgalyuk [mailto:pavel.dovga...@ispras.ru]
> >
> > This patch enables QMP-based querying of the available CPU types for MIPS
> > and MIPS64 platforms.
> >
> > Signed-off-by: Pavel Dovgalyuk
> > ---
> > monitor.c
> From: Pavel Dovgalyuk [mailto:pavel.dovga...@ispras.ru]
> Sent: Tuesday, February 05, 2019 4:08 PM
> To: qemu-devel@nongnu.org
> Cc: pavel.dovga...@ispras.ru; arik...@wavecomp.com; mdr...@linux.vnet.ibm.com;
> arm...@redhat.com; dovga...@ispras.ru; natalia.furs...@ispras.ru;
> ebl...@redhat.com;
On Fri, Feb 15, 2019 at 06:00:18PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> The HW relies on LPCR:HR along with the PATE to determine whether
> to use Radix or Hash mode. In fact it uses LPCR:HR more commonly
> than the PATE.
>
> For us, it's also more efficient to do so
> From: Markus Armbruster [mailto:arm...@redhat.com]
> dovgaluk writes:
>
> > Markus Armbruster писал 2019-02-12 10:14:
> >> "Pavel Dovgalyuk" writes:
> >>
> >>> Ping?
> >>
> >> Are you pinging for more review, or for someone to merge this?
> >
> > From my point of view this patch set is ready.
Hi Marcel and Igor,
Thanks very much for your help!
On 2/14/2019 10:42 PM, Marcel Apfelbaum wrote:
[...]
I have two questions.
1. PCI hotplug on pci.0 must manually rescan in guest. The ACPI
hotplug
handler sends the GPE event to guest but it seems guest doesn't
receive
it? I tried to ope
On 2019/2/16 上午1:46, Vincenzo Maffione wrote:
Hi,
I was doing experiments with a custom paravirtualized net device,
and I ran into a limitation of the TAP backend. I see from the kernel
code that it is not possible to set the TAP virtio-net header
length to something different from 10 or 12,
On Fri, Feb 15, 2019 at 11:09:32PM +0100, David Hildenbrand wrote:
> On 15.02.19 22:27, Michael S. Tsirkin wrote:
> > On Fri, Feb 15, 2019 at 02:29:59PM +0100, David Hildenbrand wrote:
> >> This is a set of tests to test basic device unplugging functionality for
> >> - some PCI implementations
> >>
On Fri, Feb 15, 2019 at 04:56:53PM +0100, Thomas Huth wrote:
> On 15/02/2019 14.30, David Hildenbrand wrote:
> > We can easily test this, just like PCI.
> >
> > Signed-off-by: David Hildenbrand
> > ---
> > tests/device-plug-test.c | 21 +
> > 1 file changed, 21 insertions(+)
On 2019/2/13 下午10:51, Yuri Benditovich wrote:
https://bugzilla.redhat.com/show_bug.cgi?id=1608226
On startup/link-up in multiqueue configuration the virtio-net
tries to starts all the queues, including those that the guest
will not enable by VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET.
If the guest driver
At least two machines, the PPC mac99 and MIPS fulong2e, have an ATI
gfx chip by default (Rage 128 Pro and M6/RV100 respectively) and
guests running on these and the PMON2000 firmware of the fulong2e
expect this to be available. Fortunately these are very similar chips
so they can be mostly emulated
On Fri, Feb 15, 2019 at 02:30:02PM +0100, David Hildenbrand wrote:
> The issue with testing asynchronous unplug requests it that they usually
> require a running guest to handle the request. However, to test if
> unplug of PCI devices works, we can apply a nice little trick on some
> architectures:
Currently we do device realization like below:
hotplug_handler_pre_plug()
dc->realize()
hotplug_handler_plug()
Before we do device realization and plug, we should allocate necessary
resources and check if memory-hotplug-support property is enabled.
At the piix4 and ich9, the acpi_memory
On Fri, Feb 15, 2019 at 02:30:01PM +0100, David Hildenbrand wrote:
> Fake availability of OV5_HP_EVT, so we can test memory unplug in qtest.
>
> Signed-off-by: David Hildenbrand
Kinda gross, but I don't see a better way of handling this quickly,
so,
Acked-by: David Gibson
> ---
> hw/ppc/spap
On Fri, Feb 15, 2019 at 12:40:18PM +0100, Greg Kurz wrote:
> The pre_save(), post_load() and synchronize_state() methods of the
> ICSStateClass type are really KVM only things. Make that obvious
> by dropping the indirections and directly calling the KVM functions
> instead.
>
> Signed-off-by: Gre
On Fri, Feb 15, 2019 at 10:00:41AM +, Mark Cave-Ayland wrote:
> Now that all the pre-requisite patches and bugfixes have been merged, here is
> the remainder of Richard's "tcg, target/ppc vector improvements" patchset that
> converts various PPC VMX/VSX instructions over to use TCG vector opera
On Fri, Feb 15, 2019 at 02:30:00PM +0100, David Hildenbrand wrote:
> This enables CPU unplug under qtest.
>
> Signed-off-by: David Hildenbrand
Reviewed-by: David Gibson
> ---
> cpus.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/cpus.c b/cpus.c
> index 154daf57dc..e83f72b48b 1006
On Fri, Feb 15, 2019 at 04:41:09PM +0530, Shivaprasad G Bhat wrote:
> Thanks for the comments David. Please find my replies inline..
>
>
> On 02/12/2019 07:19 AM, David Gibson wrote:
> > On Tue, Feb 05, 2019 at 11:26:27PM -0600, Shivaprasad G Bhat wrote:
> > > Add support for NVDIMM devices for s
On Fri, Feb 15, 2019 at 12:40:30PM +0100, Greg Kurz wrote:
> We want to use the "simple" ICS type in both KVM and non-KVM setups.
> Teach the "simple" ICS how to present interrupts to KVM and adapt
> sPAPR accordingly.
>
> Signed-off-by: Greg Kurz
As Cédric points out, not strictly required to a
On Fri, Feb 15, 2019 at 12:40:35PM +0100, Greg Kurz wrote:
> The "simple" ICS class knows how to interract with KVM. Adapt sPAPR to use
> it instead of the ICS KVM class.
>
> Signed-off-by: Greg Kurz
> ---
> hw/ppc/spapr_irq.c | 15 +++
> 1 file changed, 7 insertions(+), 8 deletion
On Fri, Feb 15, 2019 at 12:40:24PM +0100, Greg Kurz wrote:
> The KVM ICS reset handler simply writes the ICS state to KVM. This
> doesn't need the overkill parent_reset logic we have today. Also
> we want to use the same ICS type for the KVM and non-KVM case with
> pseries.
>
> Call icp_set_kvm_st
On Fri, Feb 15, 2019 at 02:02:16PM +0100, Cédric Le Goater wrote:
> On 2/15/19 12:40 PM, Greg Kurz wrote:
> > The "simple" ICS class knows how to interract with KVM. Adapt sPAPR to use
> > it instead of the ICS KVM class.
>
> You are changing the type name. What about migration ?
As with ICP this
On Fri, Feb 15, 2019 at 02:35:03PM +0100, Cédric Le Goater wrote:
> On 2/15/19 2:18 PM, Greg Kurz wrote:
> > On Fri, 15 Feb 2019 13:55:53 +0100
> > Cédric Le Goater wrote:
> >
> >> On 2/15/19 12:40 PM, Greg Kurz wrote:
> >>> The KVM ICP class isn't used anymore. Drop it.
> >>
> >> Isn't migrati
On Fri, Feb 15, 2019 at 12:39:48PM +0100, Greg Kurz wrote:
> The pre_save(), post_load() and synchronize_state() methods of the
> ICPStateClass type are really KVM only things. Make that obvious
> by dropping the indirections and directly calling the KVM functions
> instead.
>
> Signed-off-by: Gre
On Fri, Feb 15, 2019 at 02:27:41PM +0100, Greg Kurz wrote:
> On Fri, 15 Feb 2019 14:09:53 +0100
> Cédric Le Goater wrote:
>
> > On 2/15/19 2:03 PM, Greg Kurz wrote:
> > > On Fri, 15 Feb 2019 13:54:02 +0100
> > > Cédric Le Goater wrote:
> > >
> > >> On 2/15/19 12:40 PM, Greg Kurz wrote:
> >
On Fri, Feb 15, 2019 at 12:40:06PM +0100, Greg Kurz wrote:
> The base ICP class knows how to interact with KVM. Adapt sPAPR to use it
> instead of the ICP KVM class.
>
> Signed-off-by: Greg Kurz
Applied, thanks.
> ---
> hw/ppc/spapr_irq.c |4 +---
> include/hw/ppc/spapr.h |1 -
> 2
On Fri, Feb 15, 2019 at 12:39:54PM +0100, Greg Kurz wrote:
> The KVM ICP reset handler simply writes the ICP state to KVM. This
> doesn't need the overkill parent_reset logic we have today. Call
> icp_set_kvm_state() from the base ICP reset function instead.
>
> Since there are no other users for
On 2/14/19 4:51 AM, Peter Maydell wrote:
> Wire up the two PL011 UARTs in the Musca board.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/musca.c | 34 +-
> 1 file changed, 29 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 2/14/19 4:51 AM, Peter Maydell wrote:
> Wire up the PL031 RTC for the Musca board.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/musca.c | 26 +++---
> 1 file changed, 23 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 2/17/19 10:14 AM, Richard Henderson wrote:
> On 2/14/19 4:51 AM, Peter Maydell wrote:
>> +const PPCPortInfo devices[] = {
>> +const PPCInfo a_ppcs[] = { {
>> +const PPCInfo b1_ppcs[] = { {
>
> static const for all of these. Otherwise,
... but of course in subsequent patches you pu
On 2/14/19 4:51 AM, Peter Maydell wrote:
> The Musca board puts its SRAM and flash behind TrustZone
> Memory Protection Controllers (MPCs). Each MPC sits between
> the CPU and the RAM/flash, and also has a set of memory mapped
> control registers. Wire up the MPCs, and the memory behind them.
> For
On 2/14/19 4:51 AM, Peter Maydell wrote:
> +const PPCPortInfo devices[] = {
> +const PPCInfo a_ppcs[] = { {
> +const PPCInfo b1_ppcs[] = { {
static const for all of these. Otherwise,
Reviewed-by: Richard Henderson
r~
On 2/14/19 4:51 AM, Peter Maydell wrote:
> The Musca-A and Musca-B1 development boards are based on the
> SSE-200 subsystem for embedded. Implement an initial skeleton
> model of these boards, which are similar but not identical.
>
> This commit creates the board model with the SSE and the IRQ
> s
On 2/14/19 4:51 AM, Peter Maydell wrote:
> The pl011 logs when the guest makes a bad access. It prints
> the address offset in hex but confusingly omits the '0x'
> prefix; add it.
>
> Signed-off-by: Peter Maydell
> ---
> hw/char/pl011.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
On 2/14/19 4:51 AM, Peter Maydell wrote:
> The Musca boards have DAPLink firmware that sets the initial
> secure VTOR value (the location of the vector table) differently
> depending on the boot mode (from flash, from RAM, etc). Export
> the init-svtor as a QOM property of the ARMSSE object so that
On 2/14/19 4:51 AM, Peter Maydell wrote:
> In commit 4b635cf7a95e501211 we added a QOM property to the ARMSSE
> object, but forgot to add it to the documentation comment in the
> header. Correct the omission.
>
> Fixes: 4b635cf7a95e501211 ("hw/arm/armsse: Make SRAM bank size configurable")
> Signe
On 2/14/19 4:50 AM, Peter Maydell wrote:
> The PL011 UART has six interrupt lines:
> * RX (receive data)
> * TX (transmit data)
> * RT (receive timeout)
> * MS (modem status)
> * E (errors)
> * combined (logical OR of all the above)
>
> So far we have only emulated the combined interrupt lin
On 2/14/19 4:50 AM, Peter Maydell wrote:
> Create a new include file for the pl011's device struct,
> type macros, etc, so that it can be instantiated using
> the "embedded struct" coding style.
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/char/pl011.h | 34 +++
On 2/14/19 4:50 AM, Peter Maydell wrote:
> Convert the debug printing in the PL031 device to use trace events,
> and augment it to cover the interesting parts of device operation.
>
> Signed-off-by: Peter Maydell
> ---
> hw/timer/pl031.c | 55 +++
> h
On 2/14/19 4:50 AM, Peter Maydell wrote:
> Create a new include file for the pl031's device struct,
> type macros, etc, so that it can be instantiated using
> the "embedded struct" coding style.
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/timer/pl031.h | 44 ++
On 2/14/19 4:50 AM, Peter Maydell wrote:
> The Peripheral Protection Controller's handling of unused ports
> is that if there is nothing connected to the port's downstream
> then it does not create the sysbus MMIO region for the upstream
> end of the port. This results in odd behaviour when there i
On 2/14/19 3:34 AM, Peter Maydell wrote:
> The "background region" for a v8M MPU is a default which will be used
> (if enabled, and if the access is privileged) if the access does
> not match any specific MPU region. We were incorrectly using it
> always (by putting the condition at the wrong nesti
On 2/14/19 4:50 AM, Peter Maydell wrote:
> In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
> the ARMSSE, we set up the wiring of the expansion IRQs via nested
> loops: the outer loop on 'i' loops for each CPU, and the inner loop
> on 'j' loops for each interrupt. Fix a typo which m
If SIGP is set, the 'Wait for Reselection' command should jump
immediately to the address stored in the second DWORD of the
instruction. This fixes spurious hangs in the HP-UX 11.11
installer when the SIGP bit gets set by the kernel before the
'Wait for Reselection' command is executed by SCRIPTS.
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