On 1/7/19 20:11, Stefano Garzarella wrote:
Hi,
On Thu, Dec 27, 2018 at 9:32 PM Eduardo Habkost wrote:
On Fri, Dec 21, 2018 at 11:10:30AM -0500, Michael S. Tsirkin wrote:
On Thu, Dec 06, 2018 at 10:32:13AM +0800, Li Zhijian wrote:
a new field xloadflags was added to recent x86 linux, and BIT
Patchew URL:
https://patchew.org/QEMU/20190108223129.5570-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth
Type: series
Message-id: 201901
On 1/7/2019 6:25 PM, Michael S. Tsirkin wrote:
On Mon, Jan 07, 2019 at 05:45:22PM -0800, si-wei liu wrote:
On 01/07/2019 03:32 PM, Michael S. Tsirkin wrote:
On Mon, Jan 07, 2019 at 05:29:39PM -0500, Venu Busireddy wrote:
Implement the infrastructure to support datapath switching during live
We only have one caller that wants to export a bitmap name,
which it does right after creation of the export. But there is
still a brief window of time where an NBD client could see the
export but not the dirty bitmap, which a robust client would
have to interpret as meaning the entire image should
On Wed, Jan 09, 2019 at 08:39:07AM +0800, Dongli Zhang wrote:
> Hi Samudrala,
>
> On 2019/1/9 上午8:18, Samudrala, Sridhar wrote:
> > On 1/8/2019 4:14 PM, Dongli Zhang wrote:
> >> Hi Venu,
> >>
> >> On 2019/1/9 上午1:25, Venu Busireddy wrote:
> >>> On 2019-01-09 00:56:38 +0800, Dongli Zhang wrote:
> >
With the experimental x-nbd-server-add-bitmap command, there was
a window of time where a client could see the export but not the
associated dirty bitmap, which can cause a client that planned
on using the dirty bitmap to be forced to treat the entire image
as dirty as a safety fallback. Furthermo
Now that nbd-server-add can do the same functionality, we no
longer need the experimental separate command.
Signed-off-by: Eric Blake
---
qapi/block.json | 23 ---
blockdev-nbd.c | 23 ---
2 files changed, 46 deletions(-)
diff --git a/qapi/block.json b/q
Having to fire up qemu, then use QMP commands for nbd-server-start
and nbd-server-add, just to expose a persistent dirty bitmap, is
rather tedious. Make it possible to expose a dirty bitmap using
just qemu-nbd (of course, for now this only works when qemu-nbd is
visiting a BDS formatted as qcow2).
The existing NBD code had a weird split where nbd_export_new()
created an export but did not add it to the list of exported
names until a later nbd_export_set_name() came along and grabbed
a second reference on the object; later, nbd_export_close()
drops the second reference. But since we never ch
Or rather, move its functionality into nbd-server-add. And as
a side effect, teach qemu-nbd how to export a persistent bitmap
without having to go through a qemu process and several QMP
commands.
Based-on: <20181221093529.23855-1-js...@redhat.com>
[0/11 bitmaps: remove x- prefix from QMP api]
Pa
On Thu, Jan 03, 2019 at 05:27:24PM +0100, BALATON Zoltan wrote:
> The last code patch in this series fixes memory size larger than 1GB
> for sam460ex, other patches are just clean ups I've made along the way.
>
> The first patch is intended to be generic and may be useful for other
> boards which
On 2019/1/8 20:46, Kevin Wolf wrote:
> Am 29.12.2018 um 07:33 hat Ying Fang geschrieben:
>> Hi.
>> Recently one of our customer complained about the I/O performance of QEMU
>> emulated host cdrom device.
>> I did some investigation on it and there was still some point I could not
>> figure out
Thanks, Gerd.
On Tue, 8 Jan 2019 at 23:54, Gerd Hoffmann wrote:
>
> From: Hongbo Zhang
>
> This patch introduces a new system bus generic EHCI controller.
> For the system bus EHCI controller, we've already had "xlnx",
> "exynos4210", "tegra2", "ppc4xx" and "fusbh200", they are specific and
> on
On Tue, Jan 08, 2019 at 08:23:50AM -0700, Alex Williamson wrote:
> On Tue, 8 Jan 2019 19:47:20 +0800
> Peter Xu wrote:
>
> > In Linux version v4.15+ there's a bug (introduced in 71a7d3d78e3c,
> > "vfio/type1: silence integer overflow warning", 2017-10-20) that could
> > potentially reject a vali
On 12/21/18 3:35 AM, John Snow wrote:
> New interface, new smoke test.
>
> Signed-off-by: John Snow
> Reviewed-by: Vladimir Sementsov-Ogievskiy
> Reviewed-by: Eric Blake
> ---
> tests/qemu-iotests/236 | 161 +
> tests/qemu-iotests/236.out | 351 +
From: Li Feng
When the IO size is larger than 2 pages, we move the the pointer one by
one in the pagelist, this is inefficient.
This is a simple benchmark result:
Before:
$ qemu-io -c 'write 0 1G' nvme://:00:04.0/1
wrote 1073741824/1073741824 bytes at offset 0
1 GiB, 1 ops; 0:00:02.41 (424
From: Philippe Mathieu-Daudé
The Debian Sid repository is not garanteed to be stable, as his
'unstable' name suggest :)
To allow quick testing, Debian maintainers might push packages
various time a day. Sometime package dependencies might break,
which is annoying when using this repository for s
The following changes since commit 147923b1a901a0370f83a0f4c58ec1baffef22f0:
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190108-pull-request'
into staging (2019-01-08 16:07:32 +)
are available in the git repository at:
https://github.com/famz/qemu.git tags/st
Hi Samudrala,
On 2019/1/9 上午8:18, Samudrala, Sridhar wrote:
> On 1/8/2019 4:14 PM, Dongli Zhang wrote:
>> Hi Venu,
>>
>> On 2019/1/9 上午1:25, Venu Busireddy wrote:
>>> On 2019-01-09 00:56:38 +0800, Dongli Zhang wrote:
I am not familiar with libvirt and I would like to play with this only
On 1/8/2019 4:14 PM, Dongli Zhang wrote:
Hi Venu,
On 2019/1/9 上午1:25, Venu Busireddy wrote:
On 2019-01-09 00:56:38 +0800, Dongli Zhang wrote:
I am not familiar with libvirt and I would like to play with this only with
qemu.
With failover, we need to hotplug the VF on destination server to VM
Hi Venu,
On 2019/1/9 上午1:25, Venu Busireddy wrote:
> On 2019-01-09 00:56:38 +0800, Dongli Zhang wrote:
>> I am not familiar with libvirt and I would like to play with this only with
>> qemu.
>>
>> With failover, we need to hotplug the VF on destination server to VM after
>> live
>> migration. Ho
On Tue, 8 Jan 2019 at 18:23, Paolo Bonzini wrote:
>
> The following changes since commit 147923b1a901a0370f83a0f4c58ec1baffef22f0:
>
> Merge remote-tracking branch
> 'remotes/kraxel/tags/usb-20190108-pull-request' into staging (2019-01-08
> 16:07:32 +)
On Tue, 8 Jan 2019 at 22:32, Richard Henderson
wrote:
>
> Not that there are any stores involved, but why argue with ARM's
> naming convention.
>
> Signed-off-by: Richard Henderson
> ---
> v3: Use do_gpr_ld; fix sextend typo; iss_valid only for !wback.
What was the sextend typo ?
> ---
> targe
On Tue, 8 Jan 2019 at 22:31, Richard Henderson
wrote:
>
> This path uses cpu_loop_exit_restore to unwind current processor state.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target/arm/internals.h | 7 +++
> target/arm/op_helper.c | 19 +--
>
From: Cédric Le Goater
The error value can be squashed by the section handling radix migration.
Simply bail out if an error occurs when the RTC offset is imported.
This fixes the Coverity issue CID 1398591.
Fixes: d39c90f5f3ae ("spapr: Fix migration of Radix guests")
Signed-off-by: Cédric Le Go
From: Cédric Le Goater
Now that the 'intc' pointer is only used by the XICS interrupt mode,
let's make things clear and use a XICS type and name.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics_spapr.c| 10 +-
hw/ppc/pnv.c| 6 +++---
hw/pp
On Tue, 8 Jan 2019 at 22:31, Richard Henderson
wrote:
>
> The cryptographic internals are stubbed out for now,
> but the enable and trap bits are checked.
>
> Signed-off-by: Richard Henderson
>
> v2: Remove trap from xpac* helpers; these are now side-effect free.
> Use struct ARMPACKey.
From: Cédric Le Goater
The qemu_irq array is now allocated at the machine level using a sPAPR
IRQ set_irq handler depending on the chosen interrupt mode. The use of
this handler is slightly inefficient today but it will become necessary
when the 'dual' interrupt mode is introduced.
Signed-off-by
From: Cédric Le Goater
Depending on the interrupt mode of the machine, enable or disable the
XIVE MMIOs.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/spapr_xive.c| 9 +
hw/ppc/spapr_irq.c | 9 +
include/hw/ppc/spapr_xive.h | 1 +
3 f
From: Mark Cave-Ayland
These helpers allow us to move FP register values to/from the specified TCGv_i64
argument in the VSR helpers to be introduced shortly.
To prevent FP helpers accessing the cpu_fpr array directly, add extra TCG
temporaries as required.
Signed-off-by: Mark Cave-Ayland
Revie
From: Cédric Le Goater
To support the 'dual' interrupt mode, XICS and XIVE, we plan to move
the qemu_irq array of each interrupt controller under the machine and
do the allocation under the sPAPR IRQ init method.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c
From: Cédric Le Goater
Today, the interrupt presenter is linked to a CPU using the
cpu_intc_create() method of the sPAPR IRQ backend. The resulting
object is assigned to the PowerPCCPU 'intc' pointer whatever the
interrupt mode, XICS or XIVE.
To support the 'dual' interrupt mode, we will need to
From: Cédric Le Goater
The 'dual' sPAPR IRQ backend supports both interrupt mode, XIVE
exploitation mode and the legacy compatibility mode (XICS). both modes
are not supported at the same time.
The machine starts with the legacy mode and a new interrupt mode can
then be negotiated by the CAS pro
From: Cédric Le Goater
The qirq routines of the XiveSource and the sPAPRXive model are only
used under the sPAPR IRQ backend. Simplify the overall call stack and
gather all the code under spapr_qirq_xive(). It will ease future
changes.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
From: Cédric Le Goater
Future changes of the ICSState object will remove the qemu_irq array
from under the interrupt controller model. Prepare ground for the PSI
interrupt sources and introduce a new one directly under the PSI
device model.
Signed-off-by: Cédric Le Goater
Signed-off-by: David G
From: Michael Roth
This adds cleanup counterparts to pci_register_root_bus(),
pci_root_bus_new(), and pci_bus_irqs().
These cleanup routines are needed in the case of hotpluggable
PCIHostBridge implementations. Currently we can rely on the
object_unparent()'ing of the PCIHostState recursively un
From: Cédric Le Goater
commit 15ed653fa49a ("ppc/xics: An ICS with offset 0 is assumed to be
uninitialized") introduced an extra check on the ICS offset which is
not strictly necessary.
Revert the change to be able to map the XICS IRQ number space on the
XIVE IRQ number space.
Signed-off-by: Cé
From: Cédric Le Goater
which will be used by the machine only when the XIVE interrupt mode is
in use.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xive.c | 6 +++---
hw/ppc/spapr_cpu_core.c | 7 ++-
hw/ppc/spapr_irq.c | 8
target/ppc/cpu.h
From: Mark Cave-Ayland
The VSX register array is a block of 64 128-bit registers where the first 32
registers consist of the existing 64-bit FP registers extended to 128-bit
using new VSR registers, and the last 32 registers are the VMX 128-bit
registers as show below:
64-bit
From: Mark Cave-Ayland
These helpers allow us to move VSR register values to/from the specified
TCGv_i64
argument.
To prevent VSX helpers accessing the cpu_vsr array directly, add extra TCG
temporaries as required.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Acked-by: Davi
From: Mark Cave-Ayland
Since the VSX registers are actually a superset of the VMX registers then they
can be represented by the same type. Merge ppc_avr_t into ppc_vsr_t and change
ppc_avr_t to be a simple typedef alias.
Note that due to a difference in the naming of the float32 member between
p
From: Greg Kurz
PHB hotplug will bring more users for it. Let's define it along with
the PHB defines from which it is derived for simplicity.
While here fix a misleading comment about manual placement, which was
abandoned with 30b3bc5aa9f4.
Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goate
From: Greg Kurz
This function is only used when creating the default PHB. Let's rename
it and move it to the core machine code for clarity.
Signed-off-by: Greg Kurz
Reviewed-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 13 +
From: Mark Cave-Ayland
Instead of accessing the FPR, VMX and VSX registers through static arrays of
TCGv_i64 globals, remove them and change the helpers to load/store data directly
within cpu_env.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Acked-by: David Gibson
Signed-off
From: Mark Cave-Ayland
The VGA driver built from Ben's QemuMacDrivers repository is used exclusively
by the Mac machines.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAIN
From: Thomas Huth
hw/gpio/mpc8xxx.c is only used by the e500 machine, so add it there.
And the hw/input/adb* files are specific to the Mac machines, so
they should be assigned to these categories.
Signed-off-by: Thomas Huth
Signed-off-by: David Gibson
---
MAINTAINERS | 9 +++--
1 file cha
From: Mark Cave-Ayland
Now that the VMX and VSR register sets have been combined, the same macros can
be used to access both AVR and VSR field members.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/int_helper.c | 30 +---
From: Mark Cave-Ayland
These ensure that we consistently handle signed and unsigned extensions
correctly
when decoding immediates from instruction opcodes.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/internal.h | 8
1 fi
From: Mark Cave-Ayland
These helpers allow us to move AVR register values to/from the specified
TCGv_i64
argument.
To prevent VMX helpers accessing the cpu_avr{l,h} arrays directly, add extra TCG
temporaries as required.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Acked-by
From: Alexey Kardashevskiy
SLOF receives a device tree and updates it with various properties
before switching to the guest kernel and QEMU is not aware of any changes
made by SLOF. Since there is no real RTAS (QEMU implements it), it makes
sense to pass the SLOF final device tree to QEMU to let
From: BALATON Zoltan
Debug logs were left enabled in ppc4xx_devs.c whereas in other files
these are normally not enabled. Disable it here as well.
Signed-off-by: BALATON Zoltan
Signed-off-by: David Gibson
---
hw/ppc/ppc4xx_devs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff -
The following changes since commit 147923b1a901a0370f83a0f4c58ec1baffef22f0:
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190108-pull-request'
into staging (2019-01-08 16:07:32 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/p
Add 4 attributes that controls the EL1 enable bits, as we may not
always want to turn on pointer authentication with -cpu max.
However, by default they are enabled.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 3 +++
target/arm/cpu64.c | 60 +
Use TBID in aa64_va_parameters depending on the data parameter.
This automatically updates all existing users of the function.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 1 +
target/arm/helper.c| 14 +++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff -
From: Mark Cave-Ayland
As the macro name suggests, the argument should be signed and not unsigned.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/p
From: Laurent Vivier
H_HOME_NODE_ASSOCIATIVITY H-Call returns the associativity domain
designation associated with the identifier input parameter
This fixes a crash when we try to hotplug a CPU in memory-less and
CPU-less numa node. In this case, the kernel tries to online the
node, but without
This is the main crypto routine, an implementation of QARMA.
This matches, as much as possible, ARM pseudocode.
Signed-off-by: Richard Henderson
---
target/arm/pauth_helper.c | 241 +-
1 file changed, 240 insertions(+), 1 deletion(-)
diff --git a/target/arm/p
We can perform this with fewer operations.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
v3: Update for tbii = tbi1:tbi0.
---
target/arm/translate-a64.c | 62 +-
1 file changed, 21 insertions(+), 41 deletions(-)
diff --git a/target/arm/tra
We will want to check TBI for I and D simultaneously.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 15 ---
target/arm/helper.c| 10 --
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 82
From: BALATON Zoltan
The sm501 model belonged to SH before but that seems to be inactive
now and latest changes were for sam460ex which is the more active user
of this device at the moment so let's adopt sm501 for sam460ex.
Also add device tree and firmware sources and binaries.
Signed-off-by:
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4b544a1c58..1974f1aeb7 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -316,6 +316,10 @@ static voi
We will shortly want to talk about TBI as it relates to data.
Passing around a pair of variables is less convenient than a
single variable.
Signed-off-by: Richard Henderson
v3: New, split out of a later patch set.
---
target/arm/cpu.h | 3 +--
target/arm/translate.h | 3 +--
Stripping out the authentication data does not require any crypto,
it merely requires the virtual address parameters.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/pauth_helper.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/targ
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
v3: Fix typos.
---
target/arm/helper.c | 70 +
1 file changed, 70 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e610155166..0e1bf521ab 100644
--- a/target/ar
This function is, or will shortly become, too big to inline.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 48 +
target/arm/helper.c | 44 +
2 files changed, 49 insertions
We need to reuse this from helper-a64.c. Provide a stub
definition for CONFIG_USER_ONLY. This matches the stub
definitions that we removed for arm_regime_tbi{0,1} before.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 17 +
target/arm/
While we could expose stage_1_mmu_idx, the combination is
probably going to be more useful.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 15 +++
target/arm/helper.c| 7 +++
2 files changed, 22 insertions(+)
diff --git a/target/ar
This is not really functional yet, because the crypto is not yet
implemented. This, however follows the AddPAC pseudo function.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
v3: Use MAKE_64BIT_MASK one more place.
---
target/arm/pauth_helper.c | 42 ++
Split out functions to extract the virtual address parameters.
Let the functions choose T0 or T1 address space half, if present.
Extract (most of) the control bits that vary between EL or Tx.
Signed-off-by: Richard Henderson
v2: Incorporate feedback wrt VTCR, HTCR, and more.
v3: Remove TBID,
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 82 +-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e601753032..fa50003f0b 100644
--- a/
Not that there are any stores involved, but why argue with ARM's
naming convention.
Signed-off-by: Richard Henderson
---
v3: Use do_gpr_ld; fix sextend typo; iss_valid only for !wback.
---
target/arm/translate-a64.c | 60 ++
1 file changed, 60 insertions(+)
d
This is not really functional yet, because the crypto is not yet
implemented. This, however follows the Auth pseudo function.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/pauth_helper.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
d
The pattern
ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
is computing the full ARMMMUIdx, stripping off the ARM bits,
and then putting them back.
Avoid the extra two steps with the appropriate helper function.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Hend
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 2 +-
target/arm/helper-a64.c| 10 +-
target/arm/translate-a64.c | 7 ++-
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64
This function is only used by AArch64. Code movement only.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h | 2 +
target/arm/helper.h | 1 -
target/arm/helper-a64.c | 155
target/arm/op_helper.c | 155 ---
The arm_regime_tbi{0,1} functions are replacable with the new function
by giving the lowest and highest address.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Use aa64_va_parameters_both and compute both tbii and tbid.
Merged back from a later patch set.
---
target/arm
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8a8408c1b7..3f08db580b 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/tra
Now properly signals unallocated for REV64 with SF=0.
Allows for the opcode2 field to be decoded shortly.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git
The cryptographic internals are stubbed out for now,
but the enable and trap bits are checked.
Signed-off-by: Richard Henderson
v2: Remove trap from xpac* helpers; these are now side-effect free.
Use struct ARMPACKey.
v3: Move code to pauth_helper.c; use raise_exception_ra.
---
target/a
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 146 +
1 file changed, 146 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index dac61a3c3a..8a8408c1b7 100644
--- a/target/arm/tra
This will enable PAuth decode in a subsequent patch.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 47 +-
1 file changed, 36 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2df23236
There are 5 bits of state that could be added, but to save
space within tbflags, add only a single enable bit.
Helpers will determine the rest of the state at runtime.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
v2: Fix whitespace, comment grammar.
v3: Rebase on FIELD defini
Post v8.4 bits taken from SysReg_v85_xml-00bet8.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
v2: Review fixups from Peter.
---
target/arm/cpu.h | 45 +
1 file changed, 33 insertions(+), 12 deletions(-)
diff --git a/target/arm/cpu
This path uses cpu_loop_exit_restore to unwind current processor state.
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 7 +++
target/arm/op_helper.c | 19 +--
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/target/a
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Use binary literals.
---
target/arm/translate-a64.c | 93 +-
1 file changed, 81 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 37a57
Add storage space for the 5 encryption keys.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
v2: Remove pointless double migration.
Use a struct to make it clear which half is which.
---
target/arm/cpu.h | 30 +-
1 file changed, 29 insertions(+),
Lots more little changes since v2, mostly from Peter's review.
Some changes to ARMVAParameters and TBI incorporated from other
patch sets that I've been working on.
Not included are patches for linux-user to match the user-level
code that has gone into kernel mainline. But this patch set is
big e
On 08.01.19 20:52, Tony Krowiak wrote:
> On 1/8/19 11:09 AM, David Hildenbrand wrote:
>> On 08.01.19 17:01, Tony Krowiak wrote:
>>> Introduces hot plug/unplug support for the vfio-ap device. Note that only
>>> one
>>> vfio-ap device can be attached to the ap-bus, so a vfio-ap device can only
>>>
Works, thanks!
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1810545
Title:
[alpha] Strange exception address reported
Status in QEMU:
Fix Committed
Bug description:
For some reason the SIGIL
Patchew URL:
https://patchew.org/QEMU/20190108162154.22259-1-alex.ben...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v1 0/6] current fpu/next queue
Message-id: 20190108162154.22259-1-al
Hi Palmer,
On Tue, Jan 8, 2019 at 11:37 AM Palmer Dabbelt wrote:
> It looks like I don't have an account and I'm supposed to ask on qemu-devel
> for
> one.
I've created an account for you. Will send details in private e-mail.
--
Thanks.
-- Max
On 1/8/19 12:06 PM, Cornelia Huck wrote:
On Tue, 8 Jan 2019 17:50:21 +0100
Halil Pasic wrote:
On Tue, 8 Jan 2019 17:31:13 +0100
Cornelia Huck wrote:
On Tue, 8 Jan 2019 11:08:56 -0500
Tony Krowiak wrote:
On 12/17/18 10:57 AM, Tony Krowiak wrote:
The qbus_is_full(BusState *bus) functio
On 1/8/19 9:17 PM, Marc-André Lureau wrote:
> On Tue, Jan 8, 2019 at 11:25 PM Stefan Berger wrote:
>>
>> On 1/8/19 3:40 AM, Marc-André Lureau wrote:
>>> Note: the "Platform Reset Attack Mitigation" specification isn't
>>> explicit about NVDIMM, since they could have different usages. It uses
>>> t
Hi
On Tue, Jan 8, 2019 at 11:25 PM Stefan Berger wrote:
>
> On 1/8/19 3:40 AM, Marc-André Lureau wrote:
> > Note: the "Platform Reset Attack Mitigation" specification isn't
> > explicit about NVDIMM, since they could have different usages. It uses
> > the term "system memory" generally (and also
On 1/8/19 1:45 PM, Vladimir Sementsov-Ogievskiy wrote:
> bdrv_co_block_status digs bs->file for additional, more accurate search
> for hole inside region, reported as DATA by bs since 5daa74a6ebc.
>
> This accuracy is not free: assume we have qcow2 disk. Actually, qcow2
> knows, where are holes an
On 1/8/19 11:09 AM, David Hildenbrand wrote:
On 08.01.19 17:01, Tony Krowiak wrote:
Introduces hot plug/unplug support for the vfio-ap device. Note that only one
vfio-ap device can be attached to the ap-bus, so a vfio-ap device can only be
hot plugged if the '-device vfio-ap,sysfsdev=$path_to_md
bdrv_co_block_status digs bs->file for additional, more accurate search
for hole inside region, reported as DATA by bs since 5daa74a6ebc.
This accuracy is not free: assume we have qcow2 disk. Actually, qcow2
knows, where are holes and where is data. But every block_status
request calls lseek addit
On Thu, 03 Jan 2019 08:46:11 PST (-0800), Peter Maydell wrote:
On Wed, 26 Dec 2018 at 17:20, Palmer Dabbelt wrote:
The following changes since commit b72566a4ffaddbc0c0c1f6f5ee91b42ab13ff429:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' into staging (201
On 1/8/19 3:40 AM, Marc-André Lureau wrote:
Note: the "Platform Reset Attack Mitigation" specification isn't
explicit about NVDIMM, since they could have different usages. It uses
the term "system memory" generally (and also "volatile memory RAM" in
its introduction). For initial support, I propo
Proposed patch at https://patchwork.ozlabs.org/patch/1022092/
NB: my guess is that your pwrite on 32-bit arm test is behaving like
that because it isn't going via the pwrite64 syscall, or possibly
because glibc there is dealing with the NULL special case early. Use
QEMU's -strace argument (or stra
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