On 24 October 2018 at 00:41, Michael S. Tsirkin wrote:
> The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22'
> into staging (2018-10-23 17:20:23 +0100)
>
> are available in the Git repository a
Also remove unnecessary 'res' variable.
Signed-off-by: Li Qiang
---
hw/nvram/fw_cfg.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 946f765..f4a52d8 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -68,15 +68,14 @@
Peter Maydell writes:
> On 23 October 2018 at 14:04, Markus Armbruster wrote:
>> The following changes since commit b312532fd03413d0e6ae6767ec793a3e30f487b8:
>>
>> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
>> staging (2018-10-19 19:01:07 +0100)
>>
>> are available
在 2018/10/24 上午5:25, Cornelia Huck 写道:
On Mon, 22 Oct 2018 13:17:34 +0100
Thomas Huth wrote:
On 2018-10-22 10:02, Yi Min Zhao wrote:
Common function measurement block is used to report counters of
successfully issued pcilg/stg/stb and rpcit instructions. This patch
introduces a new struct
It makes sense to print the error message while reading
file failed.
Signed-off-by: Li Qiang
---
vl.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/vl.c b/vl.c
index b2a405f..ee6f982 100644
--- a/vl.c
+++ b/vl.c
@@ -2234,8 +2234,10 @@ static int parse_fw_cfg(void *opa
Stack pointer alignment code incorrectly adds stack_size to sp instead
of subtracting it. It also does not take flat_argvp_envp_on_stack() into
account when calculating stack_size. This results in initial stack
pointer misalignment with certain set of command line arguments and
environment variable
From: Li Qiang
Make them more QOMConventional.
Cc:qemu-triv...@nongnu.org
Signed-off-by: Li Qiang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci-host/piix.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
d
From: Laszlo Ersek
In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI
hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in
the ACPI DSDT that would be at least as large as the new "pci-hole64-size"
property (2GB on i440fx, 32GB on q35). The goal was to offer
From: yuchenlin
There are 3 virtqueues (ctrl, event and cmd) for virtio scsi device,
but seabios will only set the physical address for the 3rd one (cmd).
Then in vhost_virtqueue_start(), virtio_queue_get_desc_addr()
will be 0 for ctrl and event vq.
In this case, ctrl and event vq are not initia
From: Laszlo Ersek
In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI
hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in
the ACPI DSDT that would be at least as large as the new "pci-hole64-size"
property (2GB on i440fx, 32GB on q35). The goal was to offer
From: "Singh, Brijesh"
Now that amd-iommu support interrupt remapping, enable the GASup in IVRS
table and GASup in extended feature register to indicate that IOMMU
support guest virtual APIC mode. GASup provides option to guest OS to
make use of 128-bit IRTE.
Note that the GAMSup is set to zero
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci-bridge/ioh3420.h | 6 --
hw/pci-bridge/ioh3420.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
delete mode 100644 hw/pci-bridge/ioh342
From: Li Qiang
It seems that the intel link is unavailable, change it to point to the
qemu site.
Signed-off-by: Li Qiang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Marcel Apfelbaum
Acked-by: Michael S. Tsirkin
Reviewed-by: Michael S. Tsirkin
---
hw/pci-host/piix.c | 2 +-
1 file chang
From: "Singh, Brijesh"
Emulate the interrupt remapping support when guest virtual APIC is
enabled.
For more information refer: IOMMU spec rev 3.0 (section 2.2.5.2)
When VAPIC is enabled, it uses interrupt remapping as defined in
Table 22 and Figure 17 from IOMMU spec.
Signed-off-by: Brijesh Si
From: Philippe Mathieu-Daudé
Noted while refactoring:
CC mips-softmmu/hw/mips/gt64xxx_pci.o
In file included from include/hw/pci-host/gt64xxx.h:2,
from hw/mips/gt64xxx_pci.c:30:
include/hw/pci/pci_bus.h:23:5: error: unknown type name ‘PCIIOMMUFunc’
From: Peter Xu
QEMU is not handling the global DMAR switch well, especially when from
"on" to "off".
Let's first take the example of system reset.
Assuming that a guest has IOMMU enabled. When it reboots, we will drop
all the existing DMAR mappings to handle the system reset, however we'll
sti
From: Li Qiang
Cc: qemu-triv...@nongnu.org
Signed-off-by: Li Qiang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci-host/piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci
From: "Singh, Brijesh"
Emulate the interrupt remapping support when guest virtual APIC is
not enabled.
For more info Refer: AMD IOMMU spec Rev 3.0 - section 2.2.5.1
When VAPIC is not enabled, it uses interrupt remapping as defined in
Table 20 and Figure 15 from IOMMU spec.
Signed-off-by: Brije
From: Mao Zhongyi
Signed-off-by: Mao Zhongyi
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci/pci_bridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 08b7e
From: Gerd Hoffmann
Add memory bar to pci-testdev. Size is configurable using the membar
property. Setting the size to zero (default) turns it off. Can be used
to check whether guests handle large pci bars correctly.
Reviewed-by: Marc-André Lureau
Reviewed-by: Laszlo Ersek
Tested-by: Laszlo
From: "Singh, Brijesh"
Register the interrupt remapping callback and read/write ops for the
amd-iommu-ir memory region.
amd-iommu-ir is set to higher priority to ensure that this region won't
be masked out by other memory regions.
Signed-off-by: Brijesh Singh
Cc: Peter Xu
Cc: "Michael S. Tsir
From: Laszlo Ersek
The "tests/acpi-test-data" files are currently not covered by any section
in MAINTAINERS, and "scripts/checkpatch.pl" complains when new data files
are added.
Cc: "Michael S. Tsirkin"
Cc: Alex Williamson
Cc: Gerd Hoffmann
Cc: Igor Mammedov
Cc: Marcel Apfelbaum
Signed-off-
The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into
staging (2018-10-23 17:20:23 +0100)
are available in the Git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_
From: "Singh, Brijesh"
Currently, the amdvi_validate_dte() assumes that a valid DTE will
always have V=1. This is not true. The V=1 means that bit[127:1] are
valid. A valid DTE can have IV=1 and V=0 (i.e address translation
disabled and interrupt remapping enabled)
Remove the V=1 check from amdv
From: "Singh, Brijesh"
The vtd_generate_msi_message() in intel-iommu is used to construct a MSI
Message from IRQ. A similar function will be needed when we add interrupt
remapping support in amd-iommu. Moving the function in common file to
avoid the code duplication. Rename it to x86_iommu_irq_to
From: Laszlo Ersek
Expose the calculated "hole64 start" GPAs as plain uint64_t values,
extracting the internals of the current property getters.
This patch doesn't change behavior.
Cc: "Michael S. Tsirkin"
Cc: Alex Williamson
Cc: Gerd Hoffmann
Cc: Igor Mammedov
Cc: Marcel Apfelbaum
Signed-
From: Peter Xu
We should handle VTD_FR_CONTEXT_ENTRY_P properly when synchronizing
shadow page tables. Having invalid context entry there is perfectly
valid when we move a device out of an existing domain. When that
happens, instead of posting an error we invalidate the whole region.
Without t
From: Philippe Mathieu-Daudé
Introduced in 48ebf2f90f8 and faf1e708d5b, these functions
were never used. Remove them.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/pci-bridge/xio3130_downstream.h | 11 ---
hw/pci-bridge
From: Yongji Xie
Some old guests (before commit 7a11370e5: "virtio_blk: enable VQs early")
kick virtqueue before setting VIRTIO_CONFIG_S_DRIVER_OK. This violates
the virtio spec. But virtio 1.0 transitional devices support this behaviour.
So we should start vhost when guest kicks in this case.
S
From: "Singh, Brijesh"
To be consistent with intel-iommu:
- rename the address space to use '_' instead of '-'
- update the memory region relationships
Signed-off-by: Brijesh Singh
Reviewed-by: Peter Xu
Cc: Peter Xu
Cc: "Michael S. Tsirkin"
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Edua
From: Yaowei Bai
Here should be submit_requests, there is no submit_merged_requests
function.
Signed-off-by: Yaowei Bai
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/block/virtio-blk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block
From: "Singh, Brijesh"
Interrupt remapping needs kernel-irqchip={off|split} on both Intel and AMD
platforms. Move the check in common place.
Signed-off-by: Brijesh Singh
Reviewed-by: Peter Xu
Cc: Peter Xu
Cc: "Michael S. Tsirkin"
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
From: "Singh, Brijesh"
When interrupt remapping is enabled, add a special IVHD device
(type IOAPIC).
Signed-off-by: Brijesh Singh
Acked-by: Peter Xu
Cc: Peter Xu
Cc: "Michael S. Tsirkin"
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: Marcel Apfelbaum
Cc: Tom Lendacky
Cc
From: Peter Xu
Provide the function and use it in vtd_init(). Used to reset both
context entry cache and iotlb cache for the whole IOMMU unit.
Signed-off-by: Peter Xu
Reviewed-by: Eric Auger
Reviewed-by: Jason Wang
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/i
From: Peter Xu
There are two callers for vtd_sync_shadow_page_table_range(): one
provided a valid context entry and one not. Move that fetching
operation into the caller vtd_sync_shadow_page_table() where we need to
fetch the context entry.
Meanwhile, remove the error_report_once() directly sin
On Tue, Jan 16, 2018 at 06:06:56PM +0100, Paolo Bonzini wrote:
> Second, virtio-based vhost-user remains QEMU's preferred method for
> high-performance I/O in guests. Discard support is missing and that is
> important for SSDs; that should be fixed in the virtio spec.
BTW could you reply on the t
Considering the fact that both Ubuntu and Elementary require SSE to
boot, I'd wait to get decoding fixed. I wrote a test kernel module that
reliably reproduces your issue on qemu edu device. Whenever QEMU prints
Unimplemented handler Instruction pointer only moves two bytes further,
instead of the
On 22/10/2018 20:36, Samuel Ortiz wrote:
> This patch set implements support for the ACPI hardware-reduced
> specification.
>
> The changes are coming from the NEMU [1] project where we're defining
> a new x86 machine type: i386/virt. This is an EFI only, ACPI
> hardware-reduced platform and as su
On Thu, Oct 11, 2018 at 09:18:20AM -0700, Li Qiang wrote:
> Seems the intel link is unavailable, change it to qemu site.
>
> Signed-off-by: Li Qiang
> Reviewed-by: Philippe Mathieu-Daudé
BTW you need to fix up your setup: patches you sent confuse git
am and other tools. Somethig to do with enco
On Tue, Oct 02, 2018 at 01:54:25PM +0400, Marc-André Lureau wrote:
> Hi
>
> On Thu, Sep 27, 2018 at 7:37 PM Liang Li wrote:
> >
> > During live migration, when stopping vhost-user device, 'vhost_dev_stop'
> > will be called, 'vhost_dev_stop' will call a batch of 'vhost_user_read'
> > and 'vhost_u
On 24/10/2018 00:11, George Kennedy wrote:
>>>
>> What about "req->hba_private != s->current"? That should cause a call
>> to lsi_queue_req, and then you can check s->want_resel in lsi_queue_req.
>
> For the extended period of time where lsi_queue_req() is not being
> called from lsi_transfer_dat
On 22/10/2018 20:36, Samuel Ortiz wrote:
> +
> +static void acpi_reduced_build_update(void *build_opaque)
> +{
> +MachineState *ms = MACHINE(build_opaque);
> +AcpiBuildState *build_state = ms->firmware_build_state.acpi.state;
> +AcpiConfiguration *conf = ms->firmware_build_state.acpi.co
On 22/10/2018 20:36, Samuel Ortiz wrote:
> +static void acpi_conf_pc_init(MachineState *machine)
This should take a PCMachineState*, since you never use "machine" except
for downcasting.
Paolo
> +{
> +PCMachineState *pcms = PC_MACHINE(machine);
> +PCMachineClass *pcmc = PC_MACHINE_GET_CL
On 22/10/2018 20:36, Samuel Ortiz wrote:
> +/* Firmware building handler */
> +mc->firmware_build_methods.acpi.madt = build_madt;
> +mc->firmware_build_methods.acpi.rsdp = build_rsdp_rsdt;
> +mc->firmware_build_methods.acpi.setup = acpi_setup;
> +mc->firmware_build_methods.acpi.
Hi Fredrik,
> > target/mips/translate.c:4888:38: error: passing argument 3 of
> > ‘tcg_gen_add2_i32’ from incompatible pointer type
> > [-Werror=incompatible-pointer-types]
> > tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
> > ^~
Hi, Michael,
Just a kind reminder that this series has got enough ACKs and please
consider to merge it in your next pull. Thanks!
On Sat, Sep 29, 2018 at 11:36:13AM +0800, Peter Xu wrote:
> v4:
> - add a patch to introduce vtd_reset_caches()
> - reset the caches in the two places where GCMD upda
On 22/10/2018 20:36, Samuel Ortiz wrote:
> We build a minimal set of ACPI hardware-reduced tables: XSDT,
> FADT, MADT and a DSDT pointed by a RSDP.
> The DSDT only contains one PCI host bridge for now.
>
> This API will be consumed by new x86 machine type but also potentially
> by the ARM virt one
Hi, Michael,
Just a kind reminder that this series has got enough ACKs and please
consider to merge it in your next pull. Thanks!
On Tue, Oct 09, 2018 at 03:45:41PM +0800, Peter Xu wrote:
> v3:
> - pick r-b
> - return when -VTD_FR_CONTEXT_ENTRY_P is detected (v1 is correct here,
> but I did wr
On 10/23/2018 5:50 PM, Paolo Bonzini wrote:
On 23/10/2018 23:36, George Kennedy wrote:
On 10/23/2018 10:33 AM, Paolo Bonzini wrote:
On 22/10/2018 23:28, George Kennedy wrote:
As you suggested I moved the loading of "s->resel_dsp" down to the
"Wait Reselect"
case. The address of the Reselec
On 23/10/2018 23:36, George Kennedy wrote:
>
>
> On 10/23/2018 10:33 AM, Paolo Bonzini wrote:
>> On 22/10/2018 23:28, George Kennedy wrote:
>>> As you suggested I moved the loading of "s->resel_dsp" down to the
>>> "Wait Reselect"
>>> case. The address of the Reselection Scripts, though, is conta
A quick coredump on an incomplete command line:
./x86_64-softmmu/qemu-system-x86_64 -mon mode=control,pretty=on
#0 0x7723d9e4 in g_str_hash () at /lib64/libglib-2.0.so.0
#1 0x7723ce38 in g_hash_table_lookup () at /lib64/libglib-2.0.so.0
#2 0x55cc0073 in object_class_p
On 23/10/2018 23:35, Eric Blake wrote:
> A quick coredump on an incomplete command line:
> ./x86_64-softmmu/qemu-system-x86_64 -mon mode=control,pretty=on
>
> #0 0x7723d9e4 in g_str_hash () at /lib64/libglib-2.0.so.0
> #1 0x7723ce38 in g_hash_table_lookup () at /lib64/libglib-2
On 10/23/2018 10:33 AM, Paolo Bonzini wrote:
On 22/10/2018 23:28, George Kennedy wrote:
As you suggested I moved the loading of "s->resel_dsp" down to the "Wait
Reselect"
case. The address of the Reselection Scripts, though, is contained in "s->dsp -
8"
and not in s->dnad.
Are you sure? s
On Mon, 22 Oct 2018 13:17:34 +0100
Thomas Huth wrote:
> On 2018-10-22 10:02, Yi Min Zhao wrote:
> > Common function measurement block is used to report counters of
> > successfully issued pcilg/stg/stb and rpcit instructions. This patch
> > introduces a new struct ZpciFmb and schedules a timer ca
On 10/22/18 2:48 PM, Mao Zhongyi wrote:
The subject line says "what", but the commit body should say "why". My
suggestion:
POSIX requires $PWD to be reliable, and we expect all shells used by
qemu scripts to be relatively close to POSIX. Thus, it is smarter to
avoid forking the pwd executa
On 10/22/18 5:41 PM, Zhang Chen wrote:
This structure and command have missed qemu version 3.0, so fix it to since
version 3.1.
Signed-off-by: Zhang Chen
---
qapi/migration.json | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Eric Blake
diff --git a/qapi/migrati
Hi Peter, Aleksandar,
> Hi: I get compile errors on 32-bit hosts:
>
> /home/petmay01/qemu-for-merges/disas/mips.c:615:35: error: large
> integer implicitly truncated to unsigned type [-Werror=overflow]
> #define INSN_5900 0x1
>^
> /home/
** Changed in: qemu
Status: New => In Progress
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1796754
Title:
ioctl SIOCGIFCONF causes qemu-aarch64-static to crash with "received
signal outs
On 23/10/2018 14:07, Aleksandar Markovic wrote:
> From: Aleksandar Rikalo
>
> Implement support for translation of system call statx(). The
> implementation includes invoking other (more mature) syscalls
> (from the same 'stat' family) on the host side. This way,
> problems of availability of sta
** Tags added: linux-user sh4
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1737444
Title:
gccgo setcontext conftest crashes qemu-sh4
Status in QEMU:
New
Bug description:
While testing gccgo
** Tags added: windows10
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1775702
Title:
High host CPU load and slower guest after upgrade guest OS Windows 10
to ver 1803
Status in QEMU:
New
Bug
On Sun, Oct 21, 2018 at 14:27:22 +0100, Richard Henderson wrote:
> On 10/19/18 2:05 AM, Emilio G. Cota wrote:
> > @@ -713,9 +713,9 @@ int hvf_vcpu_exec(CPUState *cpu)
> > switch (exit_reason) {
> > case EXIT_REASON_HLT: {
> > macvm_set_rip(cpu, rip + ins_len);
> > -
On Tue, Oct 23, 2018 at 03:17:11 +0100, Richard Henderson wrote:
> On 10/23/18 12:50 AM, Emilio G. Cota wrote:
> > On Sun, Oct 21, 2018 at 14:34:25 +0100, Richard Henderson wrote:
> >> On 10/19/18 2:06 AM, Emilio G. Cota wrote:
> >>> @@ -540,16 +540,16 @@ static inline bool cpu_handle_interrupt(CPU
On 22 October 2018 at 13:57, Aleksandar Markovic
wrote:
> From: Aleksandar Markovic
>
> The following changes since commit b312532fd03413d0e6ae6767ec793a3e30f487b8:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2018-10-19 19:01:07 +0100)
>
> are available
Hi Maciej,
> target/mips/translate.c:4888:38: error: passing argument 3 of
> ‘tcg_gen_add2_i32’ from incompatible pointer type
> [-Werror=incompatible-pointer-types]
> tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
> ^~
Would you
On 23 October 2018 at 20:08, Samuel Ortiz wrote:
> Hi Peter,
>
> On Tue, Oct 23, 2018 at 08:01:26PM +0100, Peter Maydell wrote:
>> Hi -- I'd appreciate it if you don't send pull-requests for
>> patch series. They show up in my queue of things to merge directly
>> into master otherwise. Just send t
Hi Maciej,
> I have no authority to approve such a change for the kernel, but it looks
> reasonable to me and I will support you with it, with one reservation
> however. As this is an ISA extension in the vendor-specific space, I
> think it belongs to a vendor-specific namespace, so as to mak
Hi Peter,
On Tue, Oct 23, 2018 at 08:01:26PM +0100, Peter Maydell wrote:
> On 22 October 2018 at 19:36, Samuel Ortiz wrote:
> > This patch set implements support for the ACPI hardware-reduced
> > specification.
> >
> > The changes are coming from the NEMU [1] project where we're defining
> > a ne
On 22 October 2018 at 19:36, Samuel Ortiz wrote:
> This patch set implements support for the ACPI hardware-reduced
> specification.
>
> The changes are coming from the NEMU [1] project where we're defining
> a new x86 machine type: i386/virt. This is an EFI only, ACPI
> hardware-reduced platform a
On 23 October 2018 at 14:04, Markus Armbruster wrote:
> The following changes since commit b312532fd03413d0e6ae6767ec793a3e30f487b8:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2018-10-19 19:01:07 +0100)
>
> are available in the Git repository at:
>
>
On 22 October 2018 at 13:33, Markus Armbruster wrote:
> The following changes since commit 1b7490446bf41f54130c2d495dd4c8768c8e1ce3:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/linux-user-for-3.1-pull-request' into staging
> (2018-10-19 11:20:05 +0100)
>
> are available in the Git
On 23/10/18 15:54, Richard Henderson wrote:
On 10/23/18 2:27 PM, Philippe Mathieu-Daudé wrote:
+ if re_fullmatch('!extern', t):
+ extern = True
It looks odd to match a negative form then use a positive one.
Why not simply use 'extern'?
"!" is an escape character here.
Just
On 23/10/2018 14:07, Aleksandar Markovic wrote:
> From: Aleksandar Rikalo
>
> Add support for semtimedop() emulation.
>
> Signed-off-by: Aleksandar Rikalo
> Signed-off-by: Aleksandar Markovic
> ---
> linux-user/syscall.c | 27 +++
> 1 file changed, 27 insertions(+)
>
On 23/10/2018 14:07, Aleksandar Markovic wrote:
> From: Yunqiang Su
>
> Add support for SO_REUSEPORT, including strace support. SO_REUSEPORT
> was introduced relatively recently, since Linux 3.9, so use
> '#if defined SO_REUSEPORT'.
>
> Signed-off-by: Yunqiang Su
> Signed-off-by: Aleksandar Mar
On Tue, Oct 23, 2018 at 08:02:42 +0100, Richard Henderson wrote:
> The motivation here is reducing the total overhead.
>
> Before a few patches went into target-arm.next, I measured total
> tlb flush overhead for aarch64 at 25%. This appears to reduce the
> total overhead to about 5% (I do need t
From: Craig Janeczek
Add support for emulating the D16MUL MXU instruction.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 66 ++---
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/target
From: Craig Janeczek
Add bit encoding for MXU operand getting pattern 'optn2'.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 665a584
From: Craig Janeczek
Add emulation of non-MXU MULL within MXU decoding engine.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/
From: Craig Janeczek
Add support for emulating the S32I2M and S32M2I MXU instructions.
This commit also contains utility functions for reading/writing
to MXU registers. This is required for overall MXU instruction
support.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
t
From: Aleksandar Markovic
Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 41 +++--
1 file changed, 23 insertions(+), 18
From: Craig Janeczek
Add support for emulating the S32LDD and S32LDDR MXU instructions.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 54 ++---
1 file changed, 47 insertions(+), 7 deletions(-)
diff -
From: Aleksandar Markovic
Add bit encoding for MXU accumulate add/subtract 1-bit pattern
'aptn1'.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ed72b32..f274ac1 10
From: Craig Janeczek
Adds support for emulating the Q8MUL and Q8MULSU MXU instructions.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 101
1 file changed, 94 insertions(+), 7 deletions(-)
diff -
From: Aleksandar Markovic
Add MXU decoding engine: add handlers for all instruction pools,
and main decode handler. The handlers, for now, for the purpose
of this patch, contain only sceleton in the form of a single
switch statement.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate
From: Craig Janeczek
Add support for emulating the D16MAC MXU instruction.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 90 +++--
1 file changed, 87 insertions(+), 3 deletions(-)
diff --git a/target
From: Craig Janeczek
Add support for emulating the S8LDD MXU instruction.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 90 +++--
1 file changed, 87 insertions(+), 3 deletions(-)
diff --git a/target/
From: Aleksandar Markovic
Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 142 +---
On 21 October 2018 at 20:30, Samuel Thibault
wrote:
> The following changes since commit b312532fd03413d0e6ae6767ec793a3e30f487b8:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2018-10-19 19:01:07 +0100)
>
> are available in the Git repository at:
>
> ht
From: Aleksandar Markovic
Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 97fb2e0..665a584 10064
From: Craig Janeczek
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/mips-defs.h | 1
From: Craig Janeczek
Add bit encoding for MXU operand getting pattern 'optn3'.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f
From: Craig Janeczek
Add bit encoding for MXU accumulate add/subtract 2-bit pattern
'aptn2'.
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
From: Aleksandar Markovic
Provide the placeholder and add the invocation logic for MXU
decoding engine.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fefe9ac..12
From: Craig Janeczek
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.
Reviewed-by: Richard Henderson
Signed-off-by: Craig Janeczek
Signed-off-by: Aleksandar M
From: Aleksandar Markovic
This patch set begins to add MXU ASE instruction support.
v5->v6:
- added bit definitions for 'aptn1' and 'eptn2'.
- pool04 eliminated, since it is covered by a single instruction.
- moved MUL, S32M2I, S32I2M handling out of main MXU switch.
- rebased to the l
Should not be a problem right now, but it could theoretically happen
in the future.
Signed-off-by: David Hildenbrand
---
hw/mem/memory-device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/mem/memory-device.c b/hw/mem/memory-device.c
index 996ad1490f..8be63c8032 10064
While working on memory device code, I noticed that specifiying an uint64_t
on command line does not work in all cases as we always parse an int64_t.
So I fix that and also cleanup the old int64_t parser.
To be able to fix some overflows in memory-device code in a clean way,
I am reusing the range
On Thu, Oct 18, 2018 at 05:03:41PM -0300, Eduardo Habkost wrote:
> From: Markus Armbruster
>
> Calling error_report() in a function that takes an Error ** argument
> is suspicious. parse_numa_node() does that, and then exit()s. It
> also passes &error_fatal to machine_set_cpu_numa_node(). Both
The qemu api claims to be easier to use, and the resulting code seems to
agree.
Signed-off-by: David Hildenbrand
---
qapi/string-input-visitor.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/qapi/string-input-visitor.c b/qapi/string-input-visitor.c
index
On Thu, Oct 18, 2018 at 05:03:44PM -0300, Eduardo Habkost wrote:
> From: Philippe Mathieu-Daudé
>
> Move from the legacy SysBusDevice::init method to using DeviceState::realize.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Thomas Huth
> Reviewed-by: Cédric Le Goater
> Message-Id:
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