On 2018-10-04 18:18, Cleber Rosa wrote:
> Point to the right and obvious location for lm32 tests.
>
> Signed-off-by: Cleber Rosa
> ---
> tests/tcg/README | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/tcg/README b/tests/tcg/README
> index a5643d33e7..2a58f9a058 1
On 2018-10-05 06:25, David Gibson wrote:
> On Thu, Oct 04, 2018 at 12:07:01PM +0200, Thomas Huth wrote:
>> The spapr-rng device is suboptimal when compared to virtio-rng, so
>> users might want to disable it in their builds. Thus let's introduce
>> a proper CONFIG switch to allow us to compile QEMU
On Thu, Oct 04, 2018 at 12:07:01PM +0200, Thomas Huth wrote:
> The spapr-rng device is suboptimal when compared to virtio-rng, so
> users might want to disable it in their builds. Thus let's introduce
> a proper CONFIG switch to allow us to compile QEMU without this device.
>
> Signed-off-by: Thom
Ping?
On 2018-09-13 16:34, Fam Zheng wrote:
On Thu, 09/13 16:29, yuchen...@synology.com wrote:
From: yuchenlin
There is a rare case which the size of last compressed cluster
is larger than the cluster size, which will cause the file is
not aligned at the sector boundary.
There are three reas
On 04/10/2018 18:55, Laurent Vivier wrote:
> Le 28/09/2018 à 16:25, Peter Maydell a écrit :
>> Our __get_user_e() and __put_user_e() macros cause newer versions
>> of clang to generate false-positive -Waddress-of-packed-member
>> warnings if they are passed the address of a member of a packed
>> st
Hi, Cleber.
On Thu, Oct 04, 2018 at 11:14:24AM -0400, Cleber Rosa wrote:
> On a number of different scenarios, such as when choosing a QEMU
> binary to be used on tests (or a image to use to boot a test VM), it's
> useful to define the architecture that should be used.
>
> This introduces both a t
On 10/03/2018 08:07 AM, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Announce 64bit addressing support.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
---
hw/net/cadence_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/net/
On 10/03/2018 08:07 AM, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Add support for extended descriptors with optional 64bit
addressing and timestamping. QEMU will not yet provide
timestamps (always leaving the valid timestamp bit as zero).
Signed-off-by: Edgar E. Iglesias
Reviewed-b
On 10/03/2018 08:07 AM, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Add macro with max number of DMA descriptor words.
No functional change.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
---
hw/net/cadence_gem.c | 4 ++--
include/hw/net/cadenc
On 10/03/2018 08:07 AM, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Use uint32_t instead of unsigned to describe 32bit descriptor words.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
---
hw/net/cadence_gem.c | 42 +--
On 10/03/2018 08:07 AM, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: A
On Thu, Oct 4, 2018 at 3:03 PM Max Filippov wrote:
> But I guess always storing low 13 bits of LEND - PC should work?
...when they're within two pages from each other...
--
Thanks.
-- Max
Hi Richard,
thank you for taking a look.
On Thu, Oct 4, 2018 at 2:13 PM Richard Henderson
wrote:
> Think first about how, if PC >= LEND or LEND - PC > PAGE_SIZE, that all of the
> loop stuff is irrelevant because we won't hit LEND within this TB.
>
> Think second about how to represent the commo
On Thu, Oct 04, 2018 at 09:01:09PM +0100, Peter Maydell wrote:
> On 4 October 2018 at 20:52, Eduardo Habkost wrote:
> > Changing the object hierarchy based on GDB groups doesn't seem
> > right, but I don't think it would be a big deal if we have the
> > board code explicitly telling the GDB code h
On 10/04/2018 05:52 PM, Kevin Wolf wrote:
Am 04.10.2018 um 15:59 hat Vladimir Sementsov-Ogievskiy geschrieben:
04.10.2018 15:44, Kevin Wolf wrote:
Am 01.10.2018 um 12:29 hat Vladimir Sementsov-Ogievskiy geschrieben:
Fleecing-hook filter does copy-before-write operation. It should be
inserted a
On 10/4/18 3:14 PM, Max Filippov wrote:
> I thought about it some more and it looks like this is not going to work
> in general case in the presence of TB linking: a block with a big (and thus
> not precise) LEND distance may be linked to a block with a small (and
> thus precise) LEND distance. The
Emilio G. Cota writes:
> v1: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg00395.html
>
> Changes since v1:
>
> - Rebase on master
>
> - Expand lock usage to other tlb_table/tlb_v_table updates, which I
> missed in v1
>
> - Fix assert_cpu_is_self macro
>
> - Add comment on why the
On Wed, Oct 3, 2018 at 6:05 PM Max Filippov wrote:
>
> Don't invalidate TB with the end of zero overhead loop when LBEG or LEND
> change. Instead encode the distance from the TB start to the LEND in the
> TB flags and generate loopback code when offset of the next PC from the
> TB start equals tha
Connect the Xilinx PCIe device based on the information in the device
tree stored in the ROM of the HiFish Unleashed board.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 64 +
include/hw/riscv/sifive_u.h | 4 ++-
2 files changed, 67 insert
Enable compile support for VGA devices. This allows the user to conenct
a display by adding '-device bochs-display -display sdl' to their
command line argument.
Signed-off-by: Alistair Francis
---
default-configs/riscv32-softmmu.mak | 3 +++
default-configs/riscv64-softmmu.mak | 3 +++
hw/riscv/
Connect the gpex PCIe device based on the device tree included in the
HiFive Unleashed ROM.
Signed-off-by: Alistair Francis
---
default-configs/riscv32-softmmu.mak | 6 ++-
default-configs/riscv64-softmmu.mak | 6 ++-
hw/riscv/virt.c | 58 +
incl
Signed-off-by: Alistair Francis
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/virt.c | 20 +---
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/default-configs/riscv32-softmmu.mak
b/default
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 91163d6cbf..7cb2742070 100644
--- a/inclu
V5:
- Rebase
- Include pci.mak in the default configs
V4:
- Fix the spike device tree
- Don't use stdvga device
V3:
- Remove Makefile config changes
- Connect a network adapter to the virt device
V2:
- Use the gpex PCIe host for virt
- Add support for SiFive U PCIe
Alistair Francis (5):
On 4 October 2018 at 20:52, Eduardo Habkost wrote:
> Changing the object hierarchy based on GDB groups doesn't seem
> right, but I don't think it would be a big deal if we have the
> board code explicitly telling the GDB code how to group the CPUs.
>
> If you really want to do it implicitly, would
On Thu, Oct 04, 2018 at 06:07:45PM +0200, Philippe Mathieu-Daudé wrote:
> On 03/10/2018 13:44, Luc Michel wrote:
> > On 10/2/18 1:58 PM, Peter Maydell wrote:
> >> On 2 October 2018 at 12:33, Philippe Mathieu-Daudé
> >> wrote:
> >>> Cc'ing more QOM involved people.
> >>>
> >>> On 01/10/2018 13:57,
The ISA has a 128/64-bit division instruction.
Signed-off-by: Richard Henderson
---
include/fpu/softfloat-macros.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h
index 39eb08b4f1..eafc68932b 100644
--- a/include/fpu/softf
Changes from v2:
* Add shift128Left. I had been using shortShift128Left,
with a shift of 64, which lead to undefined behaviour.
Which I suspect is exactly the Heisenbug Alex saw.
I did keep the R-b tags I had already applied.
r~
Richard Henderson (4):
softfloat: Fix division
The ISA has a 128/64-bit division instruction.
Tested-by: Emilio G. Cota
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/fpu/softfloat-macros.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/s
The ISA has a 128/64-bit division instruction, though it assumes the
low 64-bits of the numerator are 0, and so requires a bit more fixup
than a full 128-bit division insn.
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
---
include/fpu/softfloat-macros.h | 16
1 fil
The __udiv_qrnnd primitive that we nicked from gmp requires its
inputs to be normalized. We were not doing that. Because the
inputs are nearly normalized already, finishing that is trivial.
Replace div128to64 with a "proper" udiv_qrnnd, so that this
remains a reusable primitive.
Fixes: cf07323d
Sorry for the late response.
By switching to 2.12 no noticeable change happens in respect to the 2.11
machine type: distorted audio but correct timing and no overlapping.
By the way, the stuttering looks less consistent than I previously thought:
today it appears even with the 2.11 setting, but
On Mon, Oct 1, 2018 at 5:07 AM Luc Michel wrote:
>
> When a new connection is established, we set the first process to be
> attached, and the others detached. The first CPU of the first process
> is selected as the current CPU.
>
> Signed-off-by: Luc Michel
Reviewed-by: Alistair Francis
Alista
On Wed, Oct 3, 2018 at 8:11 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Disable the Timestamping Unit feature bit since QEMU does not
> yet support it. This allows guest SW to correctly probe for
> its existance.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Franc
On Mon, Oct 1, 2018 at 4:57 AM Luc Michel wrote:
>
> Change the sC packet handling to support the multiprocess extension.
> Instead of returning the first thread, we return the first thread of the
> current process.
>
> Signed-off-by: Luc Michel
>
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-
On Mon, Oct 1, 2018 at 3:32 PM Philippe Mathieu-Daudé wrote:
>
> Move from the legacy SysBusDevice::init method to using DeviceState::realize.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/ssi/xilinx_spi.c | 9 +++--
> 1 file changed, 3 inser
On Tue, Oct 2, 2018 at 7:36 AM Damien Hedde wrote:
>
> Replace the zynq_slcr registers enum and macros using the
> hw/registerfields.h macros.
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/misc/zynq_slcr.c | 468 +
On Thu, Oct 04, 2018 at 01:57:21PM +0200, Igor Mammedov wrote:
> On Wed, 3 Oct 2018 10:44:20 -0700
> open sorcerer <0p3n.s0rc3...@gmail.com> wrote:
>
> > Hi,
> >
> > I am digging into an issue where qmp_device_del does not actually delete
> > devices when a guest OS is in prelaunch. This seems to
Le 25/09/2018 à 09:12, Cortland Tölva a écrit :
> This patch series aims to let programs running under QEMU Linux user mode
> emulation implement user-space USB drivers via the USBFS ioctl()s. First
> I check for the necessary header files, then I define some types, and
> last I implement the subm
Le 28/09/2018 à 16:25, Peter Maydell a écrit :
> Our __get_user_e() and __put_user_e() macros cause newer versions
> of clang to generate false-positive -Waddress-of-packed-member
> warnings if they are passed the address of a member of a packed
> struct (see https://bugs.llvm.org/show_bug.cgi?id=3
On 10/4/18 12:50 PM, Eric Blake wrote:
> On 10/4/18 11:18 AM, Cleber Rosa wrote:
>> Signed-off-by: Cleber Rosa
>> ---
>> dtc | 2 +-
>> scripts/qemu.py | 65 +++--
>> 2 files changed, 42 insertions(+), 25 deletions(-)
>>
>> diff --git
On 10/4/18 12:48 PM, Eric Blake wrote:
> On 10/4/18 11:18 AM, Cleber Rosa wrote:
>> A trivial comment typo fix.
>>
>> Signed-off-by: Cleber Rosa
>> ---
>> qemu-img.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/qemu-img.c b/qemu-img.c
>> index b12f4cd19b..a96b7
On 10/4/18 11:18 AM, Cleber Rosa wrote:
Commit 990dc39c made all tests executable at the time, but 218 came in
later, and missing those permissions.
Signed-off-by: Cleber Rosa
---
tests/qemu-iotests/218 | 0
1 file changed, 0 insertions(+), 0 deletions(-)
mode change 100644 => 100755 tests
On 10/4/18 11:18 AM, Cleber Rosa wrote:
Signed-off-by: Cleber Rosa
---
dtc | 2 +-
scripts/qemu.py | 65 +++--
2 files changed, 42 insertions(+), 25 deletions(-)
diff --git a/dtc b/dtc
index 88f18909db..e54388015a 16
--- a/dtc
+++
On 10/4/18 11:18 AM, Cleber Rosa wrote:
A trivial comment typo fix.
Signed-off-by: Cleber Rosa
---
qemu-img.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-img.c b/qemu-img.c
index b12f4cd19b..a96b76c187 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -1085,7 +1085,7 @
On 10/04/18 17:14, Cleber Rosa wrote:
> One of the Avocado features relevant to virtualization testing is the
> ability to reuse tests in different scenarios, known as variants.
> This adds a JSON based variants file, that can be used to run most
> tests in a number of different architectures. It
Le 04/10/2018 à 18:31, Cleber Rosa a écrit :
>
>
> On 10/4/18 12:24 PM, Laurent Vivier wrote:
>> Le 04/10/2018 à 18:18, Cleber Rosa a écrit :
>>> Signed-off-by: Cleber Rosa
>>> ---
>>> thunk.c | 2 --
>>> 1 file changed, 2 deletions(-)
>>>
>>> diff --git a/thunk.c b/thunk.c
>>> index d5d8645cd4
On 10/4/18 12:24 PM, Laurent Vivier wrote:
> Le 04/10/2018 à 18:18, Cleber Rosa a écrit :
>> Signed-off-by: Cleber Rosa
>> ---
>> thunk.c | 2 --
>> 1 file changed, 2 deletions(-)
>>
>> diff --git a/thunk.c b/thunk.c
>> index d5d8645cd4..e351ae53af 100644
>> --- a/thunk.c
>> +++ b/thunk.c
>> @
Signed-off-by: Cleber Rosa
---
scripts/decodetree.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 457cffea90..37c76b5507 100755
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -298,7 +298,7 @@ class Field:
Signed-off-by: Cleber Rosa
---
scripts/qemu.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/qemu.py b/scripts/qemu.py
index 7abe26de69..676eb9709a 100644
--- a/scripts/qemu.py
+++ b/scripts/qemu.py
@@ -88,7 +88,7 @@ class QEMUMachine(object):
@param name: p
Commit cce293a2945 moved some functions from common.config to
common.rc, but the error messages still reference the old file
location.
Signed-off-by: Cleber Rosa
---
tests/qemu-iotests/common.rc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/qemu-iotests/common.rc
Le 04/10/2018 à 18:18, Cleber Rosa a écrit :
> Signed-off-by: Cleber Rosa
> ---
> thunk.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/thunk.c b/thunk.c
> index d5d8645cd4..e351ae53af 100644
> --- a/thunk.c
> +++ b/thunk.c
> @@ -21,8 +21,6 @@
> #include "qemu.h"
> #include "exec/u
Signed-off-by: Cleber Rosa
---
dtc | 2 +-
scripts/qemu.py | 65 +++--
2 files changed, 42 insertions(+), 25 deletions(-)
diff --git a/dtc b/dtc
index 88f18909db..e54388015a 16
--- a/dtc
+++ b/dtc
@@ -1 +1 @@
-Subproject commit 88f1890
The line immediate following a ".. code::" block is considered
to contains arguments to the "code directive". The lack of a
new line gives me during at parse time:
testing.rst:63: (ERROR/3) Error in "code" directive:
maximum 1 argument(s) allowed, 3 supplied.
.. code::
make check-u
On 10/04/18 17:15, Philippe Mathieu-Daudé wrote:
> On 04/10/2018 17:07, Laszlo Ersek wrote:
>> On 10/03/18 20:30, Philippe Mathieu-Daudé wrote:
>>> This test boots EDK2 ArmVirtQemu and check the debug console (PL011)
>>> reports enough
>>> information on the initialized devices.
>>>
>>> $ avocado
Signed-off-by: Cleber Rosa
---
scripts/decodetree.py | 2 --
1 file changed, 2 deletions(-)
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 277f9a9bba..457cffea90 100755
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -149,12 +149,10 @@
# trans_addl_i(ctx, &arg_opi
A trivial comment typo fix.
Signed-off-by: Cleber Rosa
---
qemu-img.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-img.c b/qemu-img.c
index b12f4cd19b..a96b76c187 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -1085,7 +1085,7 @@ static int64_t find_nonzero(const uint8_t
Just a collection of trivial fixes and clean ups that have been lying
around here for some time.
Cleber Rosa (10):
qemu-img.c: comment typo fix
tests/tcg/README: fix location for lm32 tests
qemu-iotests: make 218 executable
qemu-iotests: fix filename containing checks
docs/devel/testing.
Point to the right and obvious location for lm32 tests.
Signed-off-by: Cleber Rosa
---
tests/tcg/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/tcg/README b/tests/tcg/README
index a5643d33e7..2a58f9a058 100644
--- a/tests/tcg/README
+++ b/tests/tcg/README
@@ -10
Signed-off-by: Cleber Rosa
---
thunk.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/thunk.c b/thunk.c
index d5d8645cd4..e351ae53af 100644
--- a/thunk.c
+++ b/thunk.c
@@ -21,8 +21,6 @@
#include "qemu.h"
#include "exec/user/thunk.h"
-//#define DEBUG
-
static unsigned int max_struct_ent
Commit 990dc39c made all tests executable at the time, but 218 came in
later, and missing those permissions.
Signed-off-by: Cleber Rosa
---
tests/qemu-iotests/218 | 0
1 file changed, 0 insertions(+), 0 deletions(-)
mode change 100644 => 100755 tests/qemu-iotests/218
diff --git a/tests/qemu-io
On 10/04/2018 09:17 AM, Thomas Huth wrote:
> On 2018-10-04 15:48, Andrew Jones wrote:
>> On Fri, Sep 28, 2018 at 03:47:35PM -0400, Wei Huang wrote:
> [...]
>>> diff --git a/tests/migration/aarch64/Makefile
>>> b/tests/migration/aarch64/Makefile
>>> new file mode 100644
>>> index 000..d440fa
Hi Damien,
On 02/10/2018 16:24, Damien Hedde wrote:
> This series aims to add a way to model clocks in qemu between devices.
> This allows to model the clock tree of a platform allowing us to inspect clock
> configuration and detect problems such as disabled clock or bad configured
> pll.
>
> Thi
On Wed, 3 Oct 2018 19:21:25 +0200
David Hildenbrand wrote:
> On 03/10/2018 08:29, David Gibson wrote:
> > On Wed, Sep 26, 2018 at 11:42:13AM +0200, David Hildenbrand wrote:
> >> The unplug and unplug_request handlers are special: They are not
> >> executed when unrealizing a device, but rather
On 03/10/2018 13:44, Luc Michel wrote:
> On 10/2/18 1:58 PM, Peter Maydell wrote:
>> On 2 October 2018 at 12:33, Philippe Mathieu-Daudé wrote:
>>> Cc'ing more QOM involved people.
>>>
>>> On 01/10/2018 13:57, Luc Michel wrote:
Create two separate QOM containers for APUs and RPUs to indicate t
This patch adds migration test support for aarch64. The test code, which
implements the same functionality as x86, is booted as a kernel in qemu.
Here are the design choices we make for aarch64:
* We choose this -kernel approach because aarch64 QEMU doesn't provide a
built-in fw like x86 does.
Hi Peter,
On 02/10/2018 18:35, Peter Maydell wrote:
> The Arm v8M architecture includes hardware stack limit checking.
> When certain instructions update the stack pointer, if the new
> value of SP is below the limit set in the associated limit register
> then an exception is taken. Add a TB flag
Am 21.08.2018 um 11:46 hat Anton Nefedov geschrieben:
> This will help to identify how many of the user-issued discard operations
> (accounted on a device level) have actually suceeded down on the host file
> (even though the numbers will not be exactly the same if non-raw format
> driver is used (
Hi Aleksandar and Stefan,
On 04/10/2018 14:34, Aleksandar Markovic wrote:
> From: Stefan Markovic
>
> Add DSP R3 ASE related bit definition for insn_flags and hflags.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/cpu.h | 1 +
> target/mips/mips-defs.h | 1 +
> 2 files chang
On 10/04/2018 10:30 AM, Philippe Mathieu-Daudé wrote:
> On 04/10/2018 17:27, Wei Huang wrote:
>> On 10/04/2018 10:07 AM, Philippe Mathieu-Daudé wrote:
>>> On 28/09/2018 21:47, Wei Huang wrote:
>>> [...]> +++ b/tests/migration/aarch64/Makefile
@@ -0,0 +1,20 @@
+# To specify cross compil
On 10/4/18 11:42 AM, Philippe Mathieu-Daudé wrote:
> On 04/10/2018 17:14, Cleber Rosa wrote:
>> With the introduction of a variants file that can run the same
>> tests on various architectures, it makes sense to make most tests
>> to be reusable on those environments. The exception should be
>>
Am 21.08.2018 um 11:46 hat Anton Nefedov geschrieben:
> Signed-off-by: Anton Nefedov
> Reviewed-by: Vladimir Sementsov-Ogievskiy
> Reviewed-by: Alberto Garcia
> ---
> hw/scsi/scsi-disk.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/scsi/scsi-disk.c b/hw/s
Emilio G. Cota writes:
> On Thu, Oct 04, 2018 at 10:13:55 +0100, Alex Bennée wrote:
>>
>> Richard Henderson writes:
>>
>> > Changes from v1:
>> > * Preserve udiv_qrnnd as a separate division primitive that
>> > could be used as a building block for float128 division.
>> > * Include asm
From: David Hildenbrand
Let's check this also at a central place.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
Message-Id: <20180927130303.12236-8-da...@redhat.com>
Acked-by: Thomas Huth
Signed-off-by: Cornelia Huck
---
target/s390x/insn-data.def | 138 +++
On 04/10/2018 17:14, Cleber Rosa wrote:
> With the introduction of a variants file that can run the same
> tests on various architectures, it makes sense to make most tests
> to be reusable on those environments. The exception should be
> when a test is really testing a specific architecture featu
Am 21.08.2018 um 11:46 hat Anton Nefedov geschrieben:
> Signed-off-by: Anton Nefedov
> Reviewed-by: Alberto Garcia
> ---
> hw/ide/core.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/hw/ide/core.c b/hw/ide/core.c
> index 2c62efc..352429b 100644
> --- a/hw/ide/core.c
> +
From: David Hildenbrand
These flags allow us to later on detect if a DATA program interrupt
is to be injected, and which DXC (1,2,3) is to be used.
Interestingly, some support FP instructions are considered as HFP
instructions (I assume simply because they were available very early).
Reviewed-b
From: David Hildenbrand
With the annotated functions, we can now easily check this at a central
place.
DXC 1 is to be injected if an AFP register is used (for a HFP AND FPS
instruction) when AFP is disabled.
DXC 2 is to be injected if a BFP instruction is used when AFP is
disabled.
DXC 3 is to b
From: Thomas Huth
The SysBusDeviceClass->init() interface is considered as a legacy interface
and there are currently some efforts going on to get rid of it. Thus let's
convert the init function in the s390x code to realize() instead.
Signed-off-by: Thomas Huth
Message-Id: <1538466491-2073-1-gi
From: David Hildenbrand
We exit the TB when changing the control registers, so just like PSW
bits, this should always be consistent for a TB.
Using the PSW bit semantic makes things a lot easier compared to
manually defining the spare, shifted bits.
Reviewed-by: Richard Henderson
Signed-off-by
On 04/10/2018 17:27, Wei Huang wrote:
> On 10/04/2018 10:07 AM, Philippe Mathieu-Daudé wrote:
>> On 28/09/2018 21:47, Wei Huang wrote:
>> [...]> +++ b/tests/migration/aarch64/Makefile
>>> @@ -0,0 +1,20 @@
>>> +# To specify cross compiler prefix, use CROSS_PREFIX=
>>> +# $ make CROSS_PREFIX=aarch6
From: David Hildenbrand
Storing flags for instructions allows us to efficiently verify certain
properties at a central point. Examples might later be handling if
AFP is disabled in CR0, we are not in problem state, or if vector
instructions are disabled in CR0.
Reviewed-by: Richard Henderson
Re
From: David Hildenbrand
The DXC is to be stored in the low core, and only in the FPC in case AFP
is enabled in CR0. Stub is not required in current code, but this way
we never run into problems.
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Signed-off-by: David Hildenbrand
Message-I
From: David Hildenbrand
We can fit this nicely into less LOC, without harming readability.
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Signed-off-by: David Hildenbrand
Message-Id: <20180927130303.12236-10-da...@redhat.com>
Signed-off-by: Cornelia Huck
---
target/s390x/translate.
From: David Hildenbrand
Valid register pairs are 0/2, 1/3, 4/6, 5/7, 8/10, 9/11, 12/14, 13/15.
R1/R2 always selects the lower number, so the current checks are not
correct as e.g. 2/4 could be selected as a pair.
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Signed-off-by: David Hil
Cleber Rosa writes:
> On 10/4/18 8:58 AM, Alex Bennée wrote:
>>
>>
>> The error log: https://transfer.sh/lK71v/avocado-errors.log
>>
>
> The core reason is:
>
> 2018-10-04 12:53:16,339 qemu L0270 DEBUG| Output:
> 'qemu-system-aarch64: -machine pc: unsupported machine type\nUse
> -m
From: David Hildenbrand
Move it into TCG-only code and provide a stub. Turn it into noreturn.
As Richard noted, we currently don't log the psw.addr before restoring
the state, fix that by moving (duplicating) the qemu_log_mask in the
tcg/kvm handlers.
Reviewed-by: Richard Henderson
Reviewed-by
From: Thomas Huth
The uint16_t member cu_type of struct SenseId is not naturally aligned,
and since the struct is marked with QEMU_PACKED, this can lead to
unaligned memory accesses - which does not work on architectures like
Sparc. Thus remove the QEMU_PACKED here and rather copy the struct
byte
From: Pavel Zbitskiy
Both LPSW and LPSWE should raise a specification exception when their
operand is not doubleword aligned.
Signed-off-by: Pavel Zbitskiy
Message-Id: <20180902003322.3428-3-pavel.zbits...@gmail.com>
Reviewed-by: David Hildenbrand
Signed-off-by: Cornelia Huck
---
target/s390
From: Thomas Huth
The IplParameterBlock and QemuIplParameters structures are declared with
QEMU_PACKED, so the compiler assumes that the structures do not need to
be aligned in memory. Since the are listed after a "bool" within the
S390IPLState, the IplParameterBlock and QemuIplParameters are als
From: Janosch Frank
As the kernel has no way of disallowing the start of a huge page
backed VM, we can migrate a running huge backed VM to a host that has
no huge page KVM support.
Let's glue huge page support support to the 3.1 machine, so we do not
migrate to a destination host that doesn't ha
The following changes since commit dafd95053611aa14dda40266857608d12ddce658:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2018-10-02 18:27:18 +0100)
are available in the Git repository at:
git://github.com/cohuck/qemu tags/s390x-20181004
for yo
From: Thomas Huth
struct SubchDev embeds several other structures which are marked with
QEMU_PACKED. This causes the compiler to not care for proper alignment
of these structures. When we later pass around pointers to the unaligned
struct members during migration, this causes problems on host arc
On 10/04/2018 10:07 AM, Philippe Mathieu-Daudé wrote:
> On 28/09/2018 21:47, Wei Huang wrote:
> [...]> +++ b/tests/migration/aarch64/Makefile
>> @@ -0,0 +1,20 @@
>> +# To specify cross compiler prefix, use CROSS_PREFIX=
>> +# $ make CROSS_PREFIX=aarch64-linux-gnu-
>> +
>> +.PHONY: all clean
>>
On 4 October 2018 at 16:05, Andrew Jones wrote:
> On Tue, Oct 02, 2018 at 02:07:38PM +0100, Peter Maydell wrote:
>> Hi; thanks for this patch. The issue I see with this patch
>> is that the KVM/ARM QEMU approach to system registers so far
>> has been "the kernel knows about these and it is in cont
On 04/10/2018 17:07, Laszlo Ersek wrote:
> On 10/03/18 20:30, Philippe Mathieu-Daudé wrote:
>> This test boots EDK2 ArmVirtQemu and check the debug console (PL011) reports
>> enough
>> information on the initialized devices.
>>
>> $ avocado run -p qemu_bin=aarch64-softmmu/qemu-system-aarch64
>> t
With the introduction of a variants file that can run the same
tests on various architectures, it makes sense to make most tests
to be reusable on those environments. The exception should be
when a test is really testing a specific architecture feature.
With the change proposed here, on a command
On Thu, Sep 27, 2018 at 01:13:54AM +, mja...@caviumnetworks.com wrote:
> From: Manish Jaggi
>
> Invariant registers will be skipped from being restored from
> guests' context on migrated host.
>
> Signed-off-by: Manish Jaggi
>
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index 65f8
By setting the machine type, even if it's the one that will be picked
based on the arch, it's possible to run the same tests with targets
that require a machine type (in addition to those that don't).
Given that only boot_linux_console.py contains code specific to x86_64
(an explicit reference to
Some targets require a machine type to be set, as there's no default
(aarch64 is one example). To give a consistent interface to users of
this API, this changes set_machine() so that a predefined default can
be used, if one is not given. The approach used is exactly the same
with the console devi
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