Allocate new segment for pxb-pcie host bridges in MCFG table, and reserve
corresponding MCFG space for them. This allows user-defined pxb-pcie
host bridges to be placed in different pci domain than q35 host.
The pci_host_bridges list is changed to be tail list to ensure the q35 host
is always the
This allows SeaBIOS to retrieve MCFG base and size when it initializes
pxb host bridges.
A backlink to PXBPCIEHost is added in PXBDev to achieve above goal
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 55 +
include/hw/pci-bridge/pci_exp
The bus_nr indicates the bus number of pxb-pcie under pcie.0, but since pxb
host can be put into different pci domain, the start bus should always be 0
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c| 14 ++
hw/pci-bridge/pci_expander_bridge.c | 10 +-
2 fi
This enables seabios to read config file in pxb host bus other than sysbus
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 15 +++
include/hw/pci-bridge/pci_expander_bridge.h | 3 +++
2 files changed, 18 insertions(+)
diff --git a/hw/pci-bridge/pci_expan
Describe new pci segments of host bridges in AML as new pci devices,
with _SEG and _BBN to let them be in DSDT.
Besides, bus_nr indicates the bus number of pxb-pcie under pcie.0 bus,
but since we put it into separate domain, it should be zero, which is
equal to BBN.
Signed-off-by: Zihan Yang
---
The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
change it to a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 127 ++--
1 file changed, 122 insertions(+), 5
Currently only q35 host bridge is allocated an item in MCFG table, all pxb
host bridges stay within pci domain 0. This series of patches put each pxb
host bridge in separate pci domain, allocating a new MCFG table item for it.
Users can configure whether to put pxb host bridge into separate domain
On 08/08/2018 01:48 PM, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> ---
> hw/virtio/Makefile.objs| 1 +
> hw/virtio/virtio-pci.c | 52 -
> hw/virtio/virtio-rng-pci.c | 77 ++
> tests/Makefile.include | 4 +-
> 4 f
On 08/08/2018 01:48 PM, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> ---
> hw/virtio/Makefile.objs | 1 +
> hw/virtio/virtio-input-pci.c | 136 +++
> hw/virtio/virtio-pci.c | 112 -
> 3 files changed, 137 insertions
On 08/08/2018 01:48 PM, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> ---
> default-configs/virtio.mak| 3 +++
> hw/virtio/Makefile.objs | 1 +
> hw/virtio/virtio-input-host-pci.c | 42 +++
> hw/virtio/virtio-pci.c| 20 --
On 08/08/2018 11:07 PM, Julia Suvorova via Qemu-devel wrote:
> New mini-kernel test for nRF51 SoC UART.
>
> Signed-off-by: Julia Suvorova
> ---
> tests/boot-serial-test.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/tests/boot-serial-test.c b/tests/boot-serial-t
Hello,
On Thu, Aug 9, 2018 at 6:21 AM, Richard Henderson
wrote:
> This is my current set of patches for running SVE in system mode.
>
> The first half deal with the system registers that affect SVE.
> I recall that Peter has said he'd like the first patch to be
> done a different way, but we have
On Thu, Aug 9, 2018 at 5:40 AM, Richard Henderson
wrote:
> The scaling should be solely on the memory operation size; the number
> of registers being loaded does not come in to the initial computation.
>
> Cc: qemu-sta...@nongnu.org (3.0.1)
> Reported-by: Laurent Desnogues
> Signed-off-by: Richar
On 08/08/2018 07:02 PM, Juan Quintela wrote:
> Thomas Huth wrote:
[...]
> I didn't want to go "further", but I think that we should have here is
> something like:
>
> check-qtest-$(CONFIG_USB_XHCI_NEC) += tests/usb-hcd-xhci-test$(EXESUF)
> gcov-files-$(CONFIG_USB_XHCI) += hw/usb/hcd-xhci.c
>
> a
On Thu, Aug 9, 2018 at 5:40 AM, Richard Henderson
wrote:
> The immediate should be scaled by the size of the memory reference,
> not the size of the elements into which it is loaded.
>
> Cc: qemu-sta...@nongnu.org (3.0.1)
> Reported-by: Laurent Desnogues
> Signed-off-by: Richard Henderson
Teste
On Thu, Aug 9, 2018 at 5:40 AM, Richard Henderson
wrote:
> The expression (int) imm + (uint32_t) len_align turns into uint32_t
> and thus with negative imm produces a memory operation at the wrong
> offset. None of the numbers involved are particularly large, so
> change everything to use int.
>
This implements the feature for softmmu, and moves the
main loop out of a macro and into a function.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 84 ---
target/arm/sve_helper.c| 290 +++--
target/arm/translate-sve.c | 84 +--
This fixes the endianness problem for softmmu, and does
move the main loop out of a macro and into an inlined function.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 84 +
target/arm/sve_helper.c| 218 +++--
target/arm/translate-sv
This fixes the endianness problem for softmmu, and does
move the main loop out of a macro and into an inlined function.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 52 ++
target/arm/sve_helper.c| 139 -
target/arm/transla
We can choose the endianness at translation time, rather than
re-computing it at execution time.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 117 +++---
target/arm/sve_helper.c| 70 ++---
target/arm/translate-sve.c | 196
We can choose the endianness at translation time, rather than
re-computing it at execution time.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 48 +
target/arm/sve_helper.c| 11 --
target/arm/translate-sve.c | 72 +--
Uses tlb_vaddr_to_host for correct operation with softmmu.
Optimize for accesses within a single page or pair of pages.
Perf report comparison for cortex-strings test-strlen
with aarch64-linux-user:
before:
1.59% qemu-aarch64 qemu-aarch64 [.] do_sve_ld1bb_r
0.86% qemu-aarch64 qemu-aarc
This fixes the endianness problem for softmmu, and does
move the main loop out of a macro and into an inlined function.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 351
1 file changed, 172 insertions(+), 179 deletions(-)
diff --git a/t
Use the existing helpers to determine if (1) the fpu is enabled,
(2) sve state is enabled, and (3) the current sve vector length.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4
target/arm/helper.c| 6 +++---
target/arm/translate-a64.c | 8 ++--
3 files chan
The 16-byte load only uses 16 predicate bits. But while
reusing the other load infrastructure, we find other bits
that are set and trigger an assert. To avoid this and
retain the assert, zero-extend the predicate that we pass
to the LD1 helper.
Reported-by: Laurent Desnogues
Signed-off-by: Rich
Saves about 8k code size in qemu-aarch64.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8
1 file changed, 8 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index aedaf2631e..ed51a2f5aa 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -918,7 +918,15 @@ v
There is quite a lot of code required to compute cpu_mem_index,
or even put together the full TCGMemOpIdx. This can easily be
done at translation time.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 5 ++
target/arm/sve_helper.c| 138 +++-
SVE vector length can change when changing EL, or when writing
to one of the ZCR_ELn registers.
For correctness, our implementation requires that predicate bits
that are inaccessible are never set. Which means noticing length
changes and zeroing the appropriate register bits.
Signed-off-by: Rich
Use the same *_tlb primitives as we use for ld1. This is not
a significant change, but does (for linux-user) hoist the set
of helper_retaddr, and (for softmmu) hoist the computation of
the current mmu_idx outside the loop.
This does fix the endianness problem for softmmu, and does
move the main l
Given that the only field defined for this new register may only
be 0, we don't actually need to change anything except the name.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper
Saves about 12k code size in qemu-aarch64.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2d6d7d03aa..aedaf2631e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1958,6 +1958,9 @@ sta
Unlike aa32, endianness cannot be adjusted by userland in aa64.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9526ed27cb..2d6d7d03aa 100644
--- a/ta
We are going to want to determine whether sve is enabled
for EL than current.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 26e9098c5f..290b1a849e
Check for EL3 before testing CPTR_EL3.EZ. Return 0 when the exception
should be routed via AdvSIMDFPAccessTrap. Mirror the structure of
CheckSVEEnabled more closely.
Fixes: 5be5e8eda78
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 96 ++---
For the supported extensions, fill in the appropriate bits in
ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 24 +---
target/arm/cpu64.c | 36
2 files changed, 45 insertions(+), 15
This it a hair out of spec in that we have and advertise, support
for fp16 in aarch64 mode, but do not have nor advertise the same
in aarch32 mode. Rationale as commented.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 21 +++--
1 file changed, 15 insertions(+), 6 del
This is my current set of patches for running SVE in system mode.
The first half deal with the system registers that affect SVE.
I recall that Peter has said he'd like the first patch to be
done a different way, but we haven't had a chance to talk about
what form it should take. I've left it as-i
This allows the default (and maximum) vector length to be set
from the command-line. Which is extraordinarily helpful in
debuging problems depending on vector length without having to
bake knowledge of PR_SET_SVE_VL into every guest binary.
Cc: qemu-sta...@nongnu.org (3.0.1)
Signed-off-by: Richar
The scaling should be solely on the memory operation size; the number
of registers being loaded does not come in to the initial computation.
Cc: qemu-sta...@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 5 ++---
1 file change
The immediate should be scaled by the size of the memory reference,
not the size of the elements into which it is loaded.
Cc: qemu-sta...@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 3 ++-
1 file changed, 2 insertions(+), 1
Cc: qemu-sta...@nongnu.org (3.0.1)
Tested-by: Laurent Desnogues
Reviewed-by: Laurent Desnogues
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 de
Also fold the FPCR/FPSR state onto the same line as PSTATE,
and mention but do not dump disabled FPU state.
Cc: qemu-sta...@nongnu.org (3.0.1)
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 95 +-
1 file changed, 83 insertions(+), 12 deletio
Used the wrong temporary in the computation of subtractive overflow.
Cc: qemu-sta...@nongnu.org (3.0.1)
Tested-by: Laurent Desnogues
Reviewed-by: Laurent Desnogues
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 2 +-
1 file changed, 1 insertio
The expression (int) imm + (uint32_t) len_align turns into uint32_t
and thus with negative imm produces a memory operation at the wrong
offset. None of the numbers involved are particularly large, so
change everything to use int.
Cc: qemu-sta...@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues
The pseudocode for this operation is an increment + compare loop,
so comparing <= the maximum integer produces an all-true predicate.
Rather than bound in both the inline code and the helper, pass the
helper the number of predicate bits to set instead of the number
of predicate elements to set.
C
With PC, there are 33 registers. Three per line lines up nicely
without overflowing 80 columns.
Cc: qemu-sta...@nongnu.org (3.0.1)
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/arm/transla
The normal vector element is sign-extended before
comparing with the wide vector element.
Cc: qemu-sta...@nongnu.org (3.0.1)
Tested-by: Laurent Desnogues
Reviewed-by: Laurent Desnogues
Reviewed-by: Alex Bennée
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/sve
Cc: qemu-sta...@nongnu.org (3.0.1)
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index c3cbec9cf5..e03f954a26 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/
I posted a few of these before, and I thought Peter had applied them
to his target-arm.for-3-1 branch, but I don't see them there now.
I've taken the opportunity to tag all of these for backport into the
next stable release. I'm intending to do so for all of the correctness
patches affecting sv
On Thu, Aug 09, 2018 at 11:13:17AM +0800, Xiao Guangrong wrote:
>
>
> On 08/08/2018 02:12 PM, Peter Xu wrote:
> > On Tue, Aug 07, 2018 at 05:12:09PM +0800, guangrong.x...@gmail.com wrote:
> >
> > [...]
> >
> > > @@ -1602,6 +1614,26 @@ static void migration_update_rates(RAMState *rs,
> > > int6
On 08/08/2018 02:12 PM, Peter Xu wrote:
On Tue, Aug 07, 2018 at 05:12:09PM +0800, guangrong.x...@gmail.com wrote:
[...]
@@ -1602,6 +1614,26 @@ static void migration_update_rates(RAMState *rs, int64_t
end_time)
rs->xbzrle_cache_miss_prev) / page_count;
rs->xbzrle_cac
On 08/08/2018 10:11 PM, Dr. David Alan Gilbert wrote:
* Xiao Guangrong (guangrong.x...@gmail.com) wrote:
On 08/08/2018 01:08 PM, Peter Xu wrote:
On Tue, Aug 07, 2018 at 05:12:07PM +0800, guangrong.x...@gmail.com wrote:
From: Xiao Guangrong
ram_find_and_save_block() can return negative i
On Wed, Aug 08, 2018 at 09:29:19PM +0530, Bharata B Rao wrote:
> VMStateDescription vmstate_spapr_cpu_state was added by commit
> b94020268e0b6 (spapr_cpu_core: migrate per-CPU data) to migrate per-CPU
> data with the required vmstate registration and unregistration calls.
> However the unregistrat
On Wed, 8 Aug 2018 11:45:43 +0800
Peter Xu wrote:
> On Wed, Aug 08, 2018 at 12:58:32AM +0300, Michael S. Tsirkin wrote:
> > At least with VTD, it seems entirely possible to change e.g. a PMD
> > atomically to point to a different set of PTEs, then flush.
> > That will allow removing memory at hig
The default cache-clean-interval is set to 10 minutes, in order to lower
the overhead of the qcow2 caches (before the default was 0, i.e.
disabled).
Signed-off-by: Leonid Bloch
---
block/qcow2.c| 2 +-
block/qcow2.h| 1 +
docs/qcow2-cache.txt | 4 ++--
qapi/block-core.json | 3 ++
Signed-off-by: Leonid Bloch
---
block/qcow2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/block/qcow2.c b/block/qcow2.c
index 15d849d1f0..0d9d20e46b 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -1321,7 +1321,7 @@ static int coroutine_fn qcow2_do_open(BlockDriverSt
Sufficient L2 cache can noticeably improve the performance when using
large images with frequent I/O. The memory overhead is not significant
in most cases, as the cache size is only 1 MB for each 8 GB of virtual
image size (with the default cluster size of 64 KB).
Previously, the L2 cache was allo
The caches are now recalculated upon image resizing. This is done
because the new default behavior of assigning L2 cache relatively to
the image size, implies that the cache will be adapted accordingly
after an image resize.
Signed-off-by: Leonid Bloch
---
block/qcow2.c | 10 ++
1 file c
Signed-off-by: Leonid Bloch
---
docs/qcow2-cache.txt | 3 +++
qemu-options.hx | 9 ++---
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/docs/qcow2-cache.txt b/docs/qcow2-cache.txt
index 8a09a5cc5f..5bf2a8ad29 100644
--- a/docs/qcow2-cache.txt
+++ b/docs/qcow2-cache.txt
@@
This series makes the qcow2 L2 cache assignment aware of the image size,
with the intention for it to cover the entire image. The importance of
this change is in noticeable performance improvement, especially with
heavy random I/O. The memory overhead is not big in most cases, as only
1 MB of cache
On Fri, Aug 3, 2018 at 7:47 AM, Stefan Hajnoczi wrote:
> The next patch will need to free a rom. There is already code to do
> this in rom_add_file().
>
> Note that rom_add_file() uses:
>
> rom = g_malloc0(sizeof(*rom));
> ...
> if (rom->fw_dir) {
> g_free(rom->fw_dir);
> g_free
On Fri, Aug 3, 2018 at 7:47 AM, Stefan Hajnoczi wrote:
> Image file loaders may add a series of roms. If an error occurs partway
> through loading there is no easy way to drop previously added roms.
>
> This patch adds a transaction mechanism that works like this:
>
> rom_transaction_begin();
>
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova
---
tests/boot-serial-test.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index 952a2e7ead..19714c3f87 100644
--- a/tests/boot-serial-test.c
+++
Some functional tests for:
Basic reception/transmittion
Suspending
INTEN* registers
Based-on: <20180806100114.21410-6-cont...@steffen-goertz.de>
Signed-off-by: Julia Suvorova
---
tests/microbit-test.c | 106 --
1 file changed, 103 insertions(+
Wire up nRF51 UART in the corresponding SoC using in-place init/realize.
Based-on: <20180803052137.10602-1-j...@jms.id.au>
Signed-off-by: Julia Suvorova
---
hw/arm/nrf51_soc.c | 20
include/hw/arm/nrf51_soc.h | 3 +++
2 files changed, 23 insertions(+)
diff --git a
Not implemented: CTS/NCTS, PSEL*.
Signed-off-by: Julia Suvorova
---
hw/char/Makefile.objs| 1 +
hw/char/nrf51_uart.c | 329 +++
hw/char/trace-events | 4 +
include/hw/char/nrf51_uart.h | 78 +
4 files changed, 412 insertions(+)
This series adds support for the nRF51 SoC UART, that used in
BBC Micro:bit board, and QTest for it.
v2:
* Suspend/Enable functionality added
* Connection to SoC moved to a separate patch
* Added QTest for checking reception functionality
* Mini-kernel test changed to fit current i
On Wed, Aug 08, 2018 at 09:19:31PM +0100, Mark Cave-Ayland wrote:
> On 08/08/18 20:53, Eduardo Habkost wrote:
>
> > On Wed, Aug 08, 2018 at 08:19:51PM +0100, Mark Cave-Ayland wrote:
> > > For the older machines (such as Mac and SPARC) the DT nodes representing
> > > bootdevices for disk nodes are
In preparation for having vhost-scsi also make use of host_features,
move it from struct VHostUserSCSI into struct VHostSCSICommon.
Signed-off-by: Greg Edwards
---
hw/scsi/vhost-user-scsi.c | 15 ---
include/hw/virtio/vhost-scsi-common.h | 1 +
include/hw/virtio/vhost-us
Allow toggling on/off the VIRTIO_SCSI_F_T10_PI feature bit for both
vhost-scsi and vhost-user-scsi devices.
Signed-off-by: Greg Edwards
---
hw/scsi/vhost-scsi.c | 3 +++
hw/scsi/vhost-user-scsi.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-sc
Move the enablement of preset host features into the common
vhost_scsi_common_get_features() function. This is in preparation for
having vhost-scsi also make use of host_features.
Signed-off-by: Greg Edwards
---
hw/scsi/vhost-scsi-common.c | 3 +++
hw/scsi/vhost-user-scsi.c | 14 +---
Unify the get_features functions for vhost-scsi and vhost-user-scsi, including
their use of host_features, and expose a new 't10_pi' property to enable
negotiation of the VIRTIO_SCSI_F_T10_PI feature bit with the backend.
Greg Edwards (3):
vhost-user-scsi: move host_features into VHostSCSICommon
On Wed, Aug 08, 2018 at 05:15:45PM +0200, Igor Mammedov wrote:
> It's an alternative approach to
> 1) [PATCH hack dontapply v2 0/7] Dynamic _CST generation
> which instead of dynamic AML loading uses static AML with
> dynamic values. It allows us to keep firmware blob static and
> to avoid split
On 08/08/18 20:53, Eduardo Habkost wrote:
On Wed, Aug 08, 2018 at 08:19:51PM +0100, Mark Cave-Ayland wrote:
For the older machines (such as Mac and SPARC) the DT nodes representing
bootdevices for disk nodes are irregular for mainly historical reasons.
Since the majority of bootdevice nodes fo
On Wed, Aug 08, 2018 at 05:15:48PM +0200, Igor Mammedov wrote:
> Reuse CPU hotplug IO registers for passing a CST entry
> containing package for shalowest C1 using mwait and
> read it out in guest with new CCST AML method.
I don't see how 1 entry is enough. We need to describe full _CST package so
On Wed, Aug 08, 2018 at 09:39:49PM +0200, Laszlo Ersek wrote:
> On 08/08/18 21:19, Mark Cave-Ayland wrote:
> > For the older machines (such as Mac and SPARC) the DT nodes representing
> > bootdevices for disk nodes are irregular for mainly historical reasons.
> >
> > Since the majority of bootdevi
On Wed, Aug 08, 2018 at 08:19:51PM +0100, Mark Cave-Ayland wrote:
> For the older machines (such as Mac and SPARC) the DT nodes representing
> bootdevices for disk nodes are irregular for mainly historical reasons.
>
> Since the majority of bootdevice nodes for these machines either do not have a
On 08/08/18 21:19, Mark Cave-Ayland wrote:
> For the older machines (such as Mac and SPARC) the DT nodes representing
> bootdevices for disk nodes are irregular for mainly historical reasons.
>
> Since the majority of bootdevice nodes for these machines either do not have a
> separate disk node or
On 06/08/2018 16:33, Emanuele Giuseppe Esposito wrote:
> From: Paolo Bonzini
>
> Because qtest does not support s390 channel I/O, s390 only performs smoke
> tests on
> those few devices that do not have any functional tests. Therefore, every
> time we
> add functional tests for a virtio device
On 06/08/2018 16:33, Emanuele Giuseppe Esposito wrote:
> Add pc machine for the x86_64 QEMU binary. This machine contains an
> i440FX-pcihost
> driver, that contains itself a pci-bus-pc that produces the pci-bus interface.
>
> Signed-off-by: Emanuele Giuseppe Esposito
> ---
> tests/Makefile.inc
For the older machines (such as Mac and SPARC) the DT nodes representing
bootdevices for disk nodes are irregular for mainly historical reasons.
Since the majority of bootdevice nodes for these machines either do not have a
separate disk node or require different (custom) names then it is much eas
On 07/08/18 20:45, Eduardo Habkost wrote:
Is this sufficient, or are the compat properties supposed to be versioned
according to the QEMU machine version?
I never saw compat_properties being used for non-versioned
machines, but it should work for this use case as well.
But, I'm not sure this
Hi Johannes,
On 08/08/2018 11:16 AM, Johannes Thumshirn wrote:
> Add MEN z125 UART over MEN Chameleon Bus emulation.
>
> Signed-off-by: Johannes Thumshirn
> ---
> hw/char/Makefile.objs | 1 +
> hw/char/serial-mcb.c | 97
> +++
> 2 files changed
* Collin Walling (wall...@linux.ibm.com) wrote:
> When typing 'help' followed by an unknown command, QEMU will
> not print anything to the command line to let the user know
> they typed a bad command. Let's fix this by printing a message
> to the monitor when this happens. For example:
>
> (qe
On 06/08/2018 16:33, Emanuele Giuseppe Esposito wrote:
> Add pci-bus-pc node, move QPCIBusPC struct declaration in its header
> (since it will be needed by other drivers) and introduce a setter method
> for drivers that do not need to allocate but have to initialize QPCIBusPC.
>
> Signed-off-by: E
On 08/08/2018 06:16 PM, Alberto Garcia wrote:
On Wed 08 Aug 2018 04:35:19 PM CEST, Leonid Bloch wrote:
The way I see it: there are two simple changes from the user's point of
view (they can even be two separate patches).
1) The default l2-cache-size is now 32MB. DEFAULT_L2_CACHE_CLUSTERS is
Thomas Huth wrote:
> On 08/08/2018 01:48 PM, Juan Quintela wrote:
>> Signed-off-by: Juan Quintela
>> ---
>> tests/Makefile.include | 9 +
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/tests/Makefile.include b/tests/Makefile.include
>> index 4e5f47aac0..1105469daa
Thomas Huth wrote:
> On 08/08/2018 01:48 PM, Juan Quintela wrote:
>> If we ever changed that, just make the things that are different
>> explicit.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> default-configs/i386-softmmu.mak | 65 +---
>> 1 file changed, 1 insertion(
VMStateDescription vmstate_spapr_cpu_state was added by commit
b94020268e0b6 (spapr_cpu_core: migrate per-CPU data) to migrate per-CPU
data with the required vmstate registration and unregistration calls.
However the unregistration is being done only from vcpu creation error path
and not from CPU d
"echo $solaris "
That gives:
# /usr/xpg4/bin/sh ../configure --extra-cflags="-m32"
--target-list=x86_64-softmmu
yes
Install prefix/usr/local
BIOS directory/usr/local/share/qemu
firmware path /usr/local/share/qemu-firmware
binary directory /usr/local/bin
library di
Am 07.08.2018 um 06:33 hat John Snow geschrieben:
> Change the manual deferment to commit_complete into the implicit
> callback to job_exit.
>
> Signed-off-by: John Snow
There is one tricky thing in this patch that the commit message could be
a bit more explicit about, which is moving job_comple
Alex Bennée writes:
> We can abuse the CS_OPT_SKIPDATA by providing a call back when
> capstone can't disassemble something. The passing of the string to the
> dump function is a little clunky but works.
>
> Signed-off-by: Alex Bennée
> ---
> disas.c | 30 +
Am 08.08.2018 um 17:50 hat John Snow geschrieben:
>
>
> On 08/08/2018 10:57 AM, Kevin Wolf wrote:
> > Am 07.08.2018 um 06:33 hat John Snow geschrieben:
> >> Jobs presently use both an Error object in the case of the create job,
> >> and char strings in the case of generic errors elsewhere.
> >>
>
On 08/08/2018 10:57 AM, Kevin Wolf wrote:
> Am 07.08.2018 um 06:33 hat John Snow geschrieben:
>> Jobs presently use both an Error object in the case of the create job,
>> and char strings in the case of generic errors elsewhere.
>>
>> Unify the two paths as just j->err, and remove the extra argu
Am 08.08.2018 um 17:38 hat John Snow geschrieben:
> On 08/08/2018 11:23 AM, Kevin Wolf wrote:
> > Am 08.08.2018 um 06:02 hat Jeff Cody geschrieben:
> >> On Tue, Aug 07, 2018 at 12:33:30AM -0400, John Snow wrote:
> >>> Most jobs do the same thing when they leave their running loop:
> >>> - Store the
On 08/08/2018 11:23 AM, Kevin Wolf wrote:
> Am 08.08.2018 um 06:02 hat Jeff Cody geschrieben:
>> On Tue, Aug 07, 2018 at 12:33:30AM -0400, John Snow wrote:
>>> Most jobs do the same thing when they leave their running loop:
>>> - Store the return code in a structure
>>> - wait to receive this st
On Wed 08 Aug 2018 03:58:02 PM CEST, Alberto Garcia wrote:
> 1) If l2-cache-size > l2_metadata_size, then make l2-cache-size =
> l2_metadata_size. This is already useful on its own, even with the
> current default of 1MB.
>
> 2) Increase the default to 32MB. This won't waste additional me
On 06/08/2018 16:33, Emanuele Giuseppe Esposito wrote:
> Rename qpci_init_spapr in qpci_new_spapr, since the function actually
> allocates a new QPCIBusSPAPR and initialize it.
>
I think you should merge this one with 02/34.
Thanks,
Laurent
On Thu, 2 Aug 2018 11:18:08 +0200
Igor Mammedov wrote:
> On Thu, 26 Jul 2018 19:09:22 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Wed, Jul 25, 2018 at 05:53:35PM +0200, Igor Mammedov wrote:
> > > On Wed, 25 Jul 2018 15:44:37 +0300
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Wed,
Am 08.08.2018 um 06:02 hat Jeff Cody geschrieben:
> On Tue, Aug 07, 2018 at 12:33:30AM -0400, John Snow wrote:
> > Most jobs do the same thing when they leave their running loop:
> > - Store the return code in a structure
> > - wait to receive this structure in the main thread
> > - signal job comp
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