Hi,
> > I have a problem about screen resolution.
> > Recommended resolution of my guest OS is 1920x1080.
> > If a QEMU window size is 1920x1080, it is clear.
> > But, if I change smaller of a QEMU window size, it does not display
> > clearly.(ex: 1280x720)
> > In this case, QEMU windows size in
Currently the minimal supported version of glib is 2.22.
Since testing is done with a glib that claims to be 2.22, but in fact
has APIs from newer version of glib, this bug was not caught during
submit of the patch referenced below.
Replace g_realloc_n, which is available only since 2.24, with g_r
** Changed in: qemu (Ubuntu)
Importance: Critical => High
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https://bugs.launchpad.net/bugs/1771238
Title:
Not able to passthrough > 32 PCIe devices to a KVM Guest
Status in QEMU:
Am Mon, 14 May 2018 23:04:31 -0700 (PDT)
schrieb no-re...@patchew.org:
> vfio-helpers.c:525:17: error: assignment from incompatible pointer type
Does anyone happen to know what s390x is trying to do here?
Olaf
pgpHBYpHmh42k.pgp
Description: Digitale Signatur von OpenPGP
Hi,
This series failed build test on s390x host. Please find the details below.
Type: series
Message-id: 20180515055949.6446-1-o...@aepfle.de
Subject: [Qemu-devel] [PATCH] replace functions which are only available in
glib-2.24
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invo
Currently the minimal supported version of glib is 2.22.
Since testing is done with a glib that claims to be 2.22, but in fact
has APIs from newer version of glib, this bug was not caught during
submit of the patch referenced below.
Replace g_realloc_n, which is available only since 2.24, with g_r
Murilo Opsfelder Araujo writes:
> On Sat, May 12, 2018 at 09:53:54AM +0200, David Hildenbrand wrote:
>> On 11.05.2018 20:43, Eduardo Habkost wrote:
>> > On Fri, May 11, 2018 at 03:34:05PM -0300, Murilo Opsfelder Araujo wrote:
>> >> On Fri, May 11, 2018 at 03:19:52PM +0200, David Hildenbrand wrote
This issue has finally been addressed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=af1a5c3eb41521b4f090ad61
** Changed in: qemu
Status: New => Fix Released
** Changed in: qemu
Status: Fix Released => Fix Committed
--
You received this bug notification because you are a me
Daniel Henrique Barboza writes:
> On 05/14/2018 05:46 AM, Markus Armbruster wrote:
>> Markus Armbruster writes:
>>
>>> Daniel Henrique Barboza writes:
>>>
Ping
>>> Michael, you reviewed v4 (at least in part), can you have a look?
>> Have these patches fallen through the cracks?
>>
> Should
On 14.05.2018 19:30, Peter Maydell wrote:
> In gdb_accept(), we both fail to check all errors (notably
> that from socket_set_nodelay(), as Coverity notes in CID 1005666),
> and fail to return an error status back to our caller. Correct
> both of these things, so that errors in accept() result in o
On 14.05.2018 19:30, Peter Maydell wrote:
> Use the utility routine qemu_set_cloexec() rather than
> manually calling fcntl(). This lets us drop the #ifndef _WIN32
> guards and also means Coverity doesn't complain that we're
> ignoring the fcntl error return (CID 1005665, CID 1005667).
>
> Signed-
On Tue, May 15, 2018 at 2:35 AM, 유원상 wrote:
> Thank you for your cooperation.
>
> I need graphics maintainer's help.
> I think, multisampling support of QEMU UI is important for embedded virtual
> machine.
>
> I registered to qemu-devel.
> I hope to share a lot of information.
>
> How can I commen
On Mon, 05/14 13:23, Vladimir Sementsov-Ogievskiy wrote:
> > So, you agree, that dropping all bitmaps after inactivation is good
> > idea.. The second question, is it possible to not drop them? Is there a
> > way, to check that disk was not changed after pair of
> > inactivate-invalidate? I have an
** Changed in: qemu (Ubuntu)
Importance: Undecided => Critical
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https://bugs.launchpad.net/bugs/1769053
Title:
Cannot start a guest with more than 1TB of RAM
Status in QEMU:
Inco
Public bug reported:
Using an Ubuntu Server 16.04-based host with KVM hypervisor installed,
we are unable to launch a vanilla Ubuntu Server 16.04.4 guest with >= 32
PCIe devices. It is 100% reproducible. Using fewer PCIe devices works
fine. We are using the vanilla kvm and qemu packages from the C
'test.hex' file is a bare metal ARM software stored in Hexadecimal
Object Format. When it's loaded by QEMU, it will print "Hello world!\n"
on console.
`pre_store` array in 'hexloader-test.c' file, stores the binary format
of 'test.hex' file, which is used to verify correctness.
Reviewed-by: Stefa
This patch adds Intel Hexadecimal Object File format support to
the loader. The file format specification is available here:
http://www.piclist.com/techref/fileext/hex/intel.htm
The file format is mainly intended for embedded systems
and microcontrollers, such as Micro:bit Arduino, ARM, STM32, et
These series of patchs implement Intel Hexadecimal File loader and
add QTest testcase to verify the correctness of Loader.
v1:
-- Basic version.
v2:
-- Replace `do{}while(cond);` block with `for(;;)` block.
v3:
-- Add two new files information in MAINTAINERS.
v4:
-- Correct the 'test.hex' p
Hello,
I want to know the flow of how devices read/write function be called by
code_gen_buffer().
Take pl110_write() for example, I set a breakpoint in pl110_write(), and
the backtrace shows bellow.
(gdb)
#0 * pl110_write* (opaque=0x56e8f3f0, offset=28, val=0, size=4) at
hw/display/pl110.c:3
On Mon, May 14, 2018 at 12:00:07PM +0200, David Hildenbrand wrote:
> Some architectures might support memory devices, while they don't
> support DIMM/NVDIMM. So let's
> - Rename CONFIG_MEM_HOTPLUG to CONFIG_MEM_DEVICE
> - Intriduce CONFIG_DIMM and use it similarly to CONFIG NVDIMM
Since you're res
Set the interrupt-controller ndev to the correct number taken from the
HiFive Unleashed board.
Signed-off-by: Alistair Francis
Reviewed-by: Michael Clark
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f
Signed-off-by: Alistair Francis
Reviewed-by: Michael Clark
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f71527eaff..46459cd368 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -194,7 +194,
To allow Linux to ennumerate devices on the /soc/ node set it as a
"simple-bus".
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3883d7ff9c..f438a72c27 100644
--- a/hw/risc
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_e.c | 97 +++--
include/hw/riscv/sifive_e.h | 16 +-
2 files changed, 86 insertions(+), 27 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index e4ecb7aa4b..384b456540 100644
--- a
Connect the Cadence GEM ethernet device. This also requires us to
expose the plic interrupt lines.
Signed-off-by: Alistair Francis
Reviewed-by: Michael Clark
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/sifive_u.c | 50
Instead of creating the interrupt in lines with qemu_allocate_irq() use
qdev_init_gpio_in() as this gives us the ability to use the qdev*gpio*()
helpers later on.
Signed-off-by: Alistair Francis
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael Clark
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.
We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.
Signed-off-by: Alistair Francis
Reviewed-by: Michael Clark
---
hw/riscv/sifive_u.c
This series has three tasks:
1. To convert the SiFive U and E machines into SoCs and boards
2. To connect the Cadence GEM device to the SiFive U board
3. Fix some device tree problems with the SiFive U board
After this series the SiFive E and U boards have their SoCs split into
seperate QEMU o
On Mon, May 14, 2018 at 12:00:08PM +0200, David Hildenbrand wrote:
> From: Igor Mammedov
>
> it will allow to return another hotplug handler than the default
> one for a specific bus based device type. Which is needed to handle
> non trivial plug/unplug sequences that need the access to resources
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Monday, May 14, 2018 4:12 PM
> To: Moger, Babu
> Cc: m...@redhat.com; mar...@redhat.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; ge...@hostfission.com;
> k...@tripleback.net; qemu-deve
> -Original Message-
> From: Eduardo Habkost [mailto:ehabk...@redhat.com]
> Sent: Monday, May 14, 2018 2:47 PM
> To: Moger, Babu
> Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-devel@nongnu.org;
> k...@vger.kernel.org;
On 2018-05-09 18:26, Kevin Wolf wrote:
> This adds a test case that tests the new job-* QMP commands with
> mirror and backup block jobs.
>
> Signed-off-by: Kevin Wolf
> ---
> tests/qemu-iotests/219 | 201
> tests/qemu-iotests/219.out | 327
> +++
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> Since we introduced an explicit status to block job, BlockJob.completed
> is redundant because it can be derived from the status. Remove the field
> from BlockJob and add a function to derive it from the status at the Job
> level.
>
You're braver than
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> While we already moved the state related to job pausing to Job, the
> functions to do were still BlockJob only. This commit moves them over to
> Job.
>
> Signed-off-by: Kevin Wolf
I'm slightly sad about the new callback, because it still seems silly
On 2018-05-09 18:26, Kevin Wolf wrote:
> qmp_to_opts() used to be a method of QMPTestCase, but recently we
> started to add more Python test cases that don't make use of
> QMPTestCase. In order to make the method usable there, move it to VM.
>
> Signed-off-by: Kevin Wolf
> ---
> tests/qemu-iotes
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> There is nothing block layer specific about block_job_sleep_ns(), so
> move the function to Job.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block/blockjob_int.h | 11 ---
> include/qemu/job.h | 17 +
> block/backu
On 2018-05-09 18:26, Kevin Wolf wrote:
> This adds a minimal query-jobs implementation that shouldn't pose many
> design questions. It can later be extended to expose more information,
> and especially job-specific information.
>
> Signed-off-by: Kevin Wolf
> ---
> qapi/block-core.json | 18
On Sat, May 12, 2018 at 09:53:54AM +0200, David Hildenbrand wrote:
> On 11.05.2018 20:43, Eduardo Habkost wrote:
> > On Fri, May 11, 2018 at 03:34:05PM -0300, Murilo Opsfelder Araujo wrote:
> >> On Fri, May 11, 2018 at 03:19:52PM +0200, David Hildenbrand wrote:
> >>> While s390x has no real interfa
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> This commit moves some core functions for dealing with the job coroutine
> from BlockJob to Job. This includes primarily entering the coroutine
> (both for the first and reentering) and yielding explicitly and at pause
> points.
>
> Signed-off-by: Kevi
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 1f87ad6b2e..e7c96ca990 100644
--- a/target/openrisc/translat
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 116 +--
target/openrisc/insns.decode | 12
2 files changed, 70 insertions(+), 58 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 120 +--
target/openrisc/insns.decode | 15 +
2 files changed, 73 insertions(+), 62 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 55 +++-
target/openrisc/insns.decode | 5
2 files changed, 27 insertions(+), 33 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 279 +++
target/openrisc/insns.decode | 35 -
2 files changed, 151 insertions(+), 163 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/transla
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 150 +--
target/openrisc/insns.decode | 12 +++
2 files changed, 84 insertions(+), 78 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
From: Richard Henderson
The architecture manual is unclear about this, but the or1ksim
does writeback before the exception. This requires splitting
the helpers in half, with the exception raised by the second.
Acked-by: Stafford Horne
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Hen
Rebased on master to resolve conflicts with Emilio Cota's
TranslatorOps patch set.
r~
The following changes since commit bbd87423ea0c436c55bbc3f9c23d4f811d1f3f29:
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
into staging (2018-05-14 11:08:16 +0100)
are availabl
On 2018-05-09 18:26, Kevin Wolf wrote:
> This moves block_job_dismiss() to the Job layer.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block/blockjob.h | 9 -
> include/qemu/job.h | 7 ++-
> blockdev.c | 8 +---
> blockjob.c | 13
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> Signed-off-by: Kevin Wolf
Hmm, this one is a bit more than just code motion due to the way the
aio_context acquisition has changed. I think at a minimum a good commit
message is warranted.
> ---
> include/block/blockjob.h | 5
> include/b
On 2018-05-09 18:26, Kevin Wolf wrote:
> This adds QMP commands that control the transition between states of the
> job lifecycle.
>
> Signed-off-by: Kevin Wolf
> ---
> qapi/job.json | 112 ++
> job-qmp.c | 140
> ++
Reduce the number of ifdefs. Correct the result for OpenRISC
and TriCore (although TriCore fixed in target-specific code).
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/fpu/softfloat-spe
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 356 +--
target/openrisc/insns.decode | 21 +++
2 files changed, 148 insertions(+), 229 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate
For each operand, pass a single enumeration instead of a pair of booleans.
The commit also merges multiple different ifdef-selected implementations
of pickNaN into a single function whose body is ifdef-selected.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-speci
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 322 +++
target/openrisc/insns.decode | 76 ++---
2 files changed, 229 insertions(+), 169 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/tra
We will need these helpers within softfloat-specialize.h, so move
the definitions above the include. After specialization, they will
not always be used so mark them to avoid the Werror.
Signed-off-by: Richard Henderson
---
fpu/softfloat.c | 30 --
1 file changed, 16
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 62 +++-
target/openrisc/insns.decode | 6
2 files changed, 32 insertions(+), 36 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 275 +--
target/openrisc/insns.decode | 24 +++
2 files changed, 160 insertions(+), 139 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate
Only MIPS requires snan_bit_is_one to be variable. While we are
specializing softfloat behaviour, allow other targets to eliminate
this runtime check.
Cc: Aurelien Jarno
Cc: Yongbok Kim
Cc: David Gibson
Cc: Alexander Graf
Cc: Guan Xuetao
Signed-off-by: Richard Henderson
---
v5
- do not r
Begin with the 0x08 major opcode, the system instructions.
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 84 +--
target/openrisc/Makefile.objs | 9
target/openrisc/insns.decode | 28
3 files chan
We have already checked the arguments for SNaN;
we don't need to do it again.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 44 +-
1 file changed, 34 insertions(+), 10 deletions(-)
diff --git a/fpu/softfloat-spe
Acked-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 41
target/openrisc/insns.decode | 3 +++
2 files changed, 16 insertions(+), 28 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
Isolate the target-specific choice to 3 functions instead of 6.
The code in floatx80_default_nan tried to be over-general. There are
only two targets that support this format: x86 and m68k. Thus there
is no point in inventing a mechanism for snan_bit_is_one.
Move routines that no longer have if
From: Alex Bennée
This allows us to delete a lot of additional boilerplate
code which is no longer needed.
Signed-off-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v2
- pass FloatFmt to float_to_float instead of sizes
- split AHP handling to another patch
- use rth's suggested re
This is now handled properly by the generic softfloat code.
Cc: Alexander Graf
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/fpu_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/s390x/fpu_helper.c b/target/s390x
For each operand, pass a single enumeration instead of a pair of booleans.
The commit also merges multiple different ifdef-selected implementations
of pickNaNMulAdd into a single function whose body is ifdef-selected.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat
Isolate the target-specific choice to 2 functions instead of 6.
The code in float16_default_nan was only correct for ARM, MIPS, and X86.
Though float16 support is rare among our targets.
The code in float128_default_nan was arguably wrong for Sparc. While
QEMU supports the Sparc 128-bit insns, n
Reviewed-by: Peter Maydell
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/softfloat.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c
index e41b07d042..6ec227e20f 100644
--- a/target/m68k/softf
This is now handled properly by the generic softfloat code.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/hppa/op_helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index a3af62daf7..912e8d5be4 100644
--- a/ta
These functions are now unused.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 63 --
include/fpu/softfloat.h| 5 ---
2 files changed, 68 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-
This is now handled properly by the generic softfloat code.
Cc: Aurelien Jarno
Cc: Yongbok Kim
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/mips/msa_helper.c | 4
target/mips/op_helper.c | 2 --
2 files changed, 6 deletions(-)
diff --git a/target/mips/msa_help
From: Alex Bennée
For float16 ARM supports an alternative half-precision format which
sacrifices the ability to represent NaN/Inf in return for a higher
dynamic range. The new FloatFmt flag, arm_althp, is then used to
modify the behaviour of canonicalize and round_canonical with respect
to repre
From: Alex Bennée
Instead of passing env and leaving it up to the helper to get the
right fpstatus we pass it explicitly. There was already a get_fpstatus
helper for neon for the 32 bit code. We also add an get_ahp_flag() for
passing the state of the alternative FP16 format flag. This leaves
scop
With a canonical representation of NaNs, we can return the
default nan directly rather than delay the expansion until
the final format is known.
Note one case where we uselessly assigned to a.sign, which was
overwritten/ignored later when expanding float_class_dnan.
Reviewed-by: Peter Maydell
Si
This is now handled properly by the generic softfloat code.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Reviewed-by: Michael Clark
Signed-off-by: Richard Henderson
---
target/riscv/fpu_helper.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/targe
From: Alex Bennée
The ARM ARM specifies FZ16 is suppressed for conversions. Rather than
pushing this logic into the softfloat code we can simply save the FZ
state and temporarily disable it for the softfloat call.
Reviewed-by: Peter Maydell
Signed-off-by: Alex Bennée
Signed-off-by: Richard Hen
This is now handled properly by the generic softfloat code.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 1 -
target/arm/helper.c | 12 ++--
2 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/arm/helper-a64.c b/target
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 6 +++---
target/arm/helper.c | 12 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 4f8034c513..6f0eb83661 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 15 +++
fpu/softfloat.c| 12 ++--
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 4fc9ea4ac0
With a canonical representation of NaNs, we can silence an SNaN
immediately rather than delay until the final format is known.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 23 ++
fpu/softfloat.c| 40 ++--
We want to be able to specialize on the canonical representation.
Reviewed-by: Peter Maydell
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
fpu/softfloat.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.
Move the ifdef inside the relevant functions instead of
duplicating the function declarations.
Reviewed-by: Peter Maydell
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 100 +++--
1 file changed, 40 insertions(+), 60 d
Shift the NaN fraction to a canonical position, much like we
do for the fraction of normal numbers. This will facilitate
manipulation of NaNs within the shared code paths.
Signed-off-by: Richard Henderson
---
fpu/softfloat.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --gi
The new function assumes that the input is an SNaN and
does not double-check.
Reviewed-by: Peter Maydell
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 174 +
include/fpu/softfloat.h| 5 ++
2 files changed, 1
This is my SNaN patch set, Alex's float-float refactor, and a couple
of other random outstanding fpu patches. This has been reordered so
as to be bisectable, since the float-float refactor requires the snan
work to avoid breakage.
This was built on top of pm215/target-arm.next to make it easier t
From: Petr Tesarik
The significand is passed to normalizeRoundAndPackFloat128() as high
first, low second. The current code passes the integer first, so the
result is incorrectly shifted left by 64 bits.
This bug affects the emulation of s390x instruction CXLGBR (convert
from logical 64-bit bina
On 2018-05-09 18:26, Kevin Wolf wrote:
> This adds a QMP event that is emitted whenever a job transitions from
> one status to another. For the event, a new qapi/job.json schema file is
> created which will contain all job-related definitions that aren't tied
> to the block layer.
>
> Signed-off-b
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> When block jobs need an AioContext, they just take it from their main
> block node. Generic jobs don't have a main block node, so we need to
> assign them an AioContext explicitly.
>
> Signed-off-by: Kevin Wolf
Nothing uses the field yet, but so far
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> We cannot yet move the whole logic around job cancelling to Job because
> it depends on quite a few other things that are still only in BlockJob,
> but we can move the cancelled field at least.
>
> Signed-off-by: Kevin Wolf
Reviewed-by: John Snow
The qmp/hmp command 'system_wakeup' is simply a direct call to
'qemu_system_wakeup_request' from vl.c. This function verifies if
runstate is SUSPENDED and if the wake up reason is valid before
proceeding.
However, no error or warning is thrown if any of those
pre-requirements isn't met. There is n
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> This moves reference counting from BlockJob to Job.
>
> In order to keep calling the BlockJob cleanup code when the job is
> deleted via job_unref(), introduce a new JobDriver.free callback. Every
> block job must use block_job_free() for this callback
On 2018-05-09 18:26, Kevin Wolf wrote:
> BlockJob has fields .offset and .len, which are actually misnomers today
> because they are no longer tied to block device sizes, but just progress
> counters. As such they make a lot of sense in generic Jobs.
>
> This patch moves the fields to Job and rena
On 2018-05-09 18:26, Kevin Wolf wrote:
> The transition to the READY state was still performed in the BlockJob
> layer, in the same function that sent the BLOCK_JOB_READY QMP event.
>
> This patch brings the state transition to the Job layer and implements
> the QMP event using a notifier called f
On 2018-05-09 18:26, Kevin Wolf wrote:
> This moves the logic that implements job transactions from BlockJob to
> Job.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block/blockjob.h | 54 --
> include/block/blockjob_int.h | 10 --
> include/qemu/job.h | 71 +++--
On Tue, Apr 10, 2018 at 07:16:07PM -0400, Babu Moger wrote:
> Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
> feature is supported. This is required to support hyperthreading feature
> on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
>
> Signed-off-by: B
On 2018-05-09 18:26, Kevin Wolf wrote:
> Instead of having a 'bool ready' in BlockJob, add a function that
> derives its value from the job status.
>
> At the same time, this fixes the behaviour to match what the QAPI
> documentation promises for query-block-job: 'true if the job may be
> complete
On 2018-05-09 18:26, Kevin Wolf wrote:
> This moves block_job_dismiss() to the Job layer.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block/blockjob.h | 9 -
> include/qemu/job.h | 7 ++-
> blockdev.c | 8 +---
> blockjob.c | 13
On 05/14/2018 05:46 AM, Markus Armbruster wrote:
Markus Armbruster writes:
Daniel Henrique Barboza writes:
Ping
Michael, you reviewed v4 (at least in part), can you have a look?
Have these patches fallen through the cracks?
Should I re-send it? Not sure if this is applicable in the cur
On 2018-05-09 18:26, Kevin Wolf wrote:
> This moves block_job_yield() to the Job layer.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block/blockjob_int.h | 8
> include/qemu/job.h | 9 +++--
> block/backup.c | 2 +-
> block/mirror.c | 2 +-
On 05/09/2018 12:26 PM, Kevin Wolf wrote:
> This moves BlockJob.status and the closely related functions
> (block_)job_state_transition() and (block_)job_apply_verb to Job. The
> two QAPI enums are renamed to JobStatus and JobVerb.
>
> Signed-off-by: Kevin Wolf
In good faith that the TODOs dis
On 2018-05-09 18:26, Kevin Wolf wrote:
> This moves the top-level job completion and cancellation functions from
> BlockJob to Job.
>
> Signed-off-by: Kevin Wolf
> ---
> include/block/blockjob.h | 55 ---
> include/block/blockjob_int.h | 18 --
> include/q
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