These fields are marked WARL (Write Any Values, Reads
Legal Values) in the RISC-V Privileged Architecture
Specification so instead of raising exceptions,
illegal writes are silently dropped.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Mich
Previously the mycycle/minstret CSRs and rdcycle/rdinstret
psuedo instructions would return the time as a proxy for an
increasing instruction counter in the absence of having a
precise instruction count. If QEMU is invoked with -icount,
the mcycle/minstret CSRs and rdcycle/rdinstret psuedo
instruct
Pointless indirection. Other ports use EM_ constants directly.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.
It seems the RISC-V WARL behaviour is preferred to having to
trap overhead versus simply reading back the value and checking
if the write took (saves hundreds of cycles and
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Later we can add RISCV_FEATURE_VECTORED_TRAPS however
until then the correct behavior for WARL (Write Any, Read
Legal) fi
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/i
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification
defines the canonical order for extensions in the ISA string. It is
silent on the position of the E extension however E is a substitute
for I so it must come early in the extension list order. A comment
is added to state E and I
This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Cc: Peter Maydell
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mat
The sifive_u machine already marks its ROM readonly however
it has the wrong base address for its mask ROM. This patch
fixes the sifive_u mask ROM base address.
This commit makes all other boards consistently use mask_rom
as the variable name for their ROMs. Boards that use device
tree now check t
The mstatus.MXR alias in sstatus should only be writable
by S-mode if the privileged ISA version >= v1.10. Also MXR
was masked in sstatus CSR read but not sstatus CSR writes.
Now we correctly mask sstatus.mxr in both read and write.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Privileged ISA v1.9.1 defines mscounteren and mucounteren:
* mscounteren contains a mask of counters available to S-mode
* mucounteren contains a mask of counters available to U-mode
Privileged ISA v1.10 defines mcounteren and scounteren:
* mcounteren contains a mask of counters available to S-m
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
include/hw/riscv/spike.h | 4 ++--
include/hw/riscv/virt.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unne
Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by
mtval/stval must be set on all exceptions but zero is
a legal value if there is no exception specific info.
Placing the instruction bytes for illegal instruction
exceptions in mtval/stval is an optional feature and
is currently not supported by QEMU RISC-V.
Cc: Sagar Karandikar
Cc: Bastian Koppel
This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 2 +-
1 file changed
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/risc
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into
staging (2018-05-04 14:42:46 +0100)
are available in the git repository at:
https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-2.13-pu
FYI - I've dropped this patch to qemu/include/sysemu/device_tree.h
and qemu/device_tree.c in favor of calling fdt_pack() and fdt_totalsize().
On Sun, May 6, 2018 at 9:59 AM, Michael Clark wrote:
>
>
> On Sat, May 5, 2018 at 11:48 PM, David Gibson > wrote:
>
>> On Sat, May 05, 2018 at 11:44:25AM
On Sat, May 5, 2018 at 11:48 PM, David Gibson
wrote:
> On Sat, May 05, 2018 at 11:44:25AM +0100, Peter Maydell wrote:
> > cc'ing David -- is this the best way to do this?
> >
> > (It would be nicer if libfdt would just dynamically
> > reallocate the buffer as needed,
>
> That's a deliberate desig
I'm seeing the same Win10 I/O stall problem with qemu 2.12, but with a vm with
BIOS, not UEFI.
The solution for me is only dowgrading for now.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1769189
T
On Fri, 27 Apr 2018, Peter Xu wrote:
> On Thu, Apr 26, 2018 at 11:33:53PM +, Eric Wheeler wrote:
> > Hello all,
>
> Hi, Eric,
>
> >
> > This is my first time inside of the qemu code, so your help is greatly
> > appreciated!
> >
> > I have been experimenting with stop/start of VMs to/from
On 05/04/2018 10:49 PM, Stafford Horne wrote:
> I reviewed all and everything seems good, do you plan to send the PR during
> the
> merge window?
Yes, I can do that.
r~
During incoming postcopy, the destination qemu will invoke
qemu_rdma_wait_comp_channel in a seprate thread. So does not use rdma
yield, and poll the completion channel fd instead.
Signed-off-by: Lidong Chen
Reviewed-by: Dr. David Alan Gilbert
---
migration/rdma.c | 4 +++-
1 file changed, 3 ins
The channel_close maybe invoked by different threads. For example, source
qemu invokes qemu_fclose in main thread, migration thread and return path
thread. Destination qemu invokes qemu_fclose in main thread, listen thread
and COLO incoming thread.
Add a mutex in QEMUFile struct to avoid concurren
If start a RDMA migration with postcopy enabled, the source qemu
establish a dedicated connection for return path.
Signed-off-by: Lidong Chen
Reviewed-by: Dr. David Alan Gilbert
---
migration/rdma.c | 94 ++--
1 file changed, 91 insertions(+),
This patch implements bi-directional RDMA QIOChannel. Because different
threads may access RDMAQIOChannel currently, this patch use RCU to protect it.
Signed-off-by: Lidong Chen
---
migration/colo.c | 2 +
migration/migration.c| 2 +
migration/postcopy-ram.c | 2 +
migration/ra
The RDMA QIOChannel does not support bi-directional communication, so when RDMA
live migration with postcopy enabled, the source qemu return path get qemu file
error.
These patches implement bi-directional communication for RDMA QIOChannel and
disable the RDMA WRITE during the postcopy phase.
Because qio_channel_rdma_writev and qio_channel_rdma_readv maybe invoked
by different threads concurrently, this patch removes unnecessary variables
len in QIOChannelRDMA and use local variable instead.
Signed-off-by: Lidong Chen
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Daniel P. Berrang
RDMA WRITE operations are performed with no notification to the destination
qemu, then the destination qemu can not wakeup. This patch disable RDMA WRITE
after postcopy started.
Signed-off-by: Lidong Chen
Reviewed-by: Dr. David Alan Gilbert
---
migration/qemu-file.c | 8 ++--
migration/rdm
On Thu, May 03, 2018 at 09:54:01PM +, Alistair Francis wrote:
> On Thu, May 3, 2018 at 2:44 AM Edgar E. Iglesias
> wrote:
>
> > From: "Edgar E. Iglesias"
>
> > Prepare for 64-bit addresses.
> > This makes no functional difference as the upper parts of
> > the 64-bit addresses are not yet re
On Thu, May 03, 2018 at 08:30:13PM +, Alistair Francis wrote:
> On Thu, May 3, 2018 at 2:28 AM Edgar E. Iglesias
> wrote:
>
> > From: "Edgar E. Iglesias"
>
> > Name special registers we support.
>
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target/microblaze/translate.c | 4 ++--
>
On Thu, May 03, 2018 at 12:12:40PM -0700, Richard Henderson wrote:
> On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote:
> > +trap_userspace(dc, ea);
>
> Missing if (...) return?
Yup, fixed in v2.
Thanks,
Edgar
On Thu, May 03, 2018 at 12:03:19PM -0700, Richard Henderson wrote:
> On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Extend special registers to 64-bits. This is in preparation for
> > MFSE/MTSE, moves to and from extended special registers.
> >
> > Signed-
I've read architecture manual again and found that my actual implementation
differs from it.
How it should be (my updated view, thanks to your note).
The "Exception Processing" chapters stays than "EPCR (no delay slot)" should
be "Address of next not executed instruction". And there is nothing
On Thu, May 03, 2018 at 11:21:54AM -0700, Richard Henderson wrote:
> On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Use TCGv for load/store addresses, allowing for future
> > computation of 64-bit load/store address.
> >
> > No functional change.
> >
> >
On Sat, May 05, 2018 at 11:44:25AM +0100, Peter Maydell wrote:
> cc'ing David -- is this the best way to do this?
>
> (It would be nicer if libfdt would just dynamically
> reallocate the buffer as needed,
That's a deliberate design tradeoff. Because it's designed to be
embeddable in really limit
cc'ing David -- is this the best way to do this?
(It would be nicer if libfdt would just dynamically
reallocate the buffer as needed, and then tell you
the final size, rather than having to specify a
maximum buffer size up front, but given the API we
have a "tell me how big this thing actually is"
qemu-img info with a block device which has a qcow2 format always
return 0 for disk size, and this can not reflect the qcow2 size
and the used space of the block device. This patch return the
allocated size of qcow2 as the disk size.
Signed-off-by: Ivan Ren
---
block/qcow2.c | 54 +++
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