Hi Jason,
On 2018/2/2 11:11, Jason Wang wrote:
On 2018年01月26日 11:08, Jay Zhou wrote:
If netdev_add tap,id=net0,...,vhost=on failed in net_init_tap_one(),
the followed up device_add virtio-net-pci,netdev=net0 will fail
too, prints:
TUNSETOFFLOAD ioctl() failed: Bad file descriptor TUNSETOF
On Thu, 2018-02-01 at 20:47 +0100, Greg Kurz wrote:
> Detected by Coverity (CID 1385702). This fixes the recently added
> hypercall
> to let guests properly apply Spectre and Meltdown workarounds.
>
> Fixes: c59704b25473 "target/ppc/spapr: Add H-Call
> H_GET_CPU_CHARACTERISTICS"
> Signed-off-by: G
在 2018/2/1 下午8:02, Cornelia Huck 写道:
On Thu, 1 Feb 2018 12:33:01 +0100
Pierre Morel wrote:
On 31/01/2018 12:44, Cornelia Huck wrote:
On Tue, 30 Jan 2018 10:47:15 +0100
Yi Min Zhao wrote:
When registering ioat, pba should be comprised of leftmost 52 bits and
rightmost 12 binary zeros, a
On 2018年01月26日 11:08, Jay Zhou wrote:
If netdev_add tap,id=net0,...,vhost=on failed in net_init_tap_one(),
the followed up device_add virtio-net-pci,netdev=net0 will fail
too, prints:
TUNSETOFFLOAD ioctl() failed: Bad file descriptor TUNSETOFFLOAD
ioctl() failed: Bad file descriptor
The
On 2018年02月01日 16:20, Zihan Yang wrote:
net_socket_listen_init directly uses parse_host_port, bind and listen,
change it to use functions in include/qemu/sockets.h
Signed-off-by: Zihan Yang
---
net/socket.c | 30 +-
1 file changed, 9 insertions(+), 21 deletions(
Add one more layer to our stack of MemoryRegions, this base region
allows us to register BARs independently of the vfio region or to
extend the size of BARs which do map to a region. This will be
useful when we want hypervisor defined BARs or sections of BARs,
for purposes such as relocating MSI-X
On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote:
> On a POWER9 processor, the first doubleword of the PTCR indicates
> whether the partition uses HPT or Radix Trees translation. Use that
> bit to check for radix mode on powernv QEMU machines.
The above isn't quite right.
On a POWER9 pro
On Fri, 2018-02-02 at 13:34 +1100, Suraj Jitindar Singh wrote:
> On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote:
> > The Partition Table Control Register (PTCR) is a hypervisor
> > privileged
> > SPR. It contains the host real address of the Partition Table and
> > its
> > size.
> >
> >
On 29/01/18 16:03, Alexey Kardashevskiy wrote:
> On 15/12/17 15:47, Alexey Kardashevskiy wrote:
>> On 26/10/17 12:41, Alexey Kardashevskiy wrote:
>>> The "-machine xxx,help" prints kernel-irqchip possible values as
>>> "OnOffSplit", this adds separators to the printed line.
>>>
>>> Also, since only
On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote:
> The Partition Table Control Register (PTCR) is a hypervisor
> privileged
> SPR. It contains the host real address of the Partition Table and its
> size.
>
> Signed-off-by: Cédric Le Goater
> ---
> target/ppc/cpu.h| 2 ++
>
On 01/02/18 04:22, Markus Armbruster wrote:
> Alexey Kardashevskiy writes:
>
>> There is already 'device-list-properties' which does most of the job,
>> however it does not handle everything returned by qom-list-types such
>> as machines as they inherit directly from TYPE_OBJECT and not TYPE_DEVI
On 02/01/2018 06:23 PM, Stefan Berger wrote:
Split off the tpm_crb_reset function part from tpm_crb_realize
that we need to run every time the machine resets.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_crb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/tpm/tpm_crb.c b/hw/tpm
On 2018/2/2 1:06, Michael S. Tsirkin wrote:
Yes, I plan to merge it in the next pull.
Pls don't assume anything until it's merged upstream though,
some issues surface late.
Okay, I see. Thanks for reviewing!
Regards,
Jay
On Thu, Feb 01, 2018 at 11:29:15AM +, Zhoujian (jay) wrote:
Hi M
On Mon, Jan 22, 2018 at 7:30 PM, Philippe Mathieu-Daudé wrote:
> replace switch(single case) -> if()
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/sd/sd.c | 56 ++--
> 1 file changed, 26 inserti
List all possible valid CPU options.
Signed-off-by: Alistair Francis
Reviewed-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
---
An implementation for single CPU machines is still being discussed. A
solution proposed by Eduardo is this:
1) Change the default on TYPE_MACHINE to:
List all possible valid CPU options.
Although the board only ever has a Cortex-M3 we mark the Cortex-M4 as
supported because the Netduino2 Plus supports the Cortex-M4 and the
Netduino2 Plus is similar to the Netduino2.
Signed-off-by: Alistair Francis
Reviewed-by: Eduardo Habkost
Reviewed-by: Ph
The BCM2836 uses a Cortex-A7 not a Cortex-A15. Update the device to use
the correct CPU.
https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
---
V3:
- Use ARM_CPU_TY
List all possible valid CPU options.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
V5:
- Use cpu_model names
V4:
- Remove spaces
V3:
- Make variable static
V2:
- Fixup alignment
hw/arm/xilinx_zynq.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/arm
As cpu_type is not a user visible string let's convert the
valid_cpu_types to compare against cpu_model instead. This way we have a
user friendly string to report back.
Once we have a cpu_type to cpu_model conversion this patch should be
reverted and we should use cpu_type instead.
Signed-off-by:
There are numorous QEMU machines that only have a single or a handful of
valid CPU options. To simplyfy the management of specificying which CPU
is/isn't valid let's create a property that can be set in the machine
init. We can then check to see if the user supplied CPU is in that list
or not.
I
List all possible valid CPU options.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
V5:
- Use cpu_model names
V4:
- Remove spaces
V3:
- Add static property
V2:
- Fix the indentation
hw/arm/raspi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/r
On Thu, Jan 18, 2018 at 1:25 AM, Lukáš Doktor wrote:
> Dne 18.1.2018 v 00:41 Alistair Francis napsal(a):
>> On Wed, Jan 17, 2018 at 12:05 AM, Cleber Rosa wrote:
>>> TL;DR
>>> =
>>>
>>> This is about how QEMU developers can get started with functional
>>> tests that are built on top of the Avo
On Wed, Jan 17, 2018 at 4:47 PM, Cleber Rosa wrote:
>
>
> On 01/17/2018 06:41 PM, Alistair Francis wrote:
>> On Wed, Jan 17, 2018 at 12:05 AM, Cleber Rosa wrote:
>>> TL;DR
>>> =
>>>
>>> This is about how QEMU developers can get started with functional
>>> tests that are built on top of the Av
On 01/02/2018 19:00, Alex Williamson wrote:
> On Tue, 16 Jan 2018 15:16:59 +0100
> Paolo Bonzini wrote:
>
>> From: Marc-André Lureau
>>
>> Fixes leaks such as:
>>
>> Direct leak of 2 byte(s) in 1 object(s) allocated from:
>> #0 0x7eff58beb850 in malloc (/lib64/libasan.so.4+0xde850)
>> #1
On Tue, 16 Jan 2018 15:16:59 +0100
Paolo Bonzini wrote:
> From: Marc-André Lureau
>
> Fixes leaks such as:
>
> Direct leak of 2 byte(s) in 1 object(s) allocated from:
> #0 0x7eff58beb850 in malloc (/lib64/libasan.so.4+0xde850)
> #1 0x7eff57942f0c in g_malloc ../glib/gmem.c:94
> #2
On 2018-01-26 16:00, Alberto Garcia wrote:
> Now that the code is ready to handle L2 slices we can finally add an
> option to allow configuring their size.
>
> An L2 slice is the portion of an L2 table that is read by the qcow2
> cache. Until now the cache was always reading full L2 tables, and
>
Quoting Eduardo Habkost (2018-01-26 12:08:16)
> It looks like there's some confusion here: I don't have
> additional proposed changes; the flag names and MSR code I
> mentioned are already merged on master (through this pull
> request).
Ah, my mistake, I thought the flags were being proposed as fo
Split off the tpm_crb_reset function part from tpm_crb_realize
that we need to run every time the machine resets.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_crb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c
index 687d255..624e2e9 100644
--- a/hw
The following two patches fix the resetting of the CRB interface
and wrap calls to st{w,l}_be_p in tpm_cmd_set_XYZ functions.
Stefan
Stefan Berger (2):
tpm: Split off tpm_crb_reset function
tpm: wrap stX_be_p in tpm_cmd_set_XYZ functions
hw/tpm/tpm_crb.c | 6 ++
hw/tpm/tpm_util.c |
Wrap the calls to stl_be_p and stw_be_p in tpm_cmd_set_XYZ functions
that are similar to existing getters.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_util.c | 6 +++---
hw/tpm/tpm_util.h | 15 +++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/hw/tpm/tpm_util.c b/h
On Thu, Jan 11, 2018 at 4:58 AM, Eduardo Habkost wrote:
> On Thu, Jan 11, 2018 at 11:25:08AM +0100, Igor Mammedov wrote:
>> On Wed, 10 Jan 2018 19:48:00 -0200
>> Eduardo Habkost wrote:
>>
>> > On Wed, Jan 10, 2018 at 01:30:29PM -0800, Alistair Francis wrote:
>> > > On Thu, Dec 28, 2017 at 6:59 AM
Hi Nesrine,
On 02/01/2018 11:30 PM, Nesrine Zouari wrote:
> Hello,
>
> I am a computer engineering student and I am actually working on my
> graduation project at Lauterbach company. The project is about Qemu Trace
> and as a future I would like to contribute this work to the main line.
>
> My p
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180201212917.18131-1-pbonz...@redhat.com
Subject: [Qemu-devel] [PATCH v4 0/5] coroutine-lock: polymorphic CoQueue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total
On 01.02.2018 18:28, Wei Huang wrote:
> This patch adds a small binary kernel to test aarch64 virt machine's
> UART.
>
> Signed-off-by: Wei Huang
> ---
> tests/Makefile.include | 1 +
> tests/boot-serial-test.c | 9 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/tests/Makefile
QemuLockable is a polymorphic lock type that takes an object and
knows which function to use for locking and unlocking. The
implementation could use C11 _Generic, but since the support is
not very widespread I am instead using __builtin_choose_expr and
__builtin_types_compatible_p, which are alrea
qemu_co_queue_next does not need to release and re-acquire the mutex,
because the queued coroutine does not run immediately. However, this
does not hold for qemu_co_enter_next. Now that qemu_co_queue_wait
can synchronize (via QemuLockable) with code that is not running in
coroutine context, it's
Now that CoQueues can use a QemuMutex for thread-safety, there is no
need for curl to roll its own coroutine queue. Coroutines can be
placed directly on the queue instead of using a list of CURLAIOCBs.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
---
block/curl.c | 20
There are cases in which a queued coroutine must be restarted from
non-coroutine context (with qemu_co_enter_next). In this cases,
qemu_co_enter_next also needs to be thread-safe, but it cannot use
a CoMutex and so cannot qemu_co_queue_wait. Use QemuLockable so
that the CoQueue can interchangeabl
There are cases in which a queued coroutine must be restarted from
non-coroutine context (with qemu_co_enter_next). In this cases,
qemu_co_enter_next also needs to be thread-safe, but it cannot use a
CoMutex and so cannot qemu_co_queue_wait. This happens in curl (which
right now is rolling its ow
In preparation for adding a similar test using QemuLockable, add a very
simple testcase that has two interleaved calls to lock and unlock.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
---
tests/test-coroutine.c | 50 --
1 file changed
On 2018-01-26 16:00, Alberto Garcia wrote:
> This test tries reopening a qcow2 image with valid and invalid
> options. This patch adds l2-cache-entry-size to the set.
>
> Signed-off-by: Alberto Garcia
> ---
> tests/qemu-iotests/137 | 5 +
> tests/qemu-iotests/137.out | 2 ++
> 2 files ch
On Thu, Feb 1, 2018 at 9:13 AM, Alistair Francis
wrote:
> On Thu, Feb 1, 2018 at 4:01 AM, Alex Bennée wrote:
>>
>> Alistair Francis writes:
>>
>>> On Wed, Jan 31, 2018 at 12:32 PM, Alex Bennée
>>> wrote:
Alistair Francis writes:
> On Tue, Jan 30, 2018 at 8:26 PM, Paolo Bonz
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Yuval Shaia
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f8deaf638c..23a4fd0b3d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1986,6 +1986,14 @@ F: block/replication.c
F: tests/test-re
Currently only file backed memory backend can
be created with a "share" flag in order to allow
sharing guest RAM with other processes in the host.
Add the "share" flag also to RAM Memory Backend
in order to allow remapping parts of the guest RAM
to different host virtual addresses. This is needed
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Yuval Shaia
Reviewed-by: Shamir Rabinovitch
---
docs/pvrdma.txt | 255
1 file changed, 255 insertions(+)
create mode 100644 docs/pvrdma.txt
diff --git a/docs/pvrdma.txt b/docs/pvrdma.txt
ne
V8 -> V9:
- Addressed Dotan's Barak (offline) comments:
- use g_malloc instead of malloc
- re-arrange structs for better padding
- some cosmetic changes
- do not try to fetch CQE when CQ is going down
- init state of QP changed to RESET
- modify poll_cq
- add fix to qkey handl
Queued on python-next, thanks!
On Mon, Jan 22, 2018 at 09:50:27PM +0100, Amador Pahim wrote:
> Changes v11->v12:
> - Rebase.
> - Drop the already queued commit (qemu.py: remove unused import)
> - Fix code filling the _monitor_address when it's None.
> - Drop the redundant commit checking wheth
KVM doesn't support emulating a GICv3 in userspace, only GICv2. We
currently attempt this anyway, and as a result a KVM guest doesn't
receive interrupts and the user is left wondering why. Report an error
to the user if this particular combination is requested.
Signed-off-by: Christoffer Dall
-
On Tue, Jan 16, 2018 at 01:42:14PM +, Daniel P. Berrange wrote:
> From: Miika S
>
> keycodemapdb updated to add the QKeyCodes muhenkan and katakanahiragana
>
> Signed-off-by: Miika S
Oops, this conflicts with:
commit ae6b06ab655b21c19b234ce3422f694d11a013e0
Author: Daniel P. Berrange
Dat
On Mon, Jan 22, 2018 at 09:50:28PM +0100, Amador Pahim wrote:
> To launch a VM, we need to create basically two files: the monitor
> socket (if it's a UNIX socket) and the qemu log file.
>
> For the qemu log file, we currently just open the path, which will
> create the file if it does not exist o
Detected by Coverity (CID 1385702). This fixes the recently added hypercall
to let guests properly apply Spectre and Meltdown workarounds.
Fixes: c59704b25473 "target/ppc/spapr: Add H-Call H_GET_CPU_CHARACTERISTICS"
Signed-off-by: Greg Kurz
---
hw/ppc/spapr_hcall.c |1 +
1 file changed, 1 in
On 2018-01-26 16:00, Alberto Garcia wrote:
> expand_zero_clusters_in_l1() is used when downgrading qcow2 images
> from v3 to v2 (compat=0.10). This is one of the functions that needed
> more changes to support L2 slices, so this patch extends iotest 061 to
> test downgrading a qcow2 image using a s
* Thomas Huth :
> First kudos for the new hppa-softmmu target!
Thanks Thomas!
> But these debug messages now pop up during "make check-qtest":
>
> Serial port created at 0xfff83800
> Firmware loaded at 0xf000-0xf0023f29, entry at 0xf084.
>
> That's a little bit annoying. Could you pleas
* Marcel Apfelbaum (mar...@redhat.com) wrote:
> On 01/02/2018 21:48, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> >> On Thu, Feb 01, 2018 at 02:24:15PM +0200, Marcel Apfelbaum wrote:
> >>> Hi Peter,
> >>>
> >>> On 01/02/2018 13:20, Peter Xu wrote:
> In the
* Brijesh Singh (brijesh.si...@amd.com) wrote:
>
>
> On 2/1/18 11:58 AM, Dr. David Alan Gilbert wrote:
> > * Brijesh Singh (brijesh.si...@amd.com) wrote:
> >> update 'info kvm' to display the memory encryption support.
> >>
> >> (qemu) info kvm
> >> kvm support: enabled
> >> memory encryption: di
On 2018-01-26 16:00, Alberto Garcia wrote:
> The l2-cache-entry-size setting can only contain values that are
> powers of two between 512 and the cluster size.
>
> Signed-off-by: Alberto Garcia
> ---
> tests/qemu-iotests/103 | 17 +
> tests/qemu-iotests/103.out | 3 +++
> 2
On 01/02/2018 21:48, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
>> On Thu, Feb 01, 2018 at 02:24:15PM +0200, Marcel Apfelbaum wrote:
>>> Hi Peter,
>>>
>>> On 01/02/2018 13:20, Peter Xu wrote:
In the past, we prioritized IOMMU migration so that we have such a
* Wei Huang (w...@redhat.com) wrote:
>
>
> On 01/25/2018 02:05 PM, Dr. David Alan Gilbert wrote:
> > * Wei Huang (w...@redhat.com) wrote:
> >> This patch adds the migration test support for aarch64. The test code,
> >> which implements the same functionality as x86, is compiled into a binary
> >>
On 2018-01-26 16:00, Alberto Garcia wrote:
> This function doesn't need any changes to support L2 slices, but since
> it's now dealing with slices intead of full tables, the l2_table
> variable is renamed for clarity.
>
> Signed-off-by: Alberto Garcia
> Reviewed-by: Eric Blake
> ---
> block/qco
* Michael S. Tsirkin (m...@redhat.com) wrote:
> On Thu, Feb 01, 2018 at 02:24:15PM +0200, Marcel Apfelbaum wrote:
> > Hi Peter,
> >
> > On 01/02/2018 13:20, Peter Xu wrote:
> > > In the past, we prioritized IOMMU migration so that we have such a
> > > priority order:
> > >
> > > IOMMU > PCI D
On 2/1/18 11:58 AM, Dr. David Alan Gilbert wrote:
> * Brijesh Singh (brijesh.si...@amd.com) wrote:
>> update 'info kvm' to display the memory encryption support.
>>
>> (qemu) info kvm
>> kvm support: enabled
>> memory encryption: disabled
> As Markus said, this should be split qmp/hmp; but someth
On 2018-01-26 15:59, Alberto Garcia wrote:
> The qcow2_truncate() code is mostly independent from whether
> we're using L2 slices or full L2 tables, but in full and
> falloc preallocation modes new L2 tables are allocated using
> qcow2_alloc_cluster_link_l2(). Therefore the code needs to be
> modi
On 2018-01-26 15:59, Alberto Garcia wrote:
> This function doesn't need any changes to support L2 slices, but since
> it's now dealing with slices instead of full tables, the l2_table
> variable is renamed for clarity.
>
> Signed-off-by: Alberto Garcia
> Reviewed-by: Eric Blake
> ---
> block/qc
* Peter Xu (pet...@redhat.com) wrote:
> In the past, we prioritized IOMMU migration so that we have such a
> priority order:
>
> IOMMU > PCI Devices
>
> When migrating a guest with both vIOMMU and pcie-root-port, we'll always
> migrate vIOMMU first, since pcie-root-port will be seen to have t
On 2018-01-26 16:00, Alberto Garcia wrote:
> This function doesn't need any changes to support L2 slices, but since
> it's now dealing with slices intead of full tables, the l2_table
> variable is renamed for clarity.
>
> Signed-off-by: Alberto Garcia
> Reviewed-by: Eric Blake
> ---
> block/qco
On 2018-01-26 16:00, Alberto Garcia wrote:
> This function doesn't need any changes to support L2 slices, but since
> it's now dealing with slices intead of full tables, the l2_table
> variable is renamed for clarity.
>
> Signed-off-by: Alberto Garcia
> Reviewed-by: Eric Blake
> ---
> block/qco
* Marcel Apfelbaum (mar...@redhat.com) wrote:
> Hi Peter,
>
> On 01/02/2018 13:20, Peter Xu wrote:
> > In the past, we prioritized IOMMU migration so that we have such a
> > priority order:
> >
> > IOMMU > PCI Devices
> >
> > When migrating a guest with both vIOMMU and pcie-root-port, we'll
Hi Michael,
On 01/02/2018 21:10, Michael S. Tsirkin wrote:
>> diff --git a/hw/rdma/vmw/vmw_pvrdma-abi.h b/hw/rdma/vmw/vmw_pvrdma-abi.h
>> new file mode 100644
>> index 00..8cfb9d7745
>> --- /dev/null
>> +++ b/hw/rdma/vmw/vmw_pvrdma-abi.h
>
> Why do you copy this here? Why not import it
>
On 2018-01-26 15:59, Alberto Garcia wrote:
> expand_zero_clusters_in_l1() expands zero clusters as a necessary step
> to downgrade qcow2 images to a version that doesn't support metadata
> zero clusters. This function takes an L1 table (which may or may not
> be active) and iterates over all its L2
On 2018-01-26 15:59, Alberto Garcia wrote:
> Adding support for L2 slices to expand_zero_clusters_in_l1() needs
> (among other things) an extra loop that iterates over all slices of
> each L2 table.
>
> Putting all changes in one patch would make it hard to read because
> all semantic changes woul
On 2018-01-26 15:59, Alberto Garcia wrote:
> qcow2_update_snapshot_refcount() increases the refcount of all
> clusters of a given snapshot. In order to do that it needs to load all
> its L2 tables and iterate over their entries. Since we'll be loading
> L2 slices instead of full tables we need to a
On 01/02/2018 14:21, Eduardo Habkost wrote:
>> The device looks at its own private page tables, and not
>> to the OS ones.
> I'm still confused by your statement that the device builds its
> own [IOVA->PA] page table. How would the device do that if it
> doesn't have access to the CPU MMU state?
On 2018-01-26 15:59, Alberto Garcia wrote:
> At the moment it doesn't really make a difference whether we call
> qcow2_get_refcount() before of after reading the L2 table, but if we
> want to support L2 slices we'll need to read the refcount first.
>
> This patch simply changes the order of those
On 01/02/2018 21:21, Eduardo Habkost wrote:
> On Thu, Feb 01, 2018 at 08:58:32PM +0200, Marcel Apfelbaum wrote:
>> On 01/02/2018 20:51, Eduardo Habkost wrote:
>>> On Thu, Feb 01, 2018 at 08:31:09PM +0200, Marcel Apfelbaum wrote:
On 01/02/2018 20:21, Eduardo Habkost wrote:
> On Thu, Feb 01,
On Thu, Feb 01, 2018 at 08:58:32PM +0200, Marcel Apfelbaum wrote:
> On 01/02/2018 20:51, Eduardo Habkost wrote:
> > On Thu, Feb 01, 2018 at 08:31:09PM +0200, Marcel Apfelbaum wrote:
> >> On 01/02/2018 20:21, Eduardo Habkost wrote:
> >>> On Thu, Feb 01, 2018 at 08:03:53PM +0200, Marcel Apfelbaum wro
On 2018-01-26 15:59, Alberto Garcia wrote:
> Adding support for L2 slices to qcow2_update_snapshot_refcount() needs
> (among other things) an extra loop that iterates over all slices of
> each L2 table.
>
> Putting all changes in one patch would make it hard to read because
> all semantic changes
On Thu, Feb 01, 2018 at 02:24:15PM +0200, Marcel Apfelbaum wrote:
> Hi Peter,
>
> On 01/02/2018 13:20, Peter Xu wrote:
> > In the past, we prioritized IOMMU migration so that we have such a
> > priority order:
> >
> > IOMMU > PCI Devices
> >
> > When migrating a guest with both vIOMMU and pc
On 02/01/2018 11:59 AM, Max Reitz wrote:
>>> H, now this fails again on my 32 bit build. :-(
>>>
>>> The issue there is that you get a "Cannot allocate memory" when trying
>>> to open the file. My current fix was 2291712c39111a732 which simply
>>> converted that to "Invalid argument", but now
> diff --git a/hw/rdma/vmw/vmw_pvrdma-abi.h b/hw/rdma/vmw/vmw_pvrdma-abi.h
> new file mode 100644
> index 00..8cfb9d7745
> --- /dev/null
> +++ b/hw/rdma/vmw/vmw_pvrdma-abi.h
Why do you copy this here? Why not import it
from include/uapi/rdma/vmw_pvrdma-abi.h in Linux into
standard headers?
On 2018-01-26 15:59, Alberto Garcia wrote:
> zero_single_l2() limits the number of clusters to be zeroed to the
> amount that fits inside an L2 table. Since we'll be loading L2 slices
> instead of full tables we need to update that limit.
Same as last patch, maybe we should rename the function now
On 2018-01-26 15:59, Alberto Garcia wrote:
> discard_single_l2() limits the number of clusters to be discarded to
> the amount that fits inside an L2 table. Since we'll be loading L2
> slices instead of full tables we need to update that limit.
H, maybe rename the function to discard_l2_slice(
t tags/for-release-20180201
for you to fetch changes up to 20b233641d76cc1812064304798ffeb530dc112d:
ipmi: Allow BMC device properties to be set (2018-01-30 15:52:53 -0600)
Lots of litte miscellaneous fixes for the IPMI code, plus
add
There were several issues with vmstate transfers in the IPMI devices.
This new version is heavily tested and should be much better. It will
not be possible to migrate BT devices from older systems, it was too
broken to handle that.
Just to make sure I got this right, could somebody knowledgeable
From: Corey Minyard
The vmstate for isa_ipmi_kcs was referencing into the kcs structure,
instead create a kcs structure separate and use that.
There was also some issues in the state transfer. The inlen field
was not being transferred, so if a transaction was in process during
the transfer it w
On 01/02/2018 20:51, Eduardo Habkost wrote:
> On Thu, Feb 01, 2018 at 08:31:09PM +0200, Marcel Apfelbaum wrote:
>> On 01/02/2018 20:21, Eduardo Habkost wrote:
>>> On Thu, Feb 01, 2018 at 08:03:53PM +0200, Marcel Apfelbaum wrote:
On 01/02/2018 15:53, Eduardo Habkost wrote:
> On Thu, Feb 01,
From: Corey Minyard
Macro parameters should almost always have () around them when used.
llvm reported an error on this.
Remove redundant parenthesis and put parenthesis around the entire
macros with assignments in case they are used in an expression.
The macros were doing ((v) & 1) for a binar
From: Corey Minyard
The vmstate for isa_ipmi_bt was referencing into the bt structure,
instead create a bt structure separate and use that.
The version 1 of the BT transfer was fairly broken, if a migration
occured during an IPMI operation, it is likely the migration would
be corrupted because I
On 2018-01-26 15:59, Alberto Garcia wrote:
> handle_alloc() loads an L2 table and limits the number of checked
> clusters to the amount that fits inside that table. Since we'll be
> loading L2 slices instead of full tables we need to update that limit.
>
> Apart from that, this function doesn't ne
On 2018-01-26 15:59, Alberto Garcia wrote:
> handle_copied() loads an L2 table and limits the number of checked
> clusters to the amount that fits inside that table. Since we'll be
> loading L2 slices instead of full tables we need to update that limit.
>
> Apart from that, this function doesn't n
From: Corey Minyard
Signed-off-by: Corey Minyard
Acked-by: Marc-André Lureau
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fe39b30..192d8b8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -940,6 +940,15 @@ F: tests/ahci-test.c
F: te
From: Corey Minyard
This lets an event be added to the SEL as if a sensor had generated
it. The OpenIPMI driver uses it for storing panic event information.
Signed-off-by: Corey Minyard
Reviewed-by: Cédric Le Goater
---
hw/ipmi/ipmi_bmc_sim.c | 24
1 file changed, 24
From: Corey Minyard
Signed-off-by: Corey Minyard
Reviewed-by: Marc-André Lureau
---
hw/ipmi/ipmi_bmc_sim.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
index e84d710..9b509f8 100644
--- a/hw/ipmi/ipmi
From: Corey Minyard
The minimum message size was on the wrong commands, for getting
the time it's zero and for setting the time it's 6.
Signed-off-by: Corey Minyard
Reviewed-by: Cédric Le Goater
Reviewed-by: Marc-André Lureau
---
hw/ipmi/ipmi_bmc_sim.c | 4 ++--
1 file changed, 2 insertions(
From: Corey Minyard
Otherwise there's no way to clear them without an external command,
and it could lock the OS in the VM if they were stuck.
Signed-off-by: Corey Minyard
---
hw/ipmi/ipmi_bmc_extern.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi
From: Corey Minyard
According to the spec, from section "32.3 OEM SEL Record - Type
E0h-FFh", event types from 0x0e to 0xff do not have a timestamp.
So don't set it when adding those types. This required putting
the timestamp in a temporary buffer, since it's still required
to set the last addit
On Thu, Feb 01, 2018 at 08:31:09PM +0200, Marcel Apfelbaum wrote:
> Theoretically is possible to send any contiguous IOVA instead of
> process's one but is not how is working today.
It works this way today in hardware but it's not hardware that limits
it to work this way - it's a software limitati
On Thu, Feb 01, 2018 at 08:31:09PM +0200, Marcel Apfelbaum wrote:
> On 01/02/2018 20:21, Eduardo Habkost wrote:
> > On Thu, Feb 01, 2018 at 08:03:53PM +0200, Marcel Apfelbaum wrote:
> >> On 01/02/2018 15:53, Eduardo Habkost wrote:
> >>> On Thu, Feb 01, 2018 at 02:29:25PM +0200, Marcel Apfelbaum wro
On 2018-01-26 15:59, Alberto Garcia wrote:
> There's a loop in this function that iterates over the L2 entries in a
> table, so now we need to assert that it remains within the limits of
> an L2 slice.
>
> Apart from that, this function doesn't need any additional changes, so
> this patch simply u
On 01/02/2018 20:18, Eduardo Habkost wrote:
> On Thu, Feb 01, 2018 at 07:58:10PM +0200, Marcel Apfelbaum wrote:
>> On 01/02/2018 19:36, Eduardo Habkost wrote:
>>> On Thu, Feb 01, 2018 at 07:12:45PM +0200, Michael S. Tsirkin wrote:
On Thu, Feb 01, 2018 at 03:01:36PM -0200, Eduardo Habkost wrote
On 01/02/2018 20:21, Eduardo Habkost wrote:
> On Thu, Feb 01, 2018 at 08:03:53PM +0200, Marcel Apfelbaum wrote:
>> On 01/02/2018 15:53, Eduardo Habkost wrote:
>>> On Thu, Feb 01, 2018 at 02:29:25PM +0200, Marcel Apfelbaum wrote:
On 01/02/2018 14:10, Eduardo Habkost wrote:
> On Thu, Feb 01,
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