❦ 12 janvier 2018 16:47 -0200, Eduardo Habkost :
> Adding Westmere-PCID would require adding a Westmere-PCID-IBRS
> CPU model too, so this is starting to look a bit ridiculous.
> Sane VM management systems would know how to use
> "-cpu Westmere,+pcid" without requiring new CPU model entries in
>
Hello Dan,
> Not a flag, but a new "Address Range Type GUID". See section "5.2.25.2
> System Physical Address (SPA) Range Structure" in the ACPI 6.2A
> specification. Since it is a GUID we could define a Linux specific
> type for this case, but spec changes would allow non-Linux hypervisors
> to
Hi Peter,
>> +static int kvm_arm_cpreg_value(ARMCPU *cpu, ptrdiff_t fieldoffset)
>> +{
>> +int i;
>> +
>> +for (i = 0; i < cpu->cpreg_array_len; i++) {
>
> This is still absolutely the wrong thing to do. Nothing should
> need to scan this array like this.
For the KVM mode, I use this fun
Add a 'dma' property allowing machine creation to provide the address-space
SDHCI DMA operates on.
[based on a patch from Alistair Francis
from qemu/xilinx tag xilinx-v2016.1]
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 1 +
hw/sd/sdhci.c | 17 -
From: Andrey Smirnov
Signed-off-by: Andrey Smirnov
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/sd/sdhci.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 983569ba8b..226a22c5fb 100644
--- a/hw/
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/sd/sdhci-internal.h | 2 +-
hw/sd/sdhci.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index e941bc2386..fc807f08f3 100644
--- a/hw/sd/sdh
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/sd/sdhci-internal.h | 1 +
hw/sd/sdhci.c | 3 +--
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 248fd027f9..e941bc2386 100644
--- a/hw/sd/sdh
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/sd/sdhci.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index ded4fa4885..d0a91b60d5 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -947,7 +947,8 @@ static ui
running qtests:
$ make check-qtest-arm
GTESTER check-qtest-arm
SDHC rd_4b @0x44 not implemented
SDHC wr_4b @0x40 <- 0x89abcdef not implemented
SDHC wr_4b @0x44 <- 0x01234567 not implemented
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
include/hw/sd/sdhci.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/sd/sdhci.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index b464143959..ded4fa4885 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -32,6 +32,7 @@
#include
While SysBus devices can use the get_system_memory() address space,
PCI devices should use the bus master address space for DMA.
Suggested-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
---
Should we check for the PCI_COMMAND_MASTER bit before
using pci_get_address_space()?
include/hw
zero-initialize ADMADescr 'dscr' in sdhci_do_adma() to avoid:
hw/sd/sdhci.c: In function ‘sdhci_do_adma’:
hw/sd/sdhci.c:714:29: error: ‘dscr.addr’ may be used uninitialized in this
function [-Werror=maybe-uninitialized]
trace_sdhci_adma("link", s->admasysaddr);
Now both inherited classes appear as DEVICE_CATEGORY_STORAGE.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/sd/sdhci.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 6c3389cfdc..191f0d26ee
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/sd/sdhci.c | 30 +-
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 191f0d26ee..b464143959 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -
Add common/sysbus/pci/sdbus comments to have clearer code blocks separation.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 4 +++-
hw/sd/sdhci.c | 46 --
2 files changed, 31 insertions(+), 19 deletions(-)
diff --git a/incl
Since v6:
- addressed Peter reviews
- do not use an unique Property[] for both sysbus/pci
Peter didn't recommend me to use the qdev_property_add_static() API since
it is only used by the ARM cpus and may be due for removal, however I found
it cleaner.
At the end of those series, t
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/sd/sdhci-internal.h | 4
include/hw/sd/sdhci.h | 7 ++-
hw/sd/sdhci.c | 1 +
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 161177cf
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
include/hw/sd/sdhci.h | 2 --
hw/sd/sdhci.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 1335373d3c..dacd726537 100644
--- a/include/hw/sd/sdhci.h
+++ b/in
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1449687
Title:
block migra
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/530077
Title:
kvm: 16-bit
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1727737
Title:
qemu-arm st
> On Jan 10, 2018, at 11:14 AM, Daniel P. Berrange wrote:
>
> On Tue, Dec 26, 2017 at 08:14:28PM -0500, John Arbuckle wrote:
>> Currently the ungrab keys for the Cocoa and GTK interface are Control-Alt-g.
>> This combination may not be very fun for the user to have to enter, so we
>> now enable
> -Original Message-
> From: Qemu-devel
> [mailto:qemu-devel-bounces+arei.gonglei=huawei@nongnu.org] On
> Behalf Of Eduardo Habkost
> Sent: Tuesday, January 09, 2018 11:45 PM
> To: qemu-devel@nongnu.org
> Cc: Paolo Bonzini
> Subject: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID b
Sorry for the top post, I’m on my phone.
Changing them should be fine (as you said it doesn't actually change anything)
I think it is just worth mentioning in the commit.
Thanks,
Alistair
From: Philippe Mathieu-Daudé
Sent: Friday, 12 January 2018 5:57 PM
To: Alistair Francis
Cc: Edgar E . Igles
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180113004338.16867-1-laur...@vivier.eu
Subject: [Qemu-devel] [PATCH v2 0/7] target/m68k: supervisor mode (part 2)
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total
Hi Alistair,
On 01/12/2018 09:00 PM, Alistair Francis wrote:
> On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé
> wrote:
>> (Note than Spec v2 is supported by default)
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/sd/sdhci-internal.h | 24 +++-
>> include/hw/s
On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/sd/sdhci-internal.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
> ind
Hi Peter,
I looked at the coverity output and below are my comments. Please do
correct me if I misunderstood something!
CID 1383841 (#1 of 4): Uninitialized scalar variable (UNINIT)26.
uninit_use_in_call: Using uninitialized element of array tx_rx when calling
stripe8.
'num_effective_busses
On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Alistair
> ---
> hw/arm/exynos4210.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4
On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-zynqmp.c | 38 +++---
> 1 file changed, 27 insertions(+), 11 deletions(-)
>
> diff --git a/hw/arm
Dump MMU state and address mappings.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
CC: Dr. David Alan Gilbert
hmp-commands-info.hx | 2 +-
target/m68k/cpu.h | 1 +
target/m68k/helper.c | 216 ++
target/m68k/monitor.c
The instruction "moves" can select source and destination
address space (user or kernel). This patch modifies
all the load/store functions to be able to provide
the address space the caller wants to use instead
of using the current one. All the callers are modified
to provide the default address sp
The MC68040 MMU provides the size of the access that
triggers the page fault.
This size is set in the Special Status Word which
is written in the stack frame of the access fault
exception.
So we need the size in m68k_cpu_unassigned_access() and
m68k_cpu_handle_mmu_fault().
To be able to do that,
Add ittr0, ittr1, dttr0, dttr1 and manage Transparent Translations
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/cpu.h | 18 +++
target/m68k/helper.c| 79 +
target/m68k/monitor.c | 4 +++
target/
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
v2: change ACCESS_PTEST value because of new ACCESS_DEBUG
use -page_size to mask address instead of TARGET_PAGE_MASK
target/m68k/cpu.h | 3 +++
target/m68k/helper.c| 72 ++
Only add MC68040 MMU page table processing and related
registers (Special Status Word, Translation Control Register,
User Root Pointer and Supervisor Root Pointer).
Transparent Translation Registers, DFC/SFC and pflush/ptest
will be added later.
Signed-off-by: Laurent Vivier
---
v2: move mmu_fau
and introduce SFC and DFC control registers.
Signed-off-by: Laurent Vivier
---
v2: copy bit 2 of SFC and DFC to tb->flags to
inline memory access in moves decoder.
target/m68k/cpu.h | 10 --
target/m68k/helper.c| 10 ++
target/m68k/monitor.c | 2 ++
target/m68k/op_helpe
This series introduces the MC68040 MMU.
But first of all, we need to modify the prototype
of tlb_fill() and handle_mmu_fault handler to pass
the size of the access. MC68040 stores this value
in the exception stack frame.
Following patches add:
- MMU page table and fault handlers,
- Transparent Tr
On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé
wrote:
> new properties are introduced, with default value to Spec v2:
> - adma1 (disabled, deprecated in v2)
> - adma2 (enabled)
> - 64bit (disabled)
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/sd/sdhci-internal.h | 14 +++---
Am 28.09.2017 um 19:01 hat Dr. David Alan Gilbert geschrieben:
> Hi,
> This is a 'fun' bug; I had a good chat to kwolf about it earlier.
> A proper fix really needs to be done together with libvirt so that we
> can sequence:
>a) The stopping of the CPU on the source
>b) The termination o
This did never occur again for me. So this can get closed.
** Changed in: qemu (Ubuntu)
Status: Triaged => Invalid
** Changed in: qemu
Status: Incomplete => Invalid
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https
On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/sd/core.c | 14 --
> hw/sd/trace-events | 5 +
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a
On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé
wrote:
> (Note than Spec v2 is supported by default)
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/sd/sdhci-internal.h | 24 +++-
> include/hw/sd/sdhci.h | 6 +
> hw/sd/sdhci.c | 61
>
On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/sd/sdhci.h | 2 ++
> hw/sd/sdhci.c | 53
> ---
> 2 files changed, 35 insertions(+), 20 deletions(-)
>
> diff --git
On 12/22/2017 08:00 AM, Kevin Wolf wrote:
> Am 21.12.2017 um 23:44 hat John Snow geschrieben:
>> I don't think there's a legitimate reason to open directories as if
>> they were files. This prevents QEMU from opening and attempting to probe
>> a directory inode, which can break in exciting ways.
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1515788548-3570-1-git-send-email-jute...@microsoft.com
Subject: [Qemu-devel] [PATCH 0/4] Implements the Windows Hypervisor Platform
accelerator
=== TEST SCRIPT BEGIN ===
#!/
Initial commit of the ZynqMP RTC device.
Signed-off-by: Alistair Francis
---
V2:
- Delete unused realise function
- Remove DB_PRINT()
hw/timer/Makefile.objs | 1 +
hw/timer/xlnx-zynqmp-rtc.c | 218 +
include/hw/timer/xlnx-zynqmp-rtc.h
Allow the guest to determine the time set from the QEMU command line.
This includes adding a trace event to debug the new time.
Signed-off-by: Alistair Francis
---
- Convert DB_PRINT() macro to trace
hw/timer/trace-events | 3 +++
hw/timer/xlnx-zynqmp-rtc.c | 23
V2:
- Delete unused realise function
- Add cover letter
- Convert DB_PRINT() macro to trace
Alistair Francis (3):
xlnx-zynqmp-rtc: Initial commit
xlnx-zynqmp-rtc: Add basic time support
xlnx-zynqmp: Connect the RTC device
hw/arm/xlnx-zynqmp.c | 14 +++
hw/timer/Makefile.o
On Fri, Jan 12, 2018 at 12:37 PM, Alistair Francis wrote:
> On Thu, Oct 5, 2017 at 7:36 AM, Richard Henderson
> wrote:
>> From: Richard Henderson
>>
>> We had a check using TARGET_VIRT_ADDR_SPACE_BITS to make sure
>> that the allocation coming in from the command-line option was
>> not too large
Am 12.01.2018 um 22:57 schrieb Stefan Weil:
>> Over the next few days the pre-release version of the documentation for this
>> new
>> API will be visible at https://docs.microsoft.com/en-us/virtualization under
>> the 'Windows Hypervisor Platform' section. Here you will see the
>> requirements,
>
Am 12.01.2018 um 21:22 schrieb Justin Terry (VM) via Qemu-devel:
> Hello QEMU Community!
>
> Over the past few months the Hyper-V team at Microsoft has been working hard
> on
> a new user-mode API for our hypervisor that will be released as part of the
> upcoming SDK. This new API adds user-mode
On 12/19/2017 02:45 AM, Peter Xu wrote:
> Monitor code now can be run in more than one thread. Let it be thread
> safe when accessing suspend_cnt counter.
>
> Signed-off-by: Peter Xu
> ---
> monitor.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/monito
On 2018-01-12 13:06, Richard Henderson wrote:
> This includes a fix for the tcg/arm bug exposed by the ppc64 code change
> for comparisons.
>
> It also includes improvements to tcg/arm and tcg/ppc to allow for larger
> CPUFooState structures, as exposed by expanding CPUARMState for 2048-bit
> vect
Implements the WHPX accelerator cpu enlightenments to actually use the whpx-all
accelerator on Windows platforms.
Signed-off-by: Justin Terry (VM)
---
cpus.c| 66 ++-
include/sysemu/hw_accel.h | 13 ++
target/i386/helper.c
Adds support for the Windows Hypervisor Platform accelerator (WHPX) stubs and
introduces the whpx.h sysemu API for managing the vcpu scheduling and
management.
Signed-off-by: Justin Terry (VM)
---
accel/stubs/Makefile.objs | 9 +
accel/stubs/whpx-stub.c | 48 ++
Implements the Windows Hypervisor Platform accelerator (WHPX) target. Which
acts as a hypervisor accelerator for QEMU on the Windows platform. This enables
QEMU much greater speed over the emulated x86_64 path's that are taken on
Windows today.
1. Adds support for vPartition management.
2. Adds su
Hello QEMU Community!
Over the past few months the Hyper-V team at Microsoft has been working hard on
a new user-mode API for our hypervisor that will be released as part of the
upcoming SDK. This new API adds user-mode capabilities to create and manage
partitions at the hypervisor level, configur
Introduces the configure support for the new Windows Hypervisor Platform that
allows for hypervisor acceleration from usermode components on the Windows
platform.
Signed-off-by: Justin Terry (VM)
---
configure | 48 +++-
qemu-options.hx | 8
AArch64 with SVE has an offset of 80k to the 8th TLB.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 879885b68b..74f9b4aa34 100644
--- a/
We recently relaxed the limit of the number of opcodes that can
appear in a TranslationBlock. In certain cases this has resulted
in relocation overflow.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 67
1 file changed, 39 insert
problem. However, the mips isa
makes it more difficult to fix up. I'd like someone with hardware to
make this change.
r~
The following changes since commit 7398166ddf7c6dbbc9cae6ac69bb2feda14b40ac:
Merge remote-tracking branch 'remotes/kraxel/tags/vnc-20180112-pull-request'
AArch64 with SVE has an offset of 80k to the 8th TLB.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index b9890c8bd8..4bd465732
From: Richard Henderson
The code sequence we were generating was only good for unsigned
comparisons. For signed comparisions, use the sequence from gcc.
Fixes booting of ppc64 firmware, with a patch changing the code
sequence for ppc comparisons.
Tested-by: Michael Roth
Signed-off-by: Richard
On 12/19/2017 02:45 AM, Peter Xu wrote:
> After this patch, we will allow QMP clients to enable QMP capabilities
> when sending the first "qmp_capabilities" command. Originally we are
> starting QMP session with no arguments like:
>
> { "execute": "qmp_capabilities" }
>
> Now we can enable som
> Hello QEMU Community!
>
> Over the past few months the Hyper-V team at Microsoft has been working hard
> on
> a new user-mode API for our hypervisor that will be released as part of the
> upcoming SDK. This new API adds user-mode capabilities to create and manage
> partitions at the hypervisor
On Thu, Oct 5, 2017 at 7:36 AM, Richard Henderson
wrote:
> From: Richard Henderson
>
> We had a check using TARGET_VIRT_ADDR_SPACE_BITS to make sure
> that the allocation coming in from the command-line option was
> not too large, but that didn't include target-specific knowledge
> about other re
On 01/12/2018 11:07 AM, Marc-André Lureau wrote:
Hi
On Wed, Jan 10, 2018 at 7:49 PM, Stefan Berger
wrote:
On 01/10/2018 01:35 PM, Stefan Berger wrote:
The TPM Physical Presence interface consists of an ACPI part, a shared
memory part, and code in the firmware. Users can send messages to the
f
On Thu, Jan 11, 2018 at 10:29 AM, Philippe Mathieu-Daudé
wrote:
> On Tue, Jan 9, 2018 at 3:50 PM, Alistair Francis
> wrote:
>> Initial commit of the ZynqMP RTC device.
>>
>> Signed-off-by: Alistair Francis
>> ---
>>
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/xlnx-zynqmp-rtc.c
On Thu, Jan 11, 2018 at 10:36 AM, Philippe Mathieu-Daudé
wrote:
> On 01/09/2018 03:50 PM, Alistair Francis wrote:
>> Signed-off-by: Alistair Francis
>> ---
>>
>> hw/arm/xlnx-zynqmp.c | 14 ++
>> include/hw/arm/xlnx-zynqmp.h | 2 ++
>> 2 files changed, 16 insertions(+)
>>
>>
I'm queueing patches 1-5 on x86-next.
On Tue, Jan 09, 2018 at 01:45:12PM -0200, Eduardo Habkost wrote:
> This series adds support for the new IA32_SPEC_CTRL MSR on Intel
> CPU models. The new MSR and the spec-ctrl CPUID bit
> (CPUID[EAX=7,ECX=0].EDX[bit 26]) were introduced by a recent
> Intel mi
On Fri, 12 Jan 2018 00:09:16 PST (-0800), h...@lst.de wrote:
On Fri, Jan 12, 2018 at 07:24:54AM +1300, Michael Clark wrote:
I'm going to be restoring branches for bbl and riscv-linux that work again
priv 1.9.1. There are still other emulators and RTL that support priv1.9.1.
Folk will have silico
On Mon, Jan 08, 2018 at 11:50:07PM +0200, Marcel Apfelbaum wrote:
> When all the fw_cfg slots are used, a write is made outside the
> bounds of the fw_cfg files array as part of the sort algorithm.
>
> Fix it by avoiding an unnecessary array element move.
> Fix also an assert while at it.
>
> Sig
On 01/12/2018 10:17 AM, Marc-André Lureau wrote:
2018-01-10 19:35 GMT+01:00 Stefan Berger :
LLessEqualOp = LNotOp LGreaterOp
Signed-off-by: Stefan Berger
Reviewed-by: Marc-André Lureau
Thanks. I added a comment line above the function now:
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: D
On 01/12/2018 09:22 AM, Peter Maydell wrote:
>> Richard Henderson (2):
>> target/arm: Split out vfp_expand_imm
>> target/arm: Add fp16 support to vfp_expand_imm
>>
>> target/arm/translate-a64.c | 49
>> +++---
>> 1 file changed, 33 insertions(+), 16 del
On 01/12/2018 08:12 AM, Bastian Koppelmann wrote:
> On 01/11/2018 08:12 PM, Richard Henderson wrote:
>> On 01/11/2018 10:20 AM, Peter Maydell wrote:
>>> On 18 December 2017 at 17:45, Richard Henderson
>>> wrote:
>>
>> I didn't want to attempt to generalize this until we have two users.
>> Particul
* Juan Quintela (quint...@redhat.com) wrote:
> It already has RAMBlock and offset, it can calculate it itself.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/ram.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/mig
> On 01/12/2018 02:20 PM, Philippe Mathieu-Daudé wrote:
>> On Fri, Jan 12, 2018 at 2:05 PM, Peter Maydell
>> wrote:
>>> On 11 January 2018 at 19:30, Philippe Mathieu-Daudé wrote:
Now both sysbus/pci classes inherit of the 'pending-insert-quirk' property,
which is a HCI dependent proper
On 01/12/2018 10:38 AM, Peter Maydell wrote:
>> -long ofs = offsetof(CPUARMState, vfp.regs[reg >> 1]);
>> +long r = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) &
>> 1]);
>> if (reg & 1) {
>> -ofs += offsetof(CPU_DoubleU, l.upper);
>> +ret
On 18 December 2017 at 17:30, Richard Henderson
wrote:
> This has a stub(-ish) implementation of ZCR, in that it does not
> implement _EL[123], or wire up the system register properly.
> However, it is enough for CONFIG_USER_ONLY.
>
> We will need VQ in tb->flags in order to pass the true vector
>
* Juan Quintela (quint...@redhat.com) wrote:
> So far, we had to free the error after each caller, so just do it
> here. Once there, tls.c was leaking the error.
>
> Signed-off-by: Juan Quintela
This clashes a bit with my
'Route errors down through migration_channel_connect'
'Allow migrate_fd_c
On 01/12/2018 10:44 AM, Peter Maydell wrote:
>> if (arm_feature(env, ARM_FEATURE_NEON)) {
>> nregs += 16;
>> if (reg < nregs) {
>> -env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
>> -env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
>> +
[CCing Jiri, Kashyap]
On Tue, Jan 09, 2018 at 08:01:12AM +0100, Vincent Bernat wrote:
> PCID has been introduced in Westmere and, since Linux 3.6
> (ad756a1603c5), KVM exposes PCID flag if host has it. Update CPU model
> for Westmere, Sandy Bridge and Ivy Bridge accordingly.
>
> Ensure compat 2.1
Le 10/01/2018 à 21:12, Richard Henderson a écrit :
> On 01/08/2018 03:10 PM, Laurent Vivier wrote:
>> +static int get_physical_address(CPUM68KState *env, hwaddr *physical,
>> +int *prot, target_ulong address,
>> +int access_type, targe
On 18 December 2017 at 17:30, Richard Henderson
wrote:
> Helpers that return a pointer into env->vfp.regs so that we isolate
> the logic of how to index the regs array for different cpu modes.
>
> Signed-off-by: Richard Henderson
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -64,1
Hi Peter,
On 01/12/2018 02:20 PM, Philippe Mathieu-Daudé wrote:
> On Fri, Jan 12, 2018 at 2:05 PM, Peter Maydell
> wrote:
>> On 11 January 2018 at 19:30, Philippe Mathieu-Daudé wrote:
>>> Now both sysbus/pci classes inherit of the 'pending-insert-quirk' property,
>>> which is a HCI dependent pr
On 01/12/2018 10:24 AM, Peter Maydell wrote:
>> +/**
>> + * aa32_vfp_dreg:
>> + * Return a pointer to the Dn register within env in 32-bit mode.
>> + */
>> +static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
>> +{
>> +return &env->vfp.regs[regno];
>> +}
>> +
>> +/**
>> + *
On 01/12/2018 05:31 AM, Paolo Bonzini wrote:
> From: Alex Bennée
>
> This script allows analysis of mutex acquisition and hold times based
> on a trace file. Given a trace control file of:
>
> qemu_mutex_lock
> qemu_mutex_locked
> qemu_mutex_unlock
>
> And running with:
>
> $QEMU $QEMU
On 18 December 2017 at 17:30, Richard Henderson
wrote:
> Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg.
> The previous patches have made the change in representation
> relatively painless.
>
> Add vfp.pregs as an ARMPredicateReg. Let FFR be P16 to make
> it easier to treat it as f
> I think this is the issue:
>
> I/O threadvCPU thread
> ---
>executes 1,000,000,000-th instruction
>wakes up I/O thread
> find
On 01/12/2018 08:22 AM, Peter Maydell wrote:
>> +/* Nicked from gmp longlong.h __udiv_qrnnd */
> Can we have a copyright/license attribution for code we nick
> from other projects, please? :-)
>
LGPL 2.1 in this case. ;-)
r~
On 01/12/2018 07:57 AM, Peter Maydell wrote:
> I see we're passing and returning decomposed_parts structs everywhere
> rather than pointers to them. How well does that compile? (I guess
> everything ends up inlining...)
For the x86_64 abi at least, the structure (as defined with bitfields) is 128
Hi everyone.
Ping! Please review.
Patchwork links:
1/4 multiboot: bss_end_addr can be zero
http://patchwork.ozlabs.org/patch/852049/
2/4 multiboot: Remove unused variables from multiboot.c
http://patchwork.ozlabs.org/patch/852045/
3/4 multiboot: Use header names when displaying fields
http:/
On 18 December 2017 at 17:30, Richard Henderson
wrote:
> Helpers that return a pointer into env->vfp.regs so that we isolate
> the logic of how to index the regs array for different cpu modes.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 20 +++-
> li
On 01/12/2018 09:55 AM, Marc-André Lureau wrote:
Hi
On Wed, Jan 10, 2018 at 7:35 PM, Stefan Berger
wrote:
Implement a virtual memory device for the TPM physical
presence interface. The memory is located at 0x
and used by ACPI to send messages to the firmware (BIOS).
This device should
On 12/01/2018 19:03, Steven Seeger wrote:
>> That's probably because the CPU runs in the background while the timers
>> run. So QEMU_CLOCK_VIRTUAL is _not_ latched while the timers run.
>> Would that explain it?
>
> Yes that would explain it. QEMU_CLOCK_VIRTUAL should increase with number of
> e
On 01/11/2018 04:04 AM, Dong Jia Shi wrote:
> What are still missing, thus need to be offered in the next version are:
> - I/O termination and FSM state handling if currently we have I/O on the
> status
> switched path.
> - Vary on/off event is not sensible to a guest.
I don't see a doc updat
On Friday, January 12, 2018 12:19:22 PM EST Paolo Bonzini wrote:
>
> Correct. I mentioned it because you also had "-icount sleep=off" in
> your previous message.
Yes I have tried both. With sleep=off, I get the faster interrupt response
(better granularity) but with sleep=on, it is poor. Again,
Triaging old bug tickets... can you still reproduce this issue with the
latest version of QEMU? Or could we close this ticket nowadays?
** Changed in: qemu
Status: New => Incomplete
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On Fri, Jan 12, 2018 at 9:36 AM, Max Filippov wrote:
> This fixes build on Centos 6.
>
> Fixes: 168c12b02470 ("target/xtensa: extract core opcode translators").
> Signed-off-by: Max Filippov
...and thank you Peter for fixing it.
--
Thanks.
-- Max
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