05.10.2017 16:37, Eric Blake wrote:
On 10/05/2017 06:30 AM, Vladimir Sementsov-Ogievskiy wrote:
21.09.2017 15:18, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
I'm about this:
"A server SHOULD try to minimize the number of chunks sent in a reply,
but MUST NOT mark a chunk as final if there is s
On 10/05/2017 06:24 PM, Igor Mammedov wrote:
> deduce core type directly from chip type instead of
> maintaining type mapping in PnvChipClass::cpu_model.
nice one again.
> Signed-off-by: Igor Mammedov
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> include/hw/ppc/pnv.h | 1 -
> in
On 10/05/2017 06:24 PM, Igor Mammedov wrote:
> Use a new DEFINE_TYPES() helper to simplify type registration
>
> Signed-off-by: Igor Mammedov
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> hw/ppc/pnv.c | 92
> ++--
> 1 file changed,
On 10/05/2017 06:24 PM, Igor Mammedov wrote:
> deduce cpu type directly from core type instead of
> maintaining type mapping in PnvCoreClass::cpu_oc and doing
> extra cpu_model parsing in pnv_core_class_init()
>
> Signed-off-by: Igor Mammedov
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
>
On 10/05/2017 06:24 PM, Igor Mammedov wrote:
> pnv core type definition doesn't have any fields that
> require it to be defined at runtime. So replace code
> that fills in TypeInfo at runtime with static TypeInfo
> array that does the same at complie time.
This is much better.
> Signed-off-by: Ig
On 10/05/2017 06:24 PM, Igor Mammedov wrote:
> typically for cpus/core type names following convention is used
>
>new_type_prefix-superclass_typename
>
> make PNV core/chip to follow common convention.
>
> Signed-off-by: Igor Mammedov
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
>
On 10/05/2017 06:24 PM, Igor Mammedov wrote:
> use common cpu_model prasing in vl.c and set default cpu_model
> using generic MachineClass::default_cpu_type.
>
> Beside of switching to generic infrastructure it solves several
> issues.
>
> * ppc_cpu_class_by_name() is used to deal with lower/upp
On 10/06/2017 08:10 AM, Nikunj A Dadhania wrote:
> Cédric Le Goater writes:
>
>> Hello,
>>
>> When a CPU is stopped with the 'stop-self' RTAS call, its state
>> 'halted' is switched to 1 and, in this case, the MSR is not taken into
>> account anymore in the cpu_has_work() routine. Only the pendin
Cédric Le Goater writes:
> Hello,
>
> When a CPU is stopped with the 'stop-self' RTAS call, its state
> 'halted' is switched to 1 and, in this case, the MSR is not taken into
> account anymore in the cpu_has_work() routine. Only the pending
> hardware interrupts are checked with their LPCR:PECE*
Quick drive-by comment:
Kevin Wolf writes:
[...]
> Let me try to just consolidate all of the above into a single state
> machine:
>
> 1. CREATED --> RUNNING
> driver callback: .start
> 2a. RUNNING --> READY | CANCELLED
> via: auto transition (when bulk copy is finished) / block-
Paolo Bonzini writes:
> On 05/10/2017 12:51, Dr. David Alan Gilbert (git) wrote:
>> From: Markus Armbruster
>>
>> Screwed up in commit da76ee7.
>
> Let me introduce you to these two aliases:
>
> whatis = "show -s --pretty='tformat:%h (\"%s\", %cd)' --date=short"
> pwhatis = "sho
For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift
right algebraic instructions whenever the CA bit is to be set. This
change affects the following instructions:
* Shift Right Algebraic Word (sraw[.])
* Shift Right Algebraic Word Immediate (srawi[.])
* Shift Right Algebraic Dou
Jan Dakinevich writes:
> On 10/03/2017 05:02 PM, Eric Blake wrote:
>> On 10/03/2017 07:47 AM, Jan Dakinevich wrote:
>>> The command is intended for gathering virtio information such as status,
>>> feature bits, negotiation status. It is convenient and useful for debug
>>> purpose.
>>>
>>> The com
Marc-André Lureau writes:
> On Thu, Oct 5, 2017 at 6:41 AM, Markus Armbruster wrote:
>> Marc-André Lureau writes:
>>
>>> On Mon, Oct 2, 2017 at 5:25 PM, Markus Armbruster wrote:
The QAPI schema parser has always accepted only single-quoted strings,
even though JSON strings are double
Eric Blake writes:
> On 10/04/2017 11:41 PM, Markus Armbruster wrote:
>
>> Sadly, the schema language is neither JSON, nor an established extension
>> of JSON, nor Python. This commit brings the schema language one step
>> closer to a superset of JSON. I feel "homegrown superset" is a slightly
Eric Blake writes:
> On 10/02/2017 10:25 AM, Markus Armbruster wrote:
>> Signed-off-by: Markus Armbruster
>> ---
>> scripts/texi2pod.pl | 11 +--
>> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> My perl is a bit rusty, but I think I can handle this one.
>
>>
>> diff --git a/scrip
On Thu, Oct 05, 2017 at 07:13:07PM +0200, Maxime Coquelin wrote:
> This series is a rebase of the first two patches of Peter's series
> improving address_space_get_iotlb_entry():
> Message-Id: <1496404254-17429-1-git-send-email-pet...@redhat.com>
>
> It is actually not only an improvement, but fix
On 10/05/2017 07:38 AM, Kevin Wolf wrote:
> Am 05.10.2017 um 03:46 hat John Snow geschrieben:
>> On 10/04/2017 02:27 PM, Kevin Wolf wrote:
>>> Am 04.10.2017 um 03:52 hat John Snow geschrieben:
For jobs that complete when a monitor isn't looking, there's no way to
tell what the job's fin
> >> Thanks
> >>
> >> Eric
> >>>
> >>> However you should be allowed to map 1 sg element of 5 pages and
> >>> then notify the host about this event I think. Still looking at the
> >>> code...
> >>>
> >>> I still can't reproduce the issue at the moment. What kind of device
> >>> are you assigning
On Thu, Oct 05, 2017 at 06:24:33PM +0200, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> hw/ppc/mac_oldworld.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
> index bc7c8b7..010e
On Thu, Oct 05, 2017 at 06:24:32PM +0200, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> hw/ppc/mac_newworld.c | 15 ++-
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
> index 6d0
On Thu, Oct 05, 2017 at 06:24:30PM +0200, Igor Mammedov wrote:
> DEFINE_TYPES() will help to simplify following routine patterns:
>
> static void foo_register_types(void)
> {
> type_register_static(&foo1_type_info);
> type_register_static(&foo2_type_info);
> ...
> }
>
> type_init(
On Thu, Oct 05, 2017 at 06:24:28PM +0200, Igor Mammedov wrote:
> type_register()/type_register_static() functions in current impl.
> can't fail returning 0, also none of the users check for error
> so update doc comment to reflect current behaviour.
>
> Suggested-by: Eduardo Habkost
> Signed-off-
On Thu, Oct 05, 2017 at 06:24:38PM +0200, Igor Mammedov wrote:
> ppc_cpu_parse_features() is doing practically the same thing as
> generic cpu_parse_cpu_model(). So remove duplicated impl. and
> reuse generic one.
>
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> include/hw/ppc/
On Thu, Oct 05, 2017 at 06:24:37PM +0200, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> hw/ppc/prep.c | 12
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index 94138a4..6f8accc 100644
> ---
On Thu, Oct 05, 2017 at 06:24:35PM +0200, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> hw/ppc/ppc405_uc.c | 6 --
> hw/ppc/ppc4xx_devs.c | 4 ++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405
On Thu, Oct 05, 2017 at 08:42:56AM -0400, Richard Henderson wrote:
> On 10/03/2017 02:23 AM, Sandipan Das wrote:
> > @@ -231,6 +231,10 @@ target_ulong helper_sraw(CPUPPCState *env,
> > target_ulong value,
> > ret = (int32_t)value >> 31;
> > env->ca = (ret != 0);
> > }
> > +
On Thu, Oct 05, 2017 at 06:24:34PM +0200, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> hw/ppc/ppc440_bamboo.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index f92d47f.
On Thu, Oct 05, 2017 at 06:24:36PM +0200, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
> ---
> hw/ppc/virtex_ml507.c | 11 ---
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
> index ed9b406
On Thu, Oct 05, 2017 at 06:24:29PM +0200, Igor Mammedov wrote:
> it will help to remove code duplication of registration
> static types in places that have open coded loop to
> perform batch type registering.
>
> Signed-off-by: Igor Mammedov
> Reviewed-by: Eduardo Habkost
> Reviewed-by: Philippe
On Thu, Oct 05, 2017 at 06:24:31PM +0200, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Acked-by: David Gibson
Do you want me to queue the ppc patches here, or do you already have a
plan for that?
> ---
> hw/ppc/e500.c | 8 +---
> hw/ppc/e500plat.c | 1 +
> hw/ppc/mpc8544ds.c
On Mon, Aug 07, 2017 at 19:52:16 -0400, Emilio G. Cota wrote:
> This series applies on top of the "multiple TCG contexts" series, v4:
> https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg06769.html
(snip)
> Please review!
Turns out this patchset breaks icount, even after fixing the patchse
On Mon, Sep 25, 2017 at 10:01:15 -0700, Richard Henderson wrote:
> On 09/22/2017 01:40 PM, Emilio G. Cota wrote:
> > Hi Richard,
> >
> > Are you planning to get this patchset merged in this window? If so, I can
> > give it a respin on top of the current master.
>
> Yes, I do. I've been intending
I added the tracing output in this patch to assist me in implementing
an NVMe driver. It helped tremendously.
>From 1d19086cdef8d492929852d582cb41dcc5026f71 Mon Sep 17 00:00:00 2001
From: Doug Gale
Date: Thu, 5 Oct 2017 19:02:03 -0400
Subject: [PATCH] Add tracing output to NVMe emulation to help
Thanks so much for doing that Sean.
Omitting expected changes (uuid, mac address, etc), here's are the
significant changes I see:
1) N uses the QEMU 'virt' model, O uses 'virt-2.8'
2) N and O both expose a pci root, but N also exposed 2 PCI bridges that O does
not.
3) N exposes an additional ser
On 10/05/2017 05:36 AM, Paolo Bonzini wrote:
> On 05/10/2017 12:02, Vladimir Sementsov-Ogievskiy wrote:
>> 03.10.2017 17:06, Paolo Bonzini wrote:
>>> On 03/10/2017 15:35, Vladimir Sementsov-Ogievskiy wrote:
>> In the end this probably means that you have a read_chunk_header
>> function and
On Thu, 5 Oct 2017 18:24:42 +0200
Igor Mammedov wrote:
> consolidate 'host' core type registration by moving it from
> KVM specific code into spapr_cpu_core.c, similar like it's
> done in x86 target.
>
> Signed-off-by: Igor Mammedov
> ---
On the way you could have dropped this line in target/
I want yo add extra functionality of booting from virtual USB through qemu.
I need to write a new block of code in /hw/USB to emulate virtual USB. I
don't have any clue of how to procced. Code documentation of other devices
like hub network would help us understanding and implementing usb
On Thu,
On Thu, 5 Oct 2017 18:24:41 +0200
Igor Mammedov wrote:
> replace sPAPRCPUCoreClass::cpu_class with cpu type name
> since it were needed just to get that at points it were
> accessed.
>
> Signed-off-by: Igor Mammedov
> ---
Reviewed-by: Greg Kurz
> include/hw/ppc/spapr_cpu_core.h | 2 +-
>
Change qemu_config_parse() to return the number of config groups
in success and -EINVAL on error. This will allow callers of
qemu_config_parse() to check if something was really loaded from
the config file.
All existing callers of qemu_config_parse() and
qemu_read_config_file() only check if the r
From: Todd Eisenberger
It looks like there was a transcription error when writing this code
initially. The code previously only decoded src or dst of rax. This
resolves
https://bugs.launchpad.net/qemu/+bug/1719984.
Signed-off-by: Todd Eisenberger
Message-Id:
Reviewed-by: Richard Henderson
S
Both -nodefconfig and -no-user-config options do the same thing
today, we only need one variable to keep track of them.
Suggested-by: Markus Armbruster
Acked-by: Alistair Francis
Reviewed-by: Markus Armbruster
Signed-off-by: Eduardo Habkost
Message-Id: <20171004030025.7866-2-ehabk...@redhat.co
Since 2012 (commit ba6212d8 "Eliminate cpus-x86_64.conf file") we
have no default config files that would be disabled using
-nodefconfig. Update documentation and document -nodefconfig as
deprecated.
Cc: Markus Armbruster
Acked-by: Alistair Francis
Signed-off-by: Eduardo Habkost
Message-Id: <2
From: Igor Mammedov
type_register()/type_register_static() functions in current impl.
can't fail returning 0, also none of the users check for error
so update doc comment to reflect current behaviour.
Suggested-by: Eduardo Habkost
Signed-off-by: Igor Mammedov
Message-Id: <1507111682-66171-2-gi
From: Alistair Francis
This patch add a MachineClass element that can be set in the machine C
code to specify a list of supported CPU types. If the supported CPU
types are specified the user enter CPU (by -cpu at runtime) is checked
against the supported types and QEMU exits if they aren't suppor
From: Dou Liyang
It may be hard to read the assignment statement of "next_base", so
S/next_base += (1ULL << 32) - pcms->below_4g_mem_size;
/next_base = mem_base + mem_len;
... for readability.
No functionality change.
Signed-off-by: Dou Liyang
Message-Id: <1504231805-30957-3-git-send-email-
From: Dou Liyang
As QEMU supports the memory-less node, it is possible that there is
no RAM in the first numa node(also be called as node0). eg:
... \
-m 128,slots=3,maxmem=1G \
-numa node -numa node,mem=128M \
But, this makes it hard for QEMU to build a known-to-work ACPI SRAT
table. Only
The following changes since commit d8f932cc696250cb740240d668b39df5fbb2d5a0:
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
into staging (2017-10-05 16:54:29 +0100)
are available in the git repository at:
git://github.com/ehabkost/qemu.git tags/x86-and-machine-pul
From: Philippe Mathieu-Daudé
and clean every implementation.
Suggested-by: Eduardo Habkost
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20170917232842.14544-1-f4...@amsat.org>
Reviewed-by: Igor Mammedov
Reviewed-by: Laurent Vivier
Reviewed-by: Artyom Tarasenko
Signed-off-by: Eduardo H
On Thu, 5 Oct 2017 18:24:40 +0200
Igor Mammedov wrote:
> spapr core type definition doesn't have any fields that
> require it to be defined at runtime. So replace code
> that fills in TypeInfo at runtime with static TypeInfo
> array that does the same at complie time.
>
> Signed-off-by: Igor Ma
On 5 October 2017 at 19:56, Richard Henderson
wrote:
> On 09/22/2017 11:00 AM, Peter Maydell wrote:
>> +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
>> +{
> ...
>> +if (dest & 1) {
>> +/* target is Secure, so this is just a normal BLX,
>> + * except that the low bit
In cases where a device is hotplugged and hot-unplugged shortly after,
there is a chance of QEMU breaking with the following message:
hw/ppc/spapr_drc.c:417:spapr_drc_detach: assertion failed: (drc->dev)
Aborted
spapr_drc_detach makes a g_assert(drc->dev) to ensure that the following
spapr_drc_re
On 10/05/2017 12:48 PM, Stefan Berger wrote:
This patch adds a description of the current TPM support in QEMU
to the specs.
Several public specs are referenced via their landing page on the
trustedcomputinggroup.org website.
Signed-off-by: Stefan Berger
Reviewed-by: Laszlo Ersek
This is obv
On Thu, 5 Oct 2017 18:24:39 +0200
Igor Mammedov wrote:
> there is a dedicated callback CPUClass::parse_features
> which purpose is to convert -cpu features into a set of
> global properties AND deal with compat/legacy features
> that couldn't be directly translated into CPU's properties.
>
> Cr
On 10/05/2017 02:07 PM, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> opt was declared as a separate local inside the last loop,
> shadowing the local at the top of the function.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> util/qemu-option.c | 2 +-
> 1 file ch
Improve our braindead copy-on-read implementation. Pre-patch,
we have multiple issues:
- we create a bounce buffer and perform a write for the entire
request, even if the active image already has 99% of the
clusters occupied, and really only needs to copy-on-read the
remaining 1% of the clusters
-
* Dr. David Alan Gilbert (git) (dgilb...@redhat.com) wrote:
> From: "Dr. David Alan Gilbert"
>
> Convert the 'modern_state' part of virtio-pci to modern migration
> macros.
Ping.
Dave
> Signed-off-by: Dr. David Alan Gilbert
> ---
> hw/virtio/virtio-pci.c | 108
> +---
Add a test for qcow2 copy-on-read behavior, including exposure
for the just-fixed bugs.
The copy-on-read behavior is always to a qcow2 image, but the
test is careful to allow running with most image protocol/format
combos as the backing file being copied from (luks being the
exception, as it is ha
Fix console selection keys so that the right console is selected.
Signed-off-by: John Arbuckle
---
ui/cocoa.m | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 93e56d0518..2794f60b27 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -631,7 +631,7 @@ - (
Make it possible to inject errors on writes performed during a
read operation due to copy-on-read semantics.
Signed-off-by: Eric Blake
Reviewed-by: Jeff Cody
Reviewed-by: Kevin Wolf
Reviewed-by: John Snow
Reviewed-by: Stefan Hajnoczi
---
qapi/block-core.json | 5 -
block/io.c |
Handle a 0-length block status request up front, with a uniform
return value claiming the area is not allocated.
Most callers don't pass a length of 0 to bdrv_get_block_status()
and friends; but it definitely happens with a 0-length read when
copy-on-read is enabled. While we could audit all call
From: "Dr. David Alan Gilbert"
opt was declared as a separate local inside the last loop,
shadowing the local at the top of the function.
Signed-off-by: Dr. David Alan Gilbert
---
util/qemu-option.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/qemu-option.c b/util/q
During my quest to switch block status to be byte-based, John
forced me to evaluate whether we have a situation during
copy-on-read where we could exceed BDRV_REQUEST_MAX_BYTES [1].
Sure enough, we have a number of pre-existing bugs in the
copy-on-read code. Fix those, along with adding a test.
A
Executing qemu with a terminal as stdin will temporarily alter stty
settings on that terminal (for example, disabling echo), because of
how we run both the monitor and any multiplexing with guest input.
Normally, qemu restores the original settings on exit; but if an
iotest triggers qemu to abort i
Make it easier to enable copy-on-read during iotests, by
exposing a new bool option to main and open.
Signed-off-by: Eric Blake
Reviewed-by: Jeff Cody
Reviewed-by: Kevin Wolf
Reviewed-by: John Snow
Reviewed-by: Stefan Hajnoczi
---
qemu-io.c | 15 ---
1 file changed, 12 insertions
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> When we added support for the new SHCSR bits in v8M in commit
> 437d59c17e9 the code to support writing to the new HARDFAULTPENDED
> bit was accidentally only added for non-secure writes; the
> secure banked version of the bit should also be writable.
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> Secure function return happens when a non-secure function has been
> called using BLXNS and so has a particular magic LR value (either
> 0xfefe or 0xfeff). The function return via BX behaves
> specially when the new PC value is this magic value
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
> +{
...
> +if (dest & 1) {
> +/* target is Secure, so this is just a normal BLX,
> + * except that the low bit doesn't indicate Thumb/not.
> + */
> +env->regs
On 10/05/2017 02:55 PM, Peter Maydell wrote:
> Oops. I missed this in my testing because it happens that the
> two halves of an SG instruction are the same value :-)
Hah. I didn't notice that either.
r~
On 5 October 2017 at 19:50, Richard Henderson
wrote:
> On 09/22/2017 11:00 AM, Peter Maydell wrote:
>> Implement the SG instruction, which we emulate 'by hand' in the
>> exception handling code path.
>>
>> Signed-off-by: Peter Maydell
>> ---
>> target/arm/helper.c | 129
>> +
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> Implement the SG instruction, which we emulate 'by hand' in the
> exception handling code path.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/helper.c | 129
> ++--
> 1 file changed, 124 inserti
Make scrolling in the monitor work.
Signed-off-by: John Arbuckle
---
ui/cocoa.m | 88 +++---
1 file changed, 56 insertions(+), 32 deletions(-)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 93e56d0518..5545c42b9c 100644
--- a/ui/cocoa.m
+++ b/
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> For the SG instruction and secure function return we are going
> to want to do memory accesses using the MMU index of the CPU
> in secure state, even though the CPU is currently in non-secure
> state. Write arm_v7m_mmu_idx_for_secstate() to do this job
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> In cpu_mmu_index() we try to do this:
> if (env->v7m.secure) {
> mmu_idx += ARMMMUIdx_MSUser;
> }
> but it will give the wrong answer, because ARMMMUIdx_MSUser
> includes the 0x40 ARM_MMU_IDX_M field, and so does the
> mmu_i
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> Implement the security attribute lookups for memory accesses
> in the get_phys_addr() functions, causing these to generate
> various kinds of SecureFault for bad accesses.
>
> The major subtlety in this code relates to handling of the
> case when the
On Thu, 5 Oct 2017 18:24:38 +0200
Igor Mammedov wrote:
> ppc_cpu_parse_features() is doing practically the same thing as
> generic cpu_parse_cpu_model(). So remove duplicated impl. and
> reuse generic one.
>
> Signed-off-by: Igor Mammedov
> ---
Reviewed-by: Greg Kurz
> include/hw/ppc/ppc.h
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> Implement the register interface for the SAU: SAU_CTRL,
> SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the
> actual behaviour is implemented here; registers just
> read back as written.
>
> When the CPU definition for Cortex-M33 is eventually
> a
On 09/22/2017 10:59 AM, Peter Maydell wrote:
> Add support for v8M and in particular the security extension
> to the exception entry code. This requires changes to:
> * calculation of the exception-return magic LR value
> * push the callee-saves registers in certain cases
> * clear registers whe
On 10/05/2017 12:03 AM, Swetheendra Tallamraju wrote:
> I am working on qemu source code to provide extra functionality of
> emulating virtual usb. Can I get any documentation for the qemu source
> code that helps me in implementing this?
>
The docs in source code and in the docs/ folder are
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20171005145557.5746-1-programmingk...@gmail.com
Subject: [Qemu-devel] [PATCH v2 0/2] ui/cocoa.m: enable guest to see
control-alt key combinations
=== TEST SCRIPT BEGIN ===
#
Nikolay: You mentioned a while ago that you had issues with incremental
backup's eventual return status being unknown. Can you please elaborate
for me why this is a problem?
I assume due to the long running of a backup job it's entirely possible
to imagine losing connection to QEMU and missing the
Hi,
has somebody reviewed this patch ?
I'm also able de reproduce the vm crash like the proxmox user.
This patch is fixing it for me too.
Regards,
Alexandre
- Mail original -
De: "Wolfgang Bumiller"
À: "qemu-devel"
Cc: "pbonzini" , "Michael S. Tsirkin"
Envoyé: Mercredi 20 Septembre
On 09/22/2017 10:59 AM, Peter Maydell wrote:
> For v8M, exceptions from Secure to Non-Secure state will save
> callee-saved registers to the exception frame as well as the
> caller-saved registers. Add support for unstacking these
> registers in exception exit when necessary.
>
> Signed-off-by: Pe
On 05/10/17 14:51, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
> Reviewed-by: Philippe Mathieu-Daudé
> Tested-by: Philippe Mathieu-Daudé
> ---
> CC: mark.cave-ayl...@ilande.co.uk
> CC: atar4q...@gmail.com
> ---
> hw/sparc/sun4m.c | 29 -
> 1 file changed, 12
All scripts that use the QEMUMachine and QEMUQtestMachine classes
(device-crash-test, tests/migration/*, iotests.py, basevm.py)
already configure logging.
The basicConfig() call inside QEMUMachine.__init__() is being
kept just to make sure a script would still work if it didn't
configure logging.
The logging module will eventually replace the 'debug' parameter
in QEMUMachine and QEMUMonitorProtocol.
Cc: Daniel P. Berrange
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* Inline init_logging() method on all callers because not all
classes derive from BaseShell (reported by Lukáš Do
Use logging module for the QMP debug messages. The only scripts
that set debug=True are iotests.py and guestperf/engine.py, and
they already call logging.basicConfig() to set up logging.
Scripts that don't configure logging are safe as long as they
don't need debugging output, because debug messa
Changes v1 -> v2:
* Rebased to python-next (some patches from v1 are already queued
there)S
* guestperf: Inline init_logging() method on all callers because
not all classes derive from BaseShell (reported by Lukáš
Doktor)
This series removes the 'debug' parameter from QEMUMachine and
QEMUMon
On 09/22/2017 10:59 AM, Peter Maydell wrote:
> In v8M, more bits are defined in the exception-return magic
> values; update the code that checks these so we accept
> the v8M values when the CPU permits them.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/helper.c | 73
> +++
From: Peter Xu
This patch let address_space_get_iotlb_entry() to use the newly
introduced page_mask parameter in flatview_do_translate(). Then we
will be sure the IOTLB can be aligned to page mask, also we should
nicely support huge pages now when introducing a764040.
Fixes: a764040 ("exec: abst
On Thu, Oct 05, 2017 at 03:59:12PM +0200, Igor Mammedov wrote:
> On Thu, 5 Oct 2017 14:32:17 +0200
> Thomas Huth wrote:
>
> > Instead of doing the clean-ups on errors multiple times, introduce
> > a jump label at the end of the function that can be used by all
> > error paths that need this clea
From: Peter Xu
The function is originally used for flatview_space_translate() and what
we care about most is (xlat, plen) range. However for iotlb requests, we
don't really care about "plen", but the size of the page that "xlat" is
located on. While, plen cannot really contain this information.
This series is a rebase of the first two patches of Peter's series
improving address_space_get_iotlb_entry():
Message-Id: <1496404254-17429-1-git-send-email-pet...@redhat.com>
It is actually not only an improvement, but fixes a regression in the way
IOTLB updates sent to the backends are generated
On Thu, Oct 05, 2017 at 11:04:27AM +0200, Igor Mammedov wrote:
> On Wed, 4 Oct 2017 14:39:20 -0700
> Alistair Francis wrote:
>
> > On Wed, Oct 4, 2017 at 9:34 AM, Eduardo Habkost wrote:
> > > On Wed, Oct 04, 2017 at 03:08:16PM +0200, Igor Mammedov wrote:
> > >> On Wed, 4 Oct 2017 09:28:51 -030
Hi Linu,
On 05/10/2017 14:13, Auger Eric wrote:
> Hi Linu,
>
> On 05/10/2017 13:54, Auger Eric wrote:
>> Hi Linu,
>> On 05/10/2017 12:46, Auger Eric wrote:
>>> Hi Linu,
>>> On 04/10/2017 13:49, Linu Cherian wrote:
Hi Eric,
On Wed Sep 27, 2017 at 11:24:01AM +0200, Auger Eric wr
When a CPU is stopped with the 'stop-self' RTAS call, its state
'halted' is switched to 1 and, in this case, the MSR is not taken into
account anymore in the cpu_has_work() routine. Only the pending
hardware interrupts are checked with their LPCR:PECE* enablement bit.
If the DECR timer fires after
On 5 October 2017 at 17:54, Stefan Berger wrote:
> On 10/05/2017 12:53 PM, Peter Maydell wrote:
>> Hi; this pull request appears to be signed with a gpg key that
>> isn't signed by anybody else... Are there other people you work
>> with at IBM who can verify your id and sign your key for you?
>
>
This patch adds a description of the current TPM support in QEMU
to the specs.
Several public specs are referenced via their landing page on the
trustedcomputinggroup.org website.
Signed-off-by: Stefan Berger
Reviewed-by: Laszlo Ersek
---
docs/specs/tpm.txt | 123 ++
On 10/05/2017 12:53 PM, Peter Maydell wrote:
On 5 October 2017 at 17:48, Stefan Berger wrote:
The following changes since commit d147f7e815f97cb477e223586bcb80c316ae10ea:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
staging (2017-10-03 16:27:24 +0100)
are availabl
On 10/04/2017 07:00 PM, Eric Blake wrote:
> On 10/04/2017 09:26 AM, Jan Dakinevich wrote:
>
>> +{
>> +'struct': 'VirtioInfo',
>> +'data': {
>> +'feature-names': ['VirtioInfoBit'],
>
> Why is feature-names listed at two different nestings of the return valu
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