On Wed, Jun 21, 2017 at 05:03:08PM -0700, Aaron Larson wrote:
> Properly set the book E exception syndrome register when a floating
> point exception occurs.
>
> Currently on a book E processor, the POWERPC_EXCP_FP exception handler
> fails to set "env->spr[SPR_BOOKE_ESR] = ESR_FP;" as required by
On Mon, 2017-06-26 at 11:28 +0100, Daniel P. Berrange wrote:
> On Fri, Jun 23, 2017 at 12:31:06PM +0200, Knut Omang wrote:
> >
> > First refactoring step to prepare for fixing the problem
> > exposed with the test-listen test in the previous commit
> >
> > Signed-off-by: Knut Omang
> > ---
> >
On Thu, Jun 22, 2017 at 02:41:56PM +0200, Marc-André Lureau wrote:
> I used the clang-tidy qemu-round check to generate the fix:
> https://github.com/elmarco/clang-tools-extra
>
> Signed-off-by: Marc-André Lureau
Acked-by: David Gibson
> ---
> target/ppc/mem_helper.c | 2 +-
> target/ppc/tran
From: Ben Warren
The following tests are implemented:
* test that a GUID passed in by command line is propagated to the guest.
Read the GUID from guest memory
* test that the "auto" argument to the GUID generates a valid GUID, as
seen by the guest.
* test that a GUID passed in can be queried
Nice improvement!
> On Jun 29, 2017, at 9:23 AM, Marc-André Lureau
> wrote:
>
> This compat property sole function is to prevent the device from being
> instantiated. Instead of requiring an extra compat property, check if
> fw_cfg has DMA enabled.
>
> This has the additional benefit of handlin
On 06/28/2017 07:13 AM, Lluís Vilanova wrote:
@@ -11377,6 +11385,9 @@ static void aarch64_trblock_tb_stop(DisasContextBase
*dcbase, CPUState *cpu)
break;
}
}
+
+/* Functions above can change dc->pc, so re-align db->pc_next */
+dc->base.pc_next = dc->pc;
}
On 06/28/2017 07:09 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate-a64.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henders
On 06/28/2017 07:05 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
On 06/28/2017 07:01 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate-a64.c | 123 +++-
1 file changed, 65 insertions(+), 58 deletions(-)
On 06/28/2017 06:57 AM, Lluís Vilanova wrote:
-if (max_insns > TCG_MAX_INSNS) {
-max_insns = TCG_MAX_INSNS;
+if ((dc->base.tb->cflags & CF_LAST_IO) && dc->condjmp) {
+/* FIXME: This can theoretically happen with self-modifying code. */
+cpu_abort(cpu, "IO on condit
On 06/28/2017 06:53 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate-a64.c | 74 +++-
1 file changed, 46 insertions(+), 28 deletions(-
On 06/28/2017 06:49 AM, Lluís Vilanova wrote:
+/* We want to stop the TB if the next insn starts in a new page,
+ * or if it spans between this page and the next. This means that
+ * if we're looking at the last halfword in the page we need to
+ * see if it's a 16-
On 06/28/2017 06:45 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate-a64.c | 58 +---
1 file changed, 43 insertions(+), 15 deletions(-)
On 06/28/2017 06:41 AM, Lluís Vilanova wrote:
-if (unlikely(dc->base.is_jmp > DISAS_NEXT)) {
-break;
-}
-
Surely this doesn't go away til the final conversion.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 06/28/2017 06:37 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate-a64.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
On 06/28/2017 06:33 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate.c | 34 ++
1 file changed, 22 insertions(+), 12 deletions(-)
Reviewed-by
On 06/28/2017 06:29 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate.c | 82 ++--
1 file changed, 44 insertions(+), 38 deletions(-)
On 06/28/2017 06:25 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
Reviewed-by: Richard Hend
On 06/28/2017 06:21 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate-a64.c | 36 ++--
1 file changed, 22 insertions(+), 14 deletions(-)
Revie
On 06/28/2017 06:17 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate.c | 85 +++-
1 file changed, 47 insertions(+), 38 deletions(-)
On 06/28/2017 06:13 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/arm/translate-a64.c | 119 ++--
target/arm/translate.c | 114 +++
On 06/28/2017 06:09 AM, Lluís Vilanova wrote:
Signed-off-by: Lluís Vilanova
---
target/i386/translate.c | 120 +++
1 file changed, 18 insertions(+), 102 deletions(-)
Reviewed-by: Richard Henderson
r~
On 06/28/2017 06:05 AM, Lluís Vilanova wrote:
+#ifdef TARGET_X86_64
+if (dc->code64)
+disas_flags = 2;
+else
+#endif
+disas_flags = !dc->code32;
Even though this is code movement, missing braces.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 06/28/2017 06:01 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/i386/translate.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
Reviewed-by: Richa
On 06/28/2017 05:57 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/i386/translate.c | 72 +++
1 file changed, 48 insertions(+), 24 deletions(-)
On 06/28/2017 05:52 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/i386/translate.c | 59 ++-
1 file changed, 48 insertions(+), 11 deletions(-)
On 06/28/2017 05:48 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/i386/translate.c |9 -
1 file changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 06/28/2017 05:44 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/i386/translate.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
Reviewed-by: Ri
On 06/28/2017 05:40 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/i386/translate.c | 43 ---
1 file changed, 24 insertions(+), 19 deletions(-)
R
On 06/28/2017 05:36 AM, Lluís Vilanova wrote:
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova
---
target/i386/translate.c | 142 +++
1 file changed, 70 insertions(+), 72 deletions(-)
On 06/28/2017 05:32 AM, Lluís Vilanova wrote:
+void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
+void (*init_globals)(DisasContextBase *db, CPUState *cpu);
+void (*tb_start)(DisasContextBase *db, CPUState *cpu);
+void (*insn_start)(DisasContextBase *db, CPUState *c
On 06/29/2017 05:02 PM, Emilio G. Cota wrote:
+void translate_block(const TranslatorOps *ops, DisasContextBase *db,
+ CPUState *cpu, TranslationBlock *tb);
I'd rather avoid "block" here. Some alternatives:
- tb_translate()
- translate_tb()
- translate()
- translator_gen()
-
On 06/28/2017 05:28 AM, Lluís Vilanova wrote:
Used later. An enum makes expected values explicit and bounds the value space of
switches.
Signed-off-by: Lluís Vilanova
---
include/exec/exec-all.h |6 --
include/exec/translator.h | 38 ++
On 1 July 2017 at 23:35, Richard Henderson wrote:
> On 07/01/2017 03:30 PM, Peter Maydell wrote:
>>
>> On 1 July 2017 at 23:20, Richard Henderson wrote:
>>> That is an absolutely stupid warning. There's long precedent for the
>>> compiler choosing the prefix for you based on the type of the argu
On 06/28/2017 05:20 AM, Lluís Vilanova wrote:
-void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
+void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
Ought to change the argument name too.
r~
On 07/01/2017 03:30 PM, Peter Maydell wrote:
On 1 July 2017 at 23:20, Richard Henderson wrote:
On 06/30/2017 08:39 AM, Pranith Kumar wrote:
Clang generates the following warning on aarch64 host:
CC util/cacheinfo.o
/home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does
On 1 July 2017 at 23:20, Richard Henderson wrote:
> On 06/30/2017 08:39 AM, Pranith Kumar wrote:
>>
>> Clang generates the following warning on aarch64 host:
>>
>>CC util/cacheinfo.o
>> /home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not
>> match register size specifi
On 06/30/2017 08:39 AM, Pranith Kumar wrote:
Clang generates the following warning on aarch64 host:
CC util/cacheinfo.o
/home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match
register size specified by the constraint and modifier [-Wasm-operand-widths]
a
On 06/29/17 21:31, Stefan Berger wrote:
> On 06/27/2017 12:32 PM, Laszlo Ersek wrote:
>>
>> Looks great to me, thank you!
>>
>> Two requests in addition to the above remarks:
>> - can you provide command line options / examples wherever appropriate?
>
> I didn't add it because we describe that on
The rotation is to the left, but extract shifts to the right.
The computation of the extract parameters needs adjusting.
For the entry condition, simplify
64 - rot + len <= 64
-rot + len <= 0
len <= rot
Reported-by: David Hildenbrand
Suggested-by: Aurelien Jarno
Signed-
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
target/s390x/cpu_models.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 08290ce..91ef8eb 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@
Drop TRT from the set of insns handled internally by EXECUTE.
It's more important to adjust the existing helper to handle
both TRT and TRTR.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 1 +
target/s390x/mem_helper.c | 20 +---
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 6 +
target/s390x/mem_helper.c | 310 +
target/s390x/translate.c | 44 +++
target/s390x/insn-data.def | 13 ++
4 files changed, 373 insertions(+)
diff --git a/target/s390x/hel
Since we require all registers saved on input, read R0 from ENV instead
of passing it manually. Recognize the specification exception when R0
contains incorrect data. Keep high bits of result registers unmodified
when in 31 or 24-bit mode.
Signed-off-by: Richard Henderson
---
target/s390x/help
From: David Hildenbrand
STFL bit 4 and 5 are just indications to the guest, which TLB entries an
IDTE call will clear. These are performance indicators for the guest.
STFL bit 4:
INVALIDATE DAT TABLE ENTRY (IDTE) performs
the invalidation-and-clearing operation by
selectively clearin
On 06/25/2017 03:19 PM, Aurelien Jarno wrote:
On 2017-06-23 01:12, David Hildenbrand wrote:
If we have for example: r3 contains 0x
ec 33 3f bf 61 55 risbg %r3,%r3,63,191,97
We want to rotate 33 to the left and only keep MSB bit 63 of that. So the
result is then exac
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 1 +
target/s390x/cpu_models.c | 2 +
target/s390x/mem_helper.c | 189 +
target/s390x/translate.c | 13 +++-
target/s390x/insn-data.def | 2 +
5 files changed, 206 insertions(+
Changes since v1:
* Errors corrected in CONVERT UNICODE
* Address writeback corrected in SRST/SRSTU
* IDTES feature added.
* RISBG handling fixed.
r~
David Hildenbrand (1):
target/s390x: Allow to enable "idtes" feature for TCG
Richard Henderson (7):
target/s390x: Implement CSST
t
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 1 +
target/s390x/mem_helper.c | 41 +
target/s390x/translate.c | 13 +
target/s390x/insn-data.def | 2 ++
4 files changed, 57 insertions(+)
diff --git a/target/s390x/helper
Public bug reported:
When running the gnulib testsuite, I'm seeing test failures in the tests for
libm functions
cbrt
cbrtf
ceil
ceilf
coshf
exp2
exp2f
floor
floorf
fma
fmaf
fmal
frexp
frexpf
hypot
hypotf
hypotl
ilogb
ilogbf
isfinite
isinf
isnan
isnan
Am 23.01.2017 um 11:28 schrieb Stefan Hajnoczi:
> On Sun, Jan 22, 2017 at 04:19:43PM +0100, Stefan Weil wrote:
>> On 03/02/15 23:12, Stefan Hajnoczi wrote:
>>> On Sat, Feb 28, 2015 at 04:29:44PM +0100, Stefan Weil wrote:
* It does not support secure access (https), so each login is insecure.
>
When adding a PMU with a userspace irqchip we only do the INIT
stage of the device creation.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c| 10 --
target/arm/kvm32.c | 6 ++
target/arm/kvm64.c | 52 +---
target/arm/kvm_arm.
Move the in-kernel-irqchip test to only guard the creation,
not the init'ing of the PMU. Also add the PMU to the KVM
device irq line synchronization to enable its use.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 2 +-
target/arm/kvm.c | 6 +-
target/arm/kvm64.c | 3 +--
3 files c
Andrew Jones (3):
hw/arm/virt: add pmu interrupt state
target/arm/kvm: split pmu init from creation
hw/arm/virt: allow pmu instantiation with userspace irqchip
hw/arm/virt.c| 13 +++--
target/arm/cpu.c | 2 ++
target/arm/cpu.h | 2 ++
target/arm/kvm.c | 6
Mimicking gicv3-maintenance-interrupt, add the PMU's interrupt to
CPU state.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c| 3 +++
target/arm/cpu.c | 2 ++
target/arm/cpu.h | 2 ++
3 files changed, 7 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 010f7244bf7c..9781e1cc5ed7 1
Public bug reported:
When running the gnulib testsuite, I'm seeing test failures in the tests for
libm functions
asinf
cbrtf
copysignf
coshf
expm1f
fabsf
floor
fmaf
ldexpf
logbf
round
roundf
sinhf
tanhf
How to reproduce:
- Using gnulib, run ./gnulib-tool --create-test
bdrv_open_driver() is called in two places, bdrv_new_open_driver() and
bdrv_open_common(). In the latter, failure cleanup in is in its caller,
bdrv_open_inherit(), which unrefs the bs->file of the failed driver open if it
exists.
Let's move the bs->file cleanup to bdrv_open_driver() to take care o
Signed-off-by: Benyu Xu
---
qemu-options.hx | 19 +++
1 file changed, 19 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index 297bd8a..0c2cec3 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -141,6 +141,25 @@ given, the total number of CPUs @var{n} can be omit
Pin vcpus to pcpus(set CPU affinity).
When run a Qemu in terminal, if we want to set the cpu affinity, for example,
using the tool taskset, we should find the cpus' thread ID first and then
pin it manually. It's a tedious process, now a new feature "vcpupin" can help
this. This feature will be hel
Signed-off-by: Benyu Xu
---
vl.c | 115 +++
1 file changed, 115 insertions(+)
diff --git a/vl.c b/vl.c
index 36ff3f4..8c5dd25 100644
--- a/vl.c
+++ b/vl.c
@@ -167,6 +167,7 @@ int smp_cpus = 1;
int max_cpus = 1;
int smp_cores = 1;
Signed-off-by: Benyu Xu
---
cpus.c| 126 ++
include/qom/cpu.h | 9
include/sysemu/cpus.h | 2 +
3 files changed, 137 insertions(+)
diff --git a/cpus.c b/cpus.c
index 14bb8d5..40c3abf 100644
--- a/cpus.c
+++ b/cpus.c
@@
On Fri, Jun 30, 2017 at 01:40:58PM +0200, Markus Armbruster wrote:
[...]
>
> I doubt the macros make the bug fixing materially easier, and I doubt
> they can reduce future bugs of this kind. What they can do is letting
> us get rid of error_propagate() boilerplate with relative ease.
>
> If we s
On Fri, Jun 30, 2017 at 01:40:58PM +0200, Markus Armbruster wrote:
> Eduardo Habkost writes:
>
> > On Thu, Jun 29, 2017 at 08:54:29AM +0200, Markus Armbruster wrote:
> >> Eduardo Habkost writes:
> >>
> >> > On Wed, Jun 28, 2017 at 11:05:26AM +0200, Markus Armbruster wrote:
> >> >> Eduardo Habko
Public bug reported:
A program that invokes recvmsg aborts with "*** stack smashing detected
***" when run in qemu-aarch64 (user mode), but works fine when running
on native aarch64 hardware.
How to reproduce:
$ aarch64-linux-gnu-gcc-5 -O -Wall /media/develdata/devel/qemu-bug/testpassfd.c
-stati
** Attachment added: "Statically compiled test program"
https://bugs.launchpad.net/qemu/+bug/1701808/+attachment/4907340/+files/a.out
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1701808
Title:
I would guess that the problem comes from a missing (or an extra) BSWAP call in
one of the files
include/elf.h
include/hw/elf_ops.h
linux-user/elfload.c
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net
Public bug reported:
On the targets
hppa
m68k
mips
mips64
powerpc
powerpc64
s390x
sparc64
dynamically linked binaries crash, but statically linked binaries work.
On the targets
aarch64
alpha
armhf
powerpc64le
sh4
both dynamically linked and statically linked binaries work
Likewise for 32-bit arm:
$ ~/inst-qemu/2.9.0/bin/qemu-arm ./a.arm
*** stack smashing detected ***: ./a.arm terminated
qemu: uncaught target signal 6 (Aborted) - core dumped
** Attachment added: "Statically compiled test program for arm"
https://bugs.launchpad.net/qemu/+bug/1701808/+attachment
On Wed, Jun 28, 2017 at 04:09:19PM +0200, Laurent Vivier wrote:
1;4602;0c> since commit 5c4537bd ("spapr: Fix 2.7<->2.8 migration of PCI host
bridge"),
> some migration fields are forged from the new ones in spapr_pci_pre_save().
>
> It works well, except when the number of MSI devices is 0,
> be
On Fri, Jun 30, 2017 at 11:37:07AM +0200, Greg Kurz wrote:
> $ git grep spapr_ppc_reset
> hw/ppc/spapr.c: * as part of spapr_ppc_reset().
>
> $ git grep ppc_spapr_reset
> hw/ppc/spapr.c:static void ppc_spapr_reset(void)
> hw/ppc/spapr.c:mc->reset = ppc_spapr_reset;
> hw/ppc/spapr_hcall.c:
On Fri, Jun 30, 2017 at 12:05:32PM +0200, Greg Kurz wrote:
> We have more of these since the addition of KVMPPC_H_LOGICAL_MEMOP in 2012.
>
> Signed-off-by: Greg Kurz
Applied to ppc-for-2.10.
> ---
> include/hw/ppc/spapr.h |5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> dif
On Fri, Jun 30, 2017 at 03:18:10PM +0200, Greg Kurz wrote:
> Since commit ff9006ddbfd1 ("spapr: move spapr_core_[foo]plug() callbacks
> close to machine code in spapr.c"), this function doesn't need to be extern
> anymore.
>
> Signed-off-by: Greg Kurz
Applied to ppc-for-2.10.
> ---
> hw/ppc/sp
On Fri, Jun 30, 2017 at 01:03:46PM +0200, Greg Kurz wrote:
> Not sure Sam's and Suraj's email addresses are correct but you also used
> them in the "target/ppc/cpu-models: set POWER9_v1.0 as POWER9 DD1" thread
> and, strangely, I don't seem to receive 'unknow recipient' messages from
> the Redhat
73 matches
Mail list logo
