On 04/06/17 10:43 +0100, Stefan Hajnoczi wrote:
> On Fri, Mar 31, 2017 at 04:41:43PM +0800, Haozhong Zhang wrote:
> > This patch series constructs the flush hint address structures for
> > nvdimm devices in QEMU.
> >
> > It's of course not for 2.9. I send it out early in order to get
> > comments
On 04/11/2017 04:23 AM, David Gibson wrote:
> On Mon, Apr 10, 2017 at 03:56:51PM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> It adds the Naples chip which supports proper LPC interrupts via the
>> LPC controller rather than via an external CPLD.
>>
>> Signed-off-by: Benjam
On Tue, Apr 11, 2017 at 04:04:56PM +1000, Anton Blanchard wrote:
> From: Anton Blanchard
>
> gdb refuses to parse QEMU memory dumps because struct PPCElfPrstatus
> is the wrong size. Fix it.
>
> Signed-off-by: Anton Blanchard
> Fixes: e62fbc54d459 ("target-ppc: dump-guest-memory support")
Appl
On Tue, Apr 11, 2017 at 01:05:51PM +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2017-04-10 at 18:14 +1000, David Gibson wrote:
> > > + switch (size) {
> > > + case 1:
> > > + break;
> > > + case 2:
> > > + val = bswap16(val);
> >
> > An unconditional bswap() seems unlikel
From: Anton Blanchard
gdb refuses to parse QEMU memory dumps because struct PPCElfPrstatus
is the wrong size. Fix it.
Signed-off-by: Anton Blanchard
Fixes: e62fbc54d459 ("target-ppc: dump-guest-memory support")
---
target/ppc/arch_dump.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
On Tue, Apr 11, 2017 at 3:50 AM, Stefano Stabellini
wrote:
> On Mon, 10 Apr 2017, Stefano Stabellini wrote:
>> On Mon, 10 Apr 2017, hrg wrote:
>> > On Sun, Apr 9, 2017 at 11:55 PM, hrg wrote:
>> > > On Sun, Apr 9, 2017 at 11:52 PM, hrg wrote:
>> > >> Hi,
>> > >>
>> > >> In xen_map_cache_unlocked
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/897193
Title:
virtfs: kern
On Thu, Apr 06, 2017 at 03:08:59PM +0200, Juan Quintela wrote:
> We can calculate its value, so not create a varible for it.
>
> Signed-off-by: Juan Quintela
>
> --
>
> After Peter and Dave review, I dropped the variable and just inlined
> the condition.
>
> Later, Juan.
>
> Signed-off-by: Ju
On Thu, Apr 06, 2017 at 03:08:30PM +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
-- peterx
On Thu, Apr 06, 2017 at 03:08:28PM +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
-- peterx
On Thu, Apr 06, 2017 at 03:08:27PM +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Peter Xu
-- peterx
On Thu, Apr 06, 2017 at 03:08:21PM +0200, Juan Quintela wrote:
> It reflects better what it does.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
Thanks,
-- peterx
11.04.2017 00:49, John Snow wrote:
On 02/17/2017 02:51 PM, Dr. David Alan Gilbert wrote:
* Fam Zheng (f...@redhat.com) wrote:
On Fri, 02/17 16:36, Vladimir Sementsov-Ogievskiy wrote:
17.02.2017 15:21, Fam Zheng wrote:
On Fri, 02/17 13:20, Vladimir Sementsov-Ogievskiy wrote:
16.02.2017 16:48
On 04/10/2017 10:20 PM, Michael Roth wrote:
Quoting Philippe Mathieu-Daudé (2017-04-07 17:20:16)
Suggested-by: Michael Roth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael Roth
---
Michael should I use Signed-off-by instead of the Suggested-by (since it is your
code)?
I supp
On Mon, 2017-04-10 at 18:14 +1000, David Gibson wrote:
> > + switch (size) {
> > + case 1:
> > + break;
> > + case 2:
> > + val = bswap16(val);
>
> An unconditional bswap() seems unlikely to be correct. What's the
> purpose of thise?
Though it is :-) I *think* ... I did te
On 04/04/2017 01:31 PM, Marc-André Lureau wrote:
Hi Philippe
- Original Message -
Hi Marc-André,
On 03/16/2017 06:21 AM, Marc-André Lureau wrote:
mux_chr_event() already send events to all backends, rename it,
export it, and use it from muxes_realize_done. This should help abstract
aw
On 03/16/2017 06:21 AM, Marc-André Lureau wrote:
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
chardev/char-socket.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/chardev/char-socket.c b/chardev/char-socket.c
index 81021c5863..06389393fa 100644
On 03/16/2017 06:21 AM, Marc-André Lureau wrote:
Add a property to lookup the connection details.
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
chardev/char-socket.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/chardev/char-socket.c b/chard
On 03/16/2017 06:21 AM, Marc-André Lureau wrote:
This helper will be used in yet another place in the following patch.
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
chardev/char-socket.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
dif
On 03/16/2017 06:21 AM, Marc-André Lureau wrote:
object_property_add_child() references the child, unref it after to
avoid ref leaks.
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
qom/container.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/qom/container.
On Mon, Apr 10, 2017 at 03:56:57PM +0200, Cédric Le Goater wrote:
> Skiboot, the firmware for the PowerNV platform, expects the BMC to
> provide some specific IPMI sensors. These sensors are exposed in the
> device tree and their values are updated by the firmware at boot time.
>
> Sensors of inte
On Mon, Apr 10, 2017 at 03:56:52PM +0200, Cédric Le Goater wrote:
> The firmware (skiboot) chooses the default LPC bus of a multichip
> systems using a "primary" property. The LPC bus of chip 0 should be
> the only connected in the system. Let's advertise it in the device
> tree.
>
> Signed-off-by
On Mon, Apr 10, 2017 at 03:56:51PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> It adds the Naples chip which supports proper LPC interrupts via the
> LPC controller rather than via an external CPLD.
>
> Signed-off-by: Benjamin Herrenschmidt
> [clg: - updated for qemu-2.9
>
On Mon, Apr 10, 2017 at 03:56:56PM +0200, Cédric Le Goater wrote:
> When an ipmi-bt device [1] is defined on the ISA bus, we need to
> populate the device tree with the object properties. Such devices are
> created with the command line options :
>
>-device ipmi-bmc-sim,id=bmc0 -device isa-ipm
Hi Eric,
On 04/10/2017 10:17 PM, Eric Blake wrote:
For the 'alloc' command, accepting an offset in bytes but a length
in sectors, and reporting output in sectors, is confusing. Do
everything in bytes, and adjust the expected output accordingly.
Signed-off-by: Eric Blake
---
qemu-io-cmds.c
On Mon, Apr 10, 2017 at 03:09:50PM +0800, Peter Xu wrote:
> On Mon, Apr 10, 2017 at 02:39:22PM +1000, David Gibson wrote:
> > On Fri, Apr 07, 2017 at 06:59:07PM +0800, Peter Xu wrote:
> > > In this patch, IOMMUNotifier.{start|end} are introduced to store section
> > > information for a specific not
+ Richard Henderson
Anthony
> -Original Message-
> From: Xu, Anthony
> Sent: Tuesday, April 4, 2017 5:19 PM
> To: 'qemu-devel@nongnu.org'
> Cc: 'Paolo Bonzini' ; 'Stefan Hajnoczi'
>
> Subject: [Qemu-devel] centos 7.2 guest doesn't boot without kvmvapic in
> TCG mode
>
> I disabled kvmv
> I think this is wrong, the high copy should remain read-only or pflash
> stops working when you remove PAM.
I tried to set pc.bios as read-only and isa.bios as read&write,
it doesn't work. render_memory_region doesn't honor readonly
field of alias MemoryRegion.
Two FlatRanges created for pc.bi
> On 08/04/2017 08:45, Anthony Xu wrote:
> > split PAM SMRAM functions in piix.c
> > create mch_init_pam in q35.c
>
> Could you further move
>
> MemoryRegion *ram_memory;
> MemoryRegion *system_memory;
> MemoryRegion *pci_address_space;
> PAMMemoryRegion pam_regions[13];
>
> from
On Tue, Apr 11, 2017 at 12:00 AM, Stefan Hajnoczi wrote:
> On Sun, Apr 09, 2017 at 08:37:40PM +0800, jemmy858...@gmail.com wrote:
>> From: Lidong Chen
>>
>> BLOCK_SIZE is (1 << 20), qcow2 cluster size is 65536 by default,
>> this maybe cause the qcow2 file size is bigger after migration.
>> This
Passing a byte offset, but sector count, when we ultimately
want to operate on cluster granularity, is madness. Clean up
the external interfaces to take both offset and count as bytes,
while still keeping the assertion added previously that the
caller must align the values to a cluster. Then rena
Quoting Philippe Mathieu-Daudé (2017-04-07 17:20:15)
> static code analyzer complain:
>
> qga/commands-posix.c:2127:9: warning: Null pointer passed as an argument to a
> 'nonnull' parameter
> closedir(dp);
> ^~~~
>
> Reported-by: Clang Static Analyzer
> Signed-off-by: Phi
Use blkdebug's new geometry constraints to emulate setups that
have caused recent regression fixes: write zeroes asserting
when running through a loopback block device with max-transfer
smaller than cluster size, and discard rounding away portions
of requests not aligned to preferred boundaries. A
Quoting Philippe Mathieu-Daudé (2017-04-07 17:20:16)
> Suggested-by: Michael Roth
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael Roth
> ---
>
> Michael should I use Signed-off-by instead of the Suggested-by (since it is
> your
> code)?
I suppose it could go either way dependin
For the 'alloc' command, accepting an offset in bytes but a length
in sectors, and reporting output in sectors, is confusing. Do
everything in bytes, and adjust the expected output accordingly.
Signed-off-by: Eric Blake
---
qemu-io-cmds.c| 30 ++
Commits 04ed95f4 and 1a62d0ac updated the block layer to auto-fragment
any I/O to fit within device boundaries. Additionally, when using a
minimum alignment of 4k, we want to ensure the block layer does proper
read-modify-write rather than requesting I/O on a slice of a sector.
Let's enforce that t
Make it easier to simulate various unusual hardware setups (for
example, recent commits 3482b9b and b8d0a98 affect the Dell
Equallogic iSCSI with its 15M preferred and maximum unmap and
write zero sizing, or b2f95fe deals with the Linux loopback
block device having a max_transfer of 64k), by allowi
In order to test the effects of artificial geometry constraints
on operations like write zero or discard, we first need blkdebug
to manage these actions. It also allows us to inject errors on
those operations, just like we can for read/write/flush.
We can also test the contract promised by the bl
We already audited (in commit 0c1bd469) that qcow2_discard_clusters()
is only passed cluster-aligned start values; but we can further
tighten the assertion that the only unaligned end value is at EOF.
Recent commits have taken advantage of an unaligned tail cluster,
for both discard and write zero
Rather than repeat the logic at each caller of checking if a Rule
exists that warrants an error injection, fold that logic into
inject_error(); and rename it to rule_check() for legibility.
This will help the next patch, which adds two more callers that
need to check rules for the potential of inje
We've already improved discards to operate efficiently on the tail
of an unaligned qcow2 image; it's time to make a similar improvement
to write zeroes. The special case is only valid at the tail
cluster of a file, where we must recognize that any sectors beyond
the image end would implicitly read
Rather than store into a local variable, then copy to the struct
if the value is valid, then reporting errors otherwise, it is
simpler to just store into the struct and report errors if the
value is invalid. This however requires that the struct store
a 64-bit number, rather than a narrower type.
Mixing byte offset and sector allocation counts is a bit
confusing. Also, reporting n/m sectors, where m decreases
according to the remaining size of the file, isn't really
adding any useful information. Update the output to use
byte counts, and adjust the affected tests (./check -qcow2 102,
./ch
No tests were covering write zeroes with unmap. Additionally,
I wanted to prove that my patch to optimize write zeroes for
compat=0.10 images actually had an impact; for that, run:
./check -qcow2 -o compat=0.10 179
Writing the test to work correctly for both old and new qcow2
images is a bit tric
'qemu-img map' already coalesces information about unallocated
clusters (those with status 0) and pure zero clusters (those
with status BDRV_BLOCK_ZERO and no offset). Furthermore, all
qcow2 images with no backing file already report all unallocated
clusters (in the preallocation sense of clusters
Available as a tag at:
git fetch git://repo.or.cz/qemu/ericb.git nbd-blkdebug-v9
Prerequisite: Max's block-next tree:
https://lists.gnu.org/archive/html/qemu-devel/2017-04/msg01298.html
v6 was:
https://lists.gnu.org/archive/html/qemu-devel/2017-03/msg01562.html
v7 and v8 were the first half of v6
On 2017/4/10 23:01, Eric Blake wrote:
> On 04/10/2017 03:59 AM, Longpeng(Mike) wrote:
>> Refactors the qcrypto_cipher_free(), splits it into two parts. One
>> is gcrypt/nettle__cipher_free_ctx() to free the special context.
>
> Your mail forgot to include 'In-Reply-To:' and 'References:' header
> I think we shouldn't read it like that. It seems that KVM is always
> returning the VAPIC capability except when the CPU is providing a
> special acceleration [0].
>
> I would say you can't really refer yourself at this bit to enable or
> not kvmapic in QEMU.
>
> Does that make sense?
>
> [0
Read the correct descriptor instead of hardcoding the first (q=0).
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/net/cadence_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cade
Expose the Cadence GEM revision as a property.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/net/cadence_gem.c | 6 +-
include/hw/net/cadence_gem.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/net/c
Correct the buffer descriptor busy logic to work correctly when using
multiple queues.
Signed-off-by: Alistair Francis
---
hw/net/cadence_gem.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 17c229d..a66a9
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-zynqmp.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index bc4e66b..e41b6fe 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -30,6 +
This patch fixes two mistakes in the interrupt logic.
First we only trigger single-queue or multi-queue interrupts if the status
register is set. This logic was already used for non multi-queue interrupts
but it also applies to multi-queue interrupts.
Secondly we need to lower the interrupts if t
Improve the Cadence GEM multi-queue support. This fixes a few bugs
which were hanging around from the initial implementation.
V2:
- Fix up the interrupt updating logic and consolidate all the updates
to a single function.
- Improve the debug print information
Alistair Francis (5):
cadence_
On Mon, Apr 10, 2017 at 5:44 AM, Peter Maydell wrote:
> On 5 April 2017 at 00:40, Alistair Francis
> wrote:
>> Only trigger multi-queue GEM interrupts if the interrupt status register
>> is set. This logic was already used for non multi-queue interrupts but
>> it also applies to multi-queue inte
** Changed in: qemu
Assignee: (unassigned) => John Snow (jnsnow)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1681439
Title:
qemu-system-x86_64: hw/ide/core.c:685: ide_cancel_dma_sync: Assert
On Mon, 10 Apr 2017 10:49:12 -0700
Richard Henderson wrote:
> On 04/10/2017 10:44 AM, Greg Kurz wrote:
> > On Mon, 10 Apr 2017 18:29:57 +0100
> > Peter Maydell wrote:
> >
> >> On 10 April 2017 at 18:26, Richard Henderson wrote:
> >>> On 04/09/2017 11:06 PM, Nikunj A Dadhania wrote:
>
On 02/17/2017 02:51 PM, Dr. David Alan Gilbert wrote:
> * Fam Zheng (f...@redhat.com) wrote:
>> On Fri, 02/17 16:36, Vladimir Sementsov-Ogievskiy wrote:
>>> 17.02.2017 15:21, Fam Zheng wrote:
On Fri, 02/17 13:20, Vladimir Sementsov-Ogievskiy wrote:
> 16.02.2017 16:48, Fam Zheng wrote:
>>
I don't think the assert you are talking about in the subject is added
by 9972354856. That assertion was added by 86698a12f and has been
present since QEMU 2.6. I don't see the relation immediately to
AioContext patches.
Is this only during boot/shutdown? If not, it looks like there might be
some
On 04/10/2017 12:14 PM, Stefan Berger wrote:
On 04/10/2017 06:07 AM, Patrick Ohly wrote:
On Mon, 2017-04-10 at 09:54 +, Marc-André Lureau wrote:
By "public protocol", I mean qemu communication with a foreign
project, swtpm or other.
If qemu grows new needs, or if the protocol is found lim
On Mon, Apr 10, 2017 at 5:37 AM, Peter Maydell wrote:
> On 5 April 2017 at 00:40, Alistair Francis
> wrote:
>> Correct the buffer descriptor busy logic to work correctly when using
>> multiple queues.
>>
>> Signed-off-by: Alistair Francis
>> ---
>>
>> hw/net/cadence_gem.c | 18 +++-
On Mon, Apr 10, 2017 at 05:28:44PM +0200, Laszlo Ersek wrote:
> On 04/10/17 17:03, Ard Biesheuvel wrote:
> > At the request of Michael, replace the leading capital X in the FADT
> > field name Xfacs and Xdsdt with lower case x + underscore.
> >
> > Cc: Michael S. Tsirkin
> > Signed-off-by: Ard Bi
Hello,
A very basic question...
In a vanilla KVM env. (i.e. non open stack etc) when a VM is live migrated
to another host does the MAC address of the vNICs and the DHCP IP address
for these interfaces remain the same ?
Thought the answer was a yes as the goal is to minimize disruption to the
a
On Mon, 10 Apr 2017, Stefano Stabellini wrote:
> On Mon, 10 Apr 2017, hrg wrote:
> > On Sun, Apr 9, 2017 at 11:55 PM, hrg wrote:
> > > On Sun, Apr 9, 2017 at 11:52 PM, hrg wrote:
> > >> Hi,
> > >>
> > >> In xen_map_cache_unlocked(), map to guest memory maybe in entry->next
> > >> instead of first
On Wed, Apr 05, 2017 at 02:41:43PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> This adds a devfn_max field to PCIBus and adds a pci_can_add_device()
> function which, if no "addr" (aka devfn) is specified, will tell whether
> there is any slot free between devfn_min and devf
On 03/23/2017 01:39 PM, Paolo Bonzini wrote:
> This splits the part that touches job states from the part that invokes
> callbacks. It will be a bit simpler to understand once job states will
> be protected by a different mutex than the AioContext lock.
>
> Signed-off-by: Paolo Bonzini
> ---
>
On Mon, 10 Apr 2017, hrg wrote:
> On Sun, Apr 9, 2017 at 11:55 PM, hrg wrote:
> > On Sun, Apr 9, 2017 at 11:52 PM, hrg wrote:
> >> Hi,
> >>
> >> In xen_map_cache_unlocked(), map to guest memory maybe in entry->next
> >> instead of first level entry (if map to rom other than guest memory
> >> come
On 04/10/2017 02:13 PM, Peter Maydell wrote:
We now test for "are we singlestepping" in several places and
it's not a trivial check because we need to care about both
architectural singlestep and QEMU gdbstub singlestep. We're
also about to add another place that needs to make this check,
so pull
On 04/10/2017 10:44 AM, Greg Kurz wrote:
On Mon, 10 Apr 2017 18:29:57 +0100
Peter Maydell wrote:
On 10 April 2017 at 18:26, Richard Henderson wrote:
On 04/09/2017 11:06 PM, Nikunj A Dadhania wrote:
--- a/cpus.c
+++ b/cpus.c
@@ -202,7 +202,7 @@ void qemu_tcg_configure(QemuOpts *opts, Error *
On Mon, 10 Apr 2017 18:29:57 +0100
Peter Maydell wrote:
> On 10 April 2017 at 18:26, Richard Henderson wrote:
> > On 04/09/2017 11:06 PM, Nikunj A Dadhania wrote:
> >> --- a/cpus.c
> >> +++ b/cpus.c
> >> @@ -202,7 +202,7 @@ void qemu_tcg_configure(QemuOpts *opts, Error **errp)
> >>
We currently have two places that do:
if (dc->ss_active) {
gen_step_complete_exception(dc);
} else {
gen_exception_internal(EXCP_DEBUG);
}
Factor this out into its own function, as we're about to add
a third place that needs the s
Now that we've rewritten M-profile exception return so that the magic
PC values are not visible to other parts of QEMU, we can delete the
special casing of them elsewhere.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 43 ++
We now test for "are we singlestepping" in several places and
it's not a trivial check because we need to care about both
architectural singlestep and QEMU gdbstub singlestep. We're
also about to add another place that needs to make this check,
so pull the condition out into a function.
Signed-off
Move the code to generate the "condition failed" instruction
codepath out of the if (singlestepping) {} else {}. This
will allow adding support for handling a new is_jmp type
which can't be neatly split into "singlestepping case"
versus "not singlestepping case".
Signed-off-by: Peter Maydell
Revi
On M profile, return from exceptions happen when code in Handler mode
executes one of the following function call return instructions:
* POP or LDM which loads the PC
* LDR to PC
* BX register
and the new PC value is 0xFFxx.
QEMU tries to implement this by not treating the instruction
speci
For M-profile CPUs, the BXJ instruction does not exist at all, and
the encoding should always UNDEF. We were accidentally implementing
it to behave like A-profile BXJ; correct the error.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/translate.c | 7 ++-
1 f
Move the utility routines gen_set_condexec() and gen_set_pc_im()
up in the file, as we will want to use them from a function
placed earlier in the file than their current location.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/translate.c | 31 +++--
In Thumb mode, the only instructions which can cause an interworking
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
ARM mode, data processing instructions which target the PC do not
cause interworking branches.
When we added support for doing interworking branches on writes to
On 04/10/2017 10:29 AM, Peter Maydell wrote:
On 10 April 2017 at 18:26, Richard Henderson wrote:
On 04/09/2017 11:06 PM, Nikunj A Dadhania wrote:
--- a/cpus.c
+++ b/cpus.c
@@ -202,7 +202,7 @@ void qemu_tcg_configure(QemuOpts *opts, Error **errp)
} else if (use_icount) {
On 10 April 2017 at 18:26, Richard Henderson wrote:
> On 04/09/2017 11:06 PM, Nikunj A Dadhania wrote:
>> --- a/cpus.c
>> +++ b/cpus.c
>> @@ -202,7 +202,7 @@ void qemu_tcg_configure(QemuOpts *opts, Error **errp)
>> } else if (use_icount) {
>> error_setg(errp, "No MTTC
On 04/09/2017 11:06 PM, Nikunj A Dadhania wrote:
While the configure script generates TARGET_SUPPORTS_MTTCG define, one
of the define is cpus.c is checking wrong name: TARGET_SUPPORT_MTTCG
Signed-off-by: Nikunj A Dadhania
---
cpus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
> From: Andrew Baumann
> Sent: Monday, 10 April 2017 10:05
> > From: Omar Rizwan [mailto:omar.riz...@gmail.com]
> > Sent: Friday, 7 April 2017 23:13
> > I can't easily find documentation for that 0x4000 memory mapping,
> > which I figured I'd keep in; should it just be removed from bcm2835?
>
> From: Omar Rizwan [mailto:omar.riz...@gmail.com]
> Sent: Friday, 7 April 2017 23:13
> On Fri, Apr 7, 2017 at 10:57 PM Andrew Baumann
> wrote:
> > > From: Omar Rizwan [mailto:omar.riz...@gmail.com]
> > > Sent: Friday, 7 April 2017 22:43
> > Did you do any testing of this? One of the reasons I ne
Cédric Le Goater writes:
> On 04/07/2017 08:07 AM, Cédric Le Goater wrote:
>> On 04/07/2017 07:24 AM, Nikunj A Dadhania wrote:
>>> Cédric Le Goater writes:
>>>
Hello Nikunj,
On 04/06/2017 12:22 PM, Nikunj A Dadhania wrote:
> The series enables Multi-Threaded TCG on PPC64
On M profile, return from exceptions happen when code in Handler mode
executes one of the following function call return instructions:
* POP or LDM which loads the PC
* LDR to PC
* BX register
and the new PC value is 0xFFxx.
QEMU tries to implement this by not treating the i
For M profile exception-return handling we'd like to generate different
code for some instructions depending on whether we are in Handler
mode or Thread mode. This isn't the same as "are we privileged
or user", so we need an extra bit in the TB flags to distinguish.
Signed-off-by: Peter Maydell
-
Cédric Le Goater writes:
> On 04/10/2017 06:44 PM, Nikunj A Dadhania wrote:
>> Cédric Le Goater writes:
>>
>>> On 04/07/2017 08:07 AM, Cédric Le Goater wrote:
On 04/07/2017 07:24 AM, Nikunj A Dadhania wrote:
> Cédric Le Goater writes:
sure. pnv is still on 2.9, so I will reb
On 04/10/2017 06:44 PM, Nikunj A Dadhania wrote:
> Cédric Le Goater writes:
>
>> On 04/07/2017 08:07 AM, Cédric Le Goater wrote:
>>> On 04/07/2017 07:24 AM, Nikunj A Dadhania wrote:
Cédric Le Goater writes:
> Hello Nikunj,
>
> On 04/06/2017 12:22 PM, Nikunj A Dadhania wrote
On 10 April 2017 at 14:22, Philippe Mathieu-Daudé wrote:
> I'm custom to think "let's change that and think how to protect the code to
> help the next one who will modify it" and wonder if it isn't safer to
> define:
>
> const bool singlestepping;
>
> singlestepping = cs->singlestep_enabled || dc-
Cédric Le Goater writes:
> On 04/07/2017 08:07 AM, Cédric Le Goater wrote:
>> On 04/07/2017 07:24 AM, Nikunj A Dadhania wrote:
>>> Cédric Le Goater writes:
>>>
Hello Nikunj,
On 04/06/2017 12:22 PM, Nikunj A Dadhania wrote:
> The series enables Multi-Threaded TCG on PPC64
>
On 04/07/2017 08:07 AM, Cédric Le Goater wrote:
> On 04/07/2017 07:24 AM, Nikunj A Dadhania wrote:
>> Cédric Le Goater writes:
>>
>>> Hello Nikunj,
>>>
>>> On 04/06/2017 12:22 PM, Nikunj A Dadhania wrote:
The series enables Multi-Threaded TCG on PPC64
Patch 01: Use atomic_cmpxchg in
Hello,
On 03/18/2017 02:27 AM, Mike Kravetz wrote:
On 03/15/2017 06:47 AM, Alexey Perevalov wrote:
Hi Andrea,
thank you for so perfect design description,
the main question who will do RFC patches,
you or Mike or if you not against I could try.
Sorry for not replying sooner, I have been aw
On 10 April 2017 at 11:39, Peter Maydell wrote:
> On M profile, return from exceptions happen when privileged code
> executes one of the following function call return instructions:
> * POP or LDM which loads the PC
> * LDR to PC
> * BX register
> and the new PC value is 0xFFxx.
So this is
That patch is wrong. The correct patch has been submitted and checked
on the QEMU mailing lists
(http://patchwork.ozlabs.org/patch/737446/).
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1670509
Ti
On 04/10/2017 03:08 AM, Amarnath Valluri wrote:
On 07.04.2017 17:41, Daniel P. Berrange wrote:
On Fri, Apr 07, 2017 at 05:30:31PM +0300, Amarnath Valluri wrote:
This change introduces a new TPM backend driver that can communicate
with
swtpm(software TPM emulator) using unix domain socket int
On 04/10/2017 06:07 AM, Patrick Ohly wrote:
On Mon, 2017-04-10 at 09:54 +, Marc-André Lureau wrote:
By "public protocol", I mean qemu communication with a foreign
project, swtpm or other.
If qemu grows new needs, or if the protocol is found limited or buggy,
it may change. Subtle interacti
On 04/08/2017 05:52 AM, Paolo Bonzini wrote:
>
>
> On 08/04/2017 08:03, John Snow wrote:
>> Looks clean, though it may be useful to do a few more things;
>>
>> - Demarcate what you think is the monitor API in this file
>
> It's already there:
>
> +/*
> + * API for block job drivers and the bl
Just to clarify: the issue appeared in 2.8.0, but it is still present in
current master. Commit c2b6428d38 ("block: quiesce AioContext when
detaching from it") does not solve this issue, even though it contains
the following tag:
Fixes: 99723548561978da8ef44cf804fb7912698f5d88
--
You receiv
Public bug reported:
Since upgrading to QEMU 2.8.0, my Windows 7 64-bit virtual machines
started crashing due to the assertion quoted in the summary failing.
The assertion in question was added by commit 9972354856 ("block: add
BDS field to count in-flight requests"). My tests show that setting
d
On Mon, Apr 10, 2017 at 10:26:34AM +0800, Fam Zheng wrote:
> v3: Use bdrv_parent_drained_begin/end. [Kevin]
> Do it before releasing new_context. [Stefan]
>
> Fam Zheng (2):
> block: Make bdrv_parent_drained_begin/end public
> block: Quiesce old aio context during bdrv_set_aio_context
>
>
1 - 100 of 283 matches
Mail list logo
