Dear QEMU developers,
I am a student working on the host-guest interaction for a Windows Host and
Linux Quest. Actually, I aim to make a universal pipe implementation for
any host-guest interaction.
I am now using a serial port to redirect to a pipe. This is working with
LInux host and Linux gues
On Thu, 23 Feb 2017 13:11:52 +1100
David Gibson wrote:
> On Wed, Feb 22, 2017 at 12:08:25PM +0100, Greg Kurz wrote:
> > David,
> >
> > I don't see the "spapr_pci: Allow PCI-Express devices" patch in your
> > ppc-for-2.9 tree. Do you still consider merging it ?
>
> No. After discussions with
> Apart from that I'm pretty happy with the endpoint you reach. I'm a
> bit less convinced about the path taken to get there. I'm not sure if
> it's worth the churn of doing this reorg, but I think we'd get there
> more clearly and with less intermediate abstraction violations if it
> was done by
We can call this qmp command to do checkpoint outside of qemu.
Xen colo will need this function.
Signed-off-by: Zhang Chen
Signed-off-by: Wen Congyang
Reviewed-by: Eric Blake
---
migration/colo.c | 23 +++
qapi-schema.json | 48 +
We can call this qmp command to start/stop replication outside of qemu.
Like Xen colo need this function.
Signed-off-by: Zhang Chen
Signed-off-by: Wen Congyang
Reviewed-by: Eric Blake
Reviewed-by: Stefano Stabellini
Reviewed-by: zhanghailiang
---
migration/colo.c | 23 ++
Xen COLO depend on qemu COLO replication function.
So, We need new qmp commands for Xen to use qemu replication.
Corresponding libxl patches already in xen.git.
Commit ID:
ed37ef1f91c20f0ab162ce60f8c38400b917fa64
COLO: introduce new API to prepare/start/do/get_error/stop replication
a0ddc0b35937
David Gibson writes:
> -static void gen_read_xer(TCGv dst)
>> +static void gen_read_xer(DisasContext *ctx, TCGv dst)
>> {
>> TCGv t0 = tcg_temp_new();
>> TCGv t1 = tcg_temp_new();
>> @@ -3715,15 +3719,30 @@ static void gen_read_xer(TCGv dst)
>> tcg_gen_or_tl(t0, t0, t1);
>> t
On 02/23/2017 04:07 AM, David Gibson wrote:
>> FYI, the xics-cleanup branch has some issue with migration :
>>
>> qemu-system-ppc64: VQ 0 size 0x80 < last_avail_idx 0x9f9 - used_idx 0x0
>> qemu-system-ppc64: Failed to load virtio-blk:virtio
>> qemu-system-ppc64: error while loading state for instan
Richard Henderson writes:
> Bah. Hit return too soon...
>
> On 02/22/2017 10:44 PM, Nikunj A Dadhania wrote:
>> -static void gen_read_xer(TCGv dst)
>> +static void gen_read_xer(DisasContext *ctx, TCGv dst)
>> {
>> TCGv t0 = tcg_temp_new();
>> TCGv t1 = tcg_temp_new();
>> @@ -3715,15 +
On Thu, 2017-02-23 at 13:09 +1100, David Gibson wrote:
> The pseries machine type implements the behaviour of a PAPR compliant
> hypervisor, without actually executing such a hypervisor on the
> virtual
> CPU. To do this we need some hooks in the CPU code to make
> hypervisor
> facilities get redi
Updated against Paul's kvm-ppc-next tree:
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc.git
... at commit:
5982f0849e08fe4e4e7df5e345c4539ce9780b1b
... in order to provide some new definitions needed by ISA 3.00
guests.
This is a large change because it is the first import since
som
For a little while around 4.9, Linux kernels that saw the radix bit in
ibm,pa-features would attempt to set up the MMU as if they were a
hypervisor, even if they were a guest, which would cause them to
crash.
Work around this by detecting pre-ISA 3.0 guests by their lack of that
bit in option vect
Add the new node, /chosen/ibm,arch-vec-5-platform-support to the
device tree. This allows the guest to determine which modes are
supported by the hypervisor.
Update the option vector processing in h_client_architecture_support()
to handle the new MMU bits. This allows guests to request hash or
rad
On 02/22/2017 11:23 PM, Eric Blake wrote:
On 02/22/2017 01:54 AM, Zhang Chen wrote:
if (err) {
result->status = REPLICATION_STATUS_ERROR;
result->has_desc = true;
result->desc = ...extract string from err
} else {
result->status = REPLICATION_STATUS_NORMAL;
}
by modifying the
Query and cache the value of two new KVM capabilities that indicate
KVM's support for new radix and hash modes of the MMU.
Signed-off-by: Sam Bobroff
---
v2:
* cap_mmu_hash renamed to cap_mmu_hash_v3.
target/ppc/kvm.c | 14 ++
target/ppc/kvm_ppc.h | 12
2 files cha
In the next patch, spapr_fixup_cpu_dt() will need to call
spapr_populate_pa_features() so move it's definition up without making
any other changes.
Signed-off-by: Sam Bobroff
---
hw/ppc/spapr.c | 86 +-
1 file changed, 43 insertions(+), 43
The PPC MMU types are sometimes treated as if they were a bit field
and sometime as if they were an enum which causes maintenance
problems: flipping bits in the MMU type (which is done on both the 1TB
segment and 64K segment bits) currently produces new MMU type
values that are not handled in every
Both radix and hash modes require guests to use
h_register_process_table() to set up the MMU. Implement it using the
new KVM ioctl KVM_PPC_CONFIGURE_V3_MMU.
This hypercall is also necessary for fully emulated guests, so it will
need to be reworked to integrate with Suraj's TCG patchset.
---
v2:
*
If QEMU is using KVM, and KVM is capable of running in radix mode,
guests can be run in real-mode without allocating a HPT (because KVM
will use a minimal RPT). So in this case, we avoid creating the HPT
at reset time and later (during CAS) create it if it is necessary.
Signed-off-by: Sam Bobroff
Use the new ioctl, KVM_PPC_GET_RMMU_INFO, to fetch radix MMU
information from KVM and present the page encodings in the device tree
under ibm,processor-radix-AP-encodings. This provides page size
information to the guest which is necessary for it to use radix mode.
Signed-off-by: Sam Bobroff
---
Currently, running update-linux-headers.sh will produce a patch that
deletes virtio_mmio.h, which is still needed. This happens because
virtio_mmio.h is in the directory used to store headers from the linux
kernel that are copied by the kernel's "make headers_install" target
(used by the update scr
The kernel has added some new headers for ARM, so add these so that
the script can be run successfully.
Signed-off-by: Sam Bobroff
---
v2:
* Added the two new arm headers.
scripts/update-linux-headers.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/update-linux-headers.sh b/scri
Update notes:
Since the last version, there has been a change to specification of the values
used during client architecture support, regarding the bits in option vector 5,
so some bits and other processing have changed a bit.
This version has not been as well tested as the last. Testing is ongo
Refactor the architecture specific code to make it easier
to add new special case files.
There should be no change in functionality.
Signed-off-by: Sam Bobroff
---
v2:
I've factored the script to make it easier to add new files.
scripts/update-linux-headers.sh | 25 +++--
On Thu, 2017-02-23 at 13:09 +1100, David Gibson wrote:
> CPUPPCState includes fields htab_base and htab_mask which store the
> base
> address (GPA) and size (as a mask) of the guest's hashed page table
> (HPT).
> These are set when the SDR1 register is updated.
>
> Keeping these in sync with the S
On 02/23/2017 09:02 AM, Hailiang Zhang wrote:
Hi,
On 2017/2/22 17:31, Zhang Chen wrote:
On 02/22/2017 11:42 AM, zhanghailiang wrote:
While do checkpoint, we need to flush all the unhandled packets,
By using the filter notifier mechanism, we can easily to notify
every compare object to do t
On 23/02/17 13:09, David Gibson wrote:
> CPUPPCState includes fields htab_base and htab_mask which store the base
> address (GPA) and size (as a mask) of the guest's hashed page table (HPT).
> These are set when the SDR1 register is updated.
>
> Keeping these in sync with the SDR1 is actually a li
On Wed, Feb 22, 2017 at 08:24:51PM -0700, Alex Williamson wrote:
[...]
> > Now Jintack reported another issue, that we may have two default
> > devices there if not specifying "-nodefaults", and that two devices
> > will always be the first ones to be inited.
> >
> > How about here we just expli
On Thu, 2017-02-23 at 13:09 +1100, David Gibson wrote:
> Accesses to the hashed page table (HPT) are complicated by the fact
> that
> the HPT could be in one of three places:
> 1) Within guest memory - when we're emulating a full guest CPU at
> the
> hardware level (e.g. powernv, mac99, g3
On Thu, Feb 23, 2017 at 10:39:47AM +0530, Nikunj A Dadhania wrote:
> David Gibson writes:
> >>
> >> diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
> >> index de3004b..89c1ccb 100644
> >> --- a/target/ppc/cpu.c
> >> +++ b/target/ppc/cpu.c
> >> @@ -23,8 +23,15 @@
> >>
> >> target_ulong cpu_rea
On Thu, Feb 23, 2017 at 04:02:54PM +1100, Alexey Kardashevskiy wrote:
> On 23/02/17 13:09, David Gibson wrote:
> > Accesses to the hashed page table (HPT) are complicated by the fact that
> > the HPT could be in one of three places:
> >1) Within guest memory - when we're emulating a full guest
On Thu, Feb 23, 2017 at 03:32:04PM +1100, Suraj Jitindar Singh wrote:
> On Thu, 2017-02-23 at 13:09 +1100, David Gibson wrote:
> > At present the SDR1 register - the base of the system's hashed page
> > table
> > (HPT) - is represented as an SPR with supervisor read and write
> > permission.
> > Ho
David Gibson writes:
>>
>> diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
>> index de3004b..89c1ccb 100644
>> --- a/target/ppc/cpu.c
>> +++ b/target/ppc/cpu.c
>> @@ -23,8 +23,15 @@
>>
>> target_ulong cpu_read_xer(CPUPPCState *env)
>> {
>> -return env->xer | (env->so << XER_SO) | (env->o
On 23/02/17 13:09, David Gibson wrote:
> Accesses to the hashed page table (HPT) are complicated by the fact that
> the HPT could be in one of three places:
>1) Within guest memory - when we're emulating a full guest CPU at the
> hardware level (e.g. powernv, mac99, g3beige)
>2) Withi
Richard Henderson writes:
> On 02/22/2017 10:44 PM, Nikunj A Dadhania wrote:
>> * SO and OV reflects overflow of the 64-bit result in 64-bit mode and
>> overflow of the low-order 32-bit result in 32-bit mode
>>
>> * OV32 reflects overflow of the low-order 32-bit independent of the mode
>>
>> Si
On Thu, 2017-02-23 at 13:09 +1100, David Gibson wrote:
> At present the SDR1 register - the base of the system's hashed page
> table
> (HPT) - is represented as an SPR with supervisor read and write
> permission.
> However, on CPUs which have a hypervisor mode, the SDR1 is a
> hypervisor
> only res
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1652333
Title:
TCG mode fa
On Thu, 2017-02-23 at 13:09 +1100, David Gibson wrote:
> cpu_ppc_set_papr() sets up various aspects of CPU state for use with
> PAPR
> paravirtualized guests. However, it doesn't set the virtual
> hypervisor,
> so callers must also call cpu_ppc_set_vhyp() so that PAPR hypercalls
> are
> handled pr
On Thu, 2017-02-23 at 15:08 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 03:04:35PM +1100, Suraj Jitindar Singh wrote:
> >
> > Add a new mmu fault handler for the POWER9 cpu and add it as the
> > handler
> > for the POWER9 cpu definition.
> >
> > This handler checks if the guest is radix
On Thu, 2017-02-23 at 14:50 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 03:04:33PM +1100, Suraj Jitindar Singh wrote:
> >
> > ISA v3.00 adds the idea of a partition table which is used to store
> > the
> > address translation details for all partitions on the system. The
> > partition
> >
On Thu, 2017-02-23 at 14:47 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 06:31:46PM +1100, Balbir Singh wrote:
> >
> > On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh
> > wrote:
> > >
> > > The logical partitioning control register controls a threads
> > > operation
> > > b
On Thu, 2017-02-23 at 14:43 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 04:16:26PM +1100, Balbir Singh wrote:
> >
> > On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh
> > wrote:
> > >
> > > POWER9 processors implement the mmu as defined in version 3.00 of
> > > the ISA.
> >
On 21/02/17 17:46, Yongji Xie wrote:
> At the moment ram device's memory regions are NATIVE_ENDIAN. This does
> not work on PPC64 because VFIO PCI device is little endian but PPC64
> always defines static macro TARGET_WORDS_BIGENDIAN.
>
> This fixes endianness for ram device the same way as it is
On 2017年02月22日 16:51, Hailiang Zhang wrote:
On 2017/2/22 16:45, Hailiang Zhang wrote:
On 2017/2/22 16:07, Jason Wang wrote:
On 2017年02月22日 11:46, zhanghailiang wrote:
After a net connection is closed, we didn't clear its releated
resources
in connection_track_table, which will lead to mem
On Mon, Feb 20, 2017 at 03:04:35PM +1100, Suraj Jitindar Singh wrote:
> Add a new mmu fault handler for the POWER9 cpu and add it as the handler
> for the POWER9 cpu definition.
>
> This handler checks if the guest is radix or hash based on the value in the
> partition table entry and calls the co
On Mon, Feb 20, 2017 at 03:04:28PM +1100, Suraj Jitindar Singh wrote:
> This is V3 of the patch series to implement tcg emulation support for a
> POWER9 cpu model for the pseries machine type running a legacy kernel.
> That is a kernel which doesn't use the new radix mmu mode or the new hash
> mmu
On Thu, 2017-02-23 at 13:09 +1100, David Gibson wrote:
> * Standardize on 'ptex' instead of 'pte_index' for HPTE index
> variables
> for consistency and brevity
> * Avoid variables named 'index'; shadowing index(3) from libc can
> lead to
> surprising bugs if the variable is removed, becaus
On Wed, Feb 22, 2017 at 04:43:37PM -0600, Eric Blake wrote:
> On 02/22/2017 01:26 PM, Eduardo Habkost wrote:
> > The "hotplugged" property is user visible, but it was never meant
> > to be set by the user. There are probably multiple ways to break
> > or crash device code by overriding the property
On Mon, Feb 20, 2017 at 03:04:34PM +1100, Suraj Jitindar Singh wrote:
> POWER9 doesn't have a storage description register 1 (SDR1) which is used
> to store the base and size of the hash table. Thus we don't need to
> generate this register on the POWER9 cpu model and thus shouldn't read or
> write
On Mon, Feb 20, 2017 at 04:16:26PM +1100, Balbir Singh wrote:
> On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh wrote:
> > POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
> >
> > Add a definition for this mmu model and set the POWER9 cpu model to use
> > t
On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh wrote:
> The logical partitioning control register controls a threads operation
> based on the partition it is currently executing. Add new definitions and
> update the mask used when writing to the LPCR based on the POWER9 spec.
>
> S
On Mon, Feb 20, 2017 at 03:04:33PM +1100, Suraj Jitindar Singh wrote:
> ISA v3.00 adds the idea of a partition table which is used to store the
> address translation details for all partitions on the system. The partition
> table consists of double word entries indexed by partition id where the sec
On Mon, Feb 20, 2017 at 06:31:46PM +1100, Balbir Singh wrote:
> On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh wrote:
> > The logical partitioning control register controls a threads operation
> > based on the partition it is currently executing. Add new definitions and
> > update t
On Wed, Feb 22, 2017 at 05:14:33PM +0530, Nikunj A Dadhania wrote:
> This series contains implentation of CA32 and OV32 bits added to the
> ISA 3.0. Various fixed-point arithmetic instructions are updated to take
> care of the newer flags.
>
> Finally the last patch adds new instruction mcrxrx,
On Wed, Feb 22, 2017 at 05:14:36PM +0530, Nikunj A Dadhania wrote:
> POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
> and corresponding defines.
>
> Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
> is updated.
>
> Arithmetic instructions:
> * A
On Thu, 23 Feb 2017 11:06:47 +0800
Peter Xu wrote:
> On Wed, Feb 22, 2017 at 10:30:47AM -0700, Alex Williamson wrote:
> > On Wed, 22 Feb 2017 13:49:25 +0800
> > Peter Xu wrote:
> >
> > > Intel vIOMMU devices are created with "-device" parameter, while here
> > > actually we need to make sure
On Thu, Feb 16, 2017 at 02:47:35PM +0100, Cédric Le Goater wrote:
> Let's add two new handlers for ICPs. One is to get an ICP object from
> a server number and a second is to resend the irqs when needed.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/intc/xics.c| 2 +-
> hw/ppc/spapr.c
On Thu, Feb 16, 2017 at 02:47:27PM +0100, Cédric Le Goater wrote:
> This is, again, to reduce the use of the list of ICS objects. Let's
> make each individual ICS and ICP object an InterruptStatsProvider and
> remove this same interface from XICSState.
>
> Signed-off-by: Cédric Le Goater
I'm a l
On Wed, Feb 22, 2017 at 11:55:40AM +0100, Cédric Le Goater wrote:
> On 02/22/2017 04:34 AM, David Gibson wrote:
> > On Thu, Feb 16, 2017 at 02:47:23PM +0100, Cédric Le Goater wrote:
> >> Hello,
> >>
> >> The goal behind this series is to simplify the XICS interface by
> >> moving back in the machin
On Thu, Feb 16, 2017 at 02:47:29PM +0100, Cédric Le Goater wrote:
> Add 'ics_get' and 'ics_resend' handlers to the sPAPR machine. These
> are relatively simple for a single ICS.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
> hw/intc/xics.c| 2 +-
> hw/ppc/spapr
On Thu, Feb 16, 2017 at 02:47:30PM +0100, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
> hw/intc/xics.c | 5 +++--
> hw/ppc/spapr_events.c | 6 +++---
> hw/ppc/spapr_pci.c | 2 +-
> include/hw/pci-host/spapr.h | 2 +-
> i
On Thu, Feb 16, 2017 at 02:47:39PM +0100, Cédric Le Goater wrote:
> The reset of the ICP objects is currently handled by XICS but this can
> be done for each individual ICP.
>
> Signed-off-by: Cédric Le Goater
Hrm. I think whether device_reset() gets called automatically depends
on how the devi
On Thu, Feb 16, 2017 at 02:47:34PM +0100, Cédric Le Goater wrote:
> This is not used anymore.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
> hw/intc/xics.c| 8
> hw/ppc/spapr.c| 1 -
> include/hw/ppc/xics.h | 2 --
> 3 files changed, 11 deletion
On Thu, Feb 16, 2017 at 02:47:28PM +0100, Cédric Le Goater wrote:
> This QOM interface provides two simple handlers. One is to get an ICS
> object from an irq number and a second to resend the irqs when needed.
Maybe call this XICSFabric rather than XicsInterface. While it's an
interface from the
On Thu, Feb 16, 2017 at 02:47:33PM +0100, Cédric Le Goater wrote:
> The reset of the ICS objects is currently handled by XICS but this can
> be done for each individual ICS. This also reduces the use of the XICS
> list of ICS.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
On Thu, Feb 16, 2017 at 02:47:32PM +0100, Cédric Le Goater wrote:
> It is not used anymore now that we have the QOM interface for XICS.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Several of these patches are small enough that I wonder if they could
be merged, though.
> ---
On Thu, Feb 16, 2017 at 02:47:31PM +0100, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
> ---
> hw/intc/xics.c | 26 ++
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index 0ffdf09c5304..2decb921e4e3 1006
On Wed, Feb 22, 2017 at 10:30:47AM -0700, Alex Williamson wrote:
> On Wed, 22 Feb 2017 13:49:25 +0800
> Peter Xu wrote:
>
> > Intel vIOMMU devices are created with "-device" parameter, while here
> > actually we need to make sure this device will be created before some
> > other PCI devices (like
On Wed, Feb 22, 2017 at 08:37:32AM -0500, Jintack Lim wrote:
> On Wed, Feb 22, 2017 at 6:42 AM, Jintack Lim
> wrote:
>
> >
> >
> > On Wed, Feb 22, 2017 at 12:49 AM, Peter Xu wrote:
> >
> >> Intel vIOMMU devices are created with "-device" parameter, while here
> >> actually we need to make sure t
CPUPPCState includes fields htab_base and htab_mask which store the base
address (GPA) and size (as a mask) of the guest's hashed page table (HPT).
These are set when the SDR1 register is updated.
Keeping these in sync with the SDR1 is actually a little bit fiddly, and
probably not useful for perf
The pseries machine type implements the behaviour of a PAPR compliant
hypervisor, without actually executing such a hypervisor on the virtual
CPU. To do this we need some hooks in the CPU code to make hypervisor
facilities get redirected to the machine instead of emulated internally.
For hypercal
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emu
* Standardize on 'ptex' instead of 'pte_index' for HPTE index variables
for consistency and brevity
* Avoid variables named 'index'; shadowing index(3) from libc can lead to
surprising bugs if the variable is removed, because compiler errors
might not appear for remaining references
* C
At present the SDR1 register - the base of the system's hashed page table
(HPT) - is represented as an SPR with supervisor read and write permission.
However, on CPUs which have a hypervisor mode, the SDR1 is a hypervisor
only resource. Change the permission checking on the SPR to reflect this.
N
cpu_ppc_set_papr() sets up various aspects of CPU state for use with PAPR
paravirtualized guests. However, it doesn't set the virtual hypervisor,
so callers must also call cpu_ppc_set_vhyp() so that PAPR hypercalls are
handled properly. This is a bit silly, so fold setting the virtual
hypervisor
This series has an assortment of cleanups to the handling of the hash
based MMU for 64-bit ppc machines. In particular it better handles
the case of "external" hash table - this is used on the pseries
machine type, which being a paravirtualized platform has the hashed
page table - along with other
On 02/05/2017 10:37 AM, xiaoqiang zhao wrote:
* Split the old SysBus init into an instance_init and a
DeviceClass::realize function
* Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao
Reviewed-by: Philippe Mathieu-Daudé
---
hw/misc/eccmemctl.c | 25 ++
On 02/05/2017 10:37 AM, xiaoqiang zhao wrote:
Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao
Reviewed-by: Philippe Mathieu-Daudé
---
hw/misc/slavio_misc.c | 43 +--
1 file changed, 17 insertions(+), 26 deletion
On 02/05/2017 10:37 AM, xiaoqiang zhao wrote:
Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao
Reviewed-by: Philippe Mathieu-Daudé
---
hw/dma/sun4m_iommu.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/dma/sun4m_io
In mttcg, calling pause_all_vcpus() during execution from the
generated TBs causes a deadlock if some vCPU is waiting for exclusive
execution in start_exclusive(). Fix this by using the aync_safe_*
framework instead of pausing vcpus for patching instructions.
CC: Richard Henderson
CC: Peter Mayde
Hi Eric,
On 2017/2/22 23:35, Eric Blake wrote:
On 02/21/2017 09:42 PM, zhanghailiang wrote:
If VM is in COLO FT state, we need to do some extra works before
starting normal shutdown process.
Secondary VM will ignore the shutdown command if users issue it directly
to Secondary VM. COLO will cap
On Wed, Feb 22, 2017 at 4:02 PM, Alex Bennée wrote:
>
> Alex Bennée writes:
>
>> no-re...@patchew.org writes:
>>
>>> Hi,
>>>
>>> This series failed build test on s390x host. Please find the details
>>> below.
>
> It also failed on x86-on-x86 MTTCG as well as other tests:
>
>>> ERROR:/var/tmp/patc
Hi,
On 2017/2/22 17:31, Zhang Chen wrote:
On 02/22/2017 11:42 AM, zhanghailiang wrote:
While do checkpoint, we need to flush all the unhandled packets,
By using the filter notifier mechanism, we can easily to notify
every compare object to do this process, which runs inside
of compare threads
On 02/17/2017 01:30 AM, fred.kon...@greensocs.com wrote:
From: KONRAD Frederic
get_page_addr_code(..) does a cpu_ldub_code to fill the tlb:
This can lead to some side effects if a device is mapped at this address.
So this patch replaces the cpu_memory_ld by a tlb_fill.
Signed-off-by: KONRAD F
On Wed, 22 Feb 2017 10:03:56 +0100
Paolo Bonzini wrote:
> On 21/02/2017 18:54, Laszlo Ersek wrote:
> > Actually, QEMU segfaults. From the dmesg:
> >
> > [Tue Feb 21 18:47:28 2017] CPU 0/KVM[8298]: segfault at 48 ip
> > 7fcb5dd02105 sp 7fcb49efc270 error 4 in
> > qemu-system-x86_64[7fcb5d
On 02/17/2017 01:30 AM, fred.kon...@greensocs.com wrote:
From: KONRAD Frederic
This just moves the code before VICTIM_TLB_HIT macro definition
so we can use it.
Signed-off-by: KONRAD Frederic
---
cputlb.c | 72
1 file changed,
On 02/17/2017 01:30 AM, fred.kon...@greensocs.com wrote:
From: KONRAD Frederic
This replaces env1 and page_index variables by env and index
so we can use VICTIM_TLB_HIT macro later.
Signed-off-by: KONRAD Frederic
---
cputlb.c | 18 +-
1 file changed, 9 insertions(+), 9 deleti
On 02/21/2017 05:55 AM, Daniel P. Berrange wrote:
> The previous commit:
>
> commit a3e1505daec31ef56f0489f8c8fff1b8e4ca92bd
> Author: Eric Blake
> Date: Mon Dec 5 09:49:34 2016 -0600
>
> qcow2: Don't strand clusters near 2G intervals during commit
>
> extended the 097 test case so
On 02/22/2017 12:04 PM, Paolo Bonzini wrote:
> The functions simplify the handling of QOM properties whose type
> is a QAPI struct. They go through a QObject just like the other
> functions that access a QOM property through its C type.
>
> Like QAPI_CLONE, the functions are wrapped by macros tha
On 02/21/2017 03:01 PM, Markus Armbruster wrote:
> The new command line option -blockdev works like QMP command
> blockdev-add.
>
> The option argument may be given in JSON syntax, exactly as in QMP.
> Example usage:
>
> -blockdev '{"node-name": "foo", "driver": "raw", "file": {"driver":
> "
On 02/21/2017 03:01 PM, Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> ---
> qapi/qobject-input-visitor.c | 87
> ++--
> 1 file changed, 35 insertions(+), 52 deletions(-)
>
Reviewed-by: Eric Blake
I guess you aren't squashing this into 3
On 02/21/2017 03:01 PM, Markus Armbruster wrote:
> From: "Daniel P. Berrange"
>
> Currently the QObjectInputVisitor assumes that all scalar values are
> directly represented as the final types declared by the thing being
> visited. i.e. it assumes an 'int' is using QInt, and a 'bool' is using
> Q
Hello,
On 02/22/2017 07:27 PM, Andrew Baumann wrote:
> Hi,
>
>> From: Clement Deschamps [mailto:clement.descha...@antfield.fr]
>> Sent: Wednesday, 22 February 2017 3:24
>> Subject: [PATCH v2 3/3] bcm2835: add sdhost and gpio controllers
>>
>> This adds the bcm2835_sdhost and bcm2835_gpio to the B
On 02/22/2017 01:26 PM, Eduardo Habkost wrote:
> The "hotplugged" property is user visible, but it was never meant
> to be set by the user. There are probably multiple ways to break
> or crash device code by overriding the property. For example, we
> recently fixed a crash in rtc_set_memory() relat
glibc blacklists TSX on Haswell CPUs with model==60 and
stepping < 4. To make the Haswell CPU model more useful, make
those guests actually use TSX by changing CPU stepping to 4.
References:
* glibc commit 2702856bf45c82cf8e69f2064f5aa15c0ceb6359
https://sourceware.org/git/?p=glibc.git;a=commit
Helper function for code that needs to check the host CPU
vendor/family/model/stepping values.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* Coding style fix (split long lines)
---
target/i386/cpu.h | 1 +
target/i386/cpu.c | 29 +
2 files changed, 22 insert
Some Intel CPUs are known to have a broken TSX implementation. A
microcode update from Intel disabled TSX on those CPUs, but
GET_SUPPORTED_CPUID might be reporting it as supported if the
hosts were not updated yet.
Manually fixup the GET_SUPPORTED_CPUID data to ensure we will
never enable TSX when
Changes v1 -> v2:
* Coding style fixes
* Make series simpler:
* Don't use trick: char vendor[static (CPUID_VENDOR_SZ + 1)]
because it confuses checkpatch.pl
* Removed patch "Add explicit array size to x86_cpu_vendor_words2str()"
* Rebased on top of my x86-next branch:
https://github.com/e
Hi,
I added a few clarifications inline.
The relevant calculation is:
header_size + l2_tables_size + refcounts_tables_size + data_size
and it is also described inline.
I will be happy if you can confirm this calculation is acceptable
Thanks,
Maor
On Wed, Feb 22, 2017 at 6:15 PM, Maor Lipch
On 02/22/2017 03:45 AM, Peter Lieven wrote:
>
> Am 21.02.2017 um 22:13 schrieb John Snow:
>>
>> On 02/21/2017 07:43 AM, Peter Lieven wrote:
>>> Hi,
>>>
>>>
>>> is there anyone ever thought about implementing something like VMware
>>> CBT in Qemu?
>>>
>>>
>>> https://kb.vmware.com/selfservice/mic
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