Richard Henderson <r...@twiddle.net> writes:
> On 02/22/2017 10:44 PM, Nikunj A Dadhania wrote:
>> * SO and OV reflects overflow of the 64-bit result in 64-bit mode and
>> overflow of the low-order 32-bit result in 32-bit mode
>>
>> * OV32 reflects overflow of the low-order 32-bit independent of the mode
>>
>> Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com>
>> ---
>> target/ppc/translate.c | 15 ++++++++++++---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
>> index f3f92aa..43366e7 100644
>> --- a/target/ppc/translate.c
>> +++ b/target/ppc/translate.c
>> @@ -809,10 +809,19 @@ static inline void
>> gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
>> tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
>> }
>> tcg_temp_free(t0);
>> - if (NARROW_MODE(ctx)) {
>> - tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
>> + if (is_isa300(ctx)) {
>> + tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
>> + if (NARROW_MODE(ctx)) {
>> + tcg_gen_mov_tl(cpu_ov, cpu_ov32);
>> + } else {
>> + tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
>> + }
>> + } else {
>> + if (NARROW_MODE(ctx)) {
>> + tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
>> + }
>> + tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
>> }
>> - tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
>
> We're computing this two different ways for no reason. How about
>
> if (NARROW_MODE(ctx)) {
> tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
> if (is_isa300(ctx)) {
> tcg_gen_mov_tl(cpu_ov32, cpu_ov);
> }
> } else {
> if (is_isa300(ctx)) {
> tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
> }
> tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
> }
Yes, no need to extend-sign and shift. Will incorparate.
Regards
Nikunj
