On Fr, 2017-02-10 at 01:17 +0100, Martin Cerveny wrote:
> Hello.
>
> Ok. Not more bugs. The problem was in qemu-xen-4.8 missing "usb-redir:
> allocate buffers before waking up the host adapter"
Ah cool. Thanks for the notice.
cheers,
Gerd
Use float126_to_uint[64/32] instead of using int versions of the same.
Signed-off-by: Bharata B Rao
CC: Christian Borntraeger
CC: Cornelia Huck
---
target/s390x/fpu_helper.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_h
xsaddqpo: VSX Scalar Add Quad-Precision using round to Odd
xsmulqo: VSX Scalar Multiply Quad-Precision using round to Odd
xsdivqpo: VSX Scalar Divide Quad-Precision using round to Odd
xscvqpdpo: VSX Scalar round & Convert Quad-Precision format to
Double-Precision format using round t
float128_to_uint32() is needed by target/s390.
Signed-off-by: Bharata B Rao
CC: Christian Borntraeger
CC: Cornelia Huck
---
fpu/softfloat.c | 17 +
include/fpu/softfloat.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 48
xscvqpudz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Doubleword format
xscvqpuwz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Word format
Signed-off-by: Bharata B Rao
---
target/ppc/fpu_helper.c | 2 ++
target/ppc/helper
This series contains 2 new instructions (xscvqpudz, xscvqpuwz) and
round-to-odd variants of 6 instructions (xsaddqpo, xsmulqpo, xsdivqpo,
xscvqpdpo, xssqrtqpo, xssubqpo)
This also includes softfloat enhancements that are needed by
the above instructions. These softfloat patches have been posted
s
Implement float128_to_uint64() and use that to implement
float128_to_uint64_round_to_zero()
This is required by xscvqpudz instruction of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao
Reviewed-by: Peter Maydell
---
Ealier posted separately at:
https://lists.nongnu.org/archive/html/qemu-devel/201
Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:
Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exactly in the target form
float128_to_uint32_round_to_zero() is needed by xscvqpuwz instruction
of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao
Reviewed-by: Peter Maydell
---
Earlier posted separately at:
https://lists.nongnu.org/archive/html/qemu-devel/2017-02/msg01326.html
fpu/softfloat.c | 28 ++
On 02/09/2017 09:53 PM, Bystricky, Juro wrote:
>
>
>> On 02/09/2017 07:52 PM, Juro Bystricky wrote:
>>> JTAG UART core eliminates the need for a separate RS-232 serial
>>> connection to a host PC for character I/O.
>>
>> And how does this describe the content of this patch ? This patch adds a
>>
Hi,
On 02/09/2017 07:52 PM, Juro Bystricky wrote:
> JTAG UART core eliminates the need for a separate RS-232 serial
> connection to a host PC for character I/O.
>
> Hardware emulation based on:
> https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf
> (Please see "Register Map" on pa
On 2017年02月07日 16:28, Peter Xu wrote:
This patch is based on Aviv Ben-David ()'s patch
upstream:
"IOMMU: enable intel_iommu map and unmap notifiers"
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg01453.html
However I removed/fixed some content, and added my own codes.
Instead
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Subject: [Qemu-devel] [PATCH] osdep.h: pull in sys/sysmacros.h for
major/minor/makedev
Message-id: 20170210061200.15373-1-vap
Linux C libs are moving away from implicit header pollution with
sys/types.h
Signed-off-by: Mike Frysinger
---
include/qemu/osdep.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index 56c9e22405ec..6aaace6cf37f 100644
--- a/include/qemu/osdep
On Fri, Feb 10, 2017 at 12:12:22PM +1100, David Gibson wrote:
> On Tue, Feb 07, 2017 at 04:28:04PM +0800, Peter Xu wrote:
> > A cleanup for vfio_iommu_map_notify(). Now we will fetch vaddr even if
> > the operation is unmap, but it won't hurt much.
> >
> > One thing to mention is that we need the
On Fri, 2017-02-10 at 16:28 +1100, Suraj Jitindar Singh wrote:
> On Fri, 2017-02-10 at 16:25 +1100, Suraj Jitindar Singh wrote:
> >
> > This is V2 of the patch series to implement tcg emulation support
> > for
> > a
> > POWER9 cpu model for the pseries machine type running a legacy
> > kernel.
> >
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9
pseries tcg
Message-id: 1486704360-27361-1-git
Add POWER9 cpu to list of spapr core models which allows it to be specified
as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9).
This now allows a POWER9 cpu to boot to userspace in tcg emulation for a
pseries machine with a legacy kernel.
Signed-off-by: Suraj Jitindar Singh
On Fri, 2017-02-10 at 16:25 +1100, Suraj Jitindar Singh wrote:
> This is V2 of the patch series to implement tcg emulation support for
> a
> POWER9 cpu model for the pseries machine type running a legacy
> kernel.
> That is a kernel which doesn't use the new radix mmu mode or the new
> hash
> mmu m
ISA v3.00 adds the idea of a partition table which is used to store the
address translation details for all partitions on the system. The partition
table consists of double word entries indexed by partition id where the second
double word contains the location of the process table in guest memory.
The cpu has work function is used to mask interrupts used to determine
if there is work for the cpu based on the LPCR. Add a function to do this
for POWER9 and add it to the POWER9 cpu definition. This is similar to that
for POWER8 except using the LPCR bits as defined for POWER9.
Signed-off-by: S
Add a new mmu fault handler for the POWER9 cpu and add it as the handler
for the POWER9 cpu definition.
This handler checks if the guest is radix or hash based on the value in the
partition table entry and calls the correct fault handler accordingly.
The hash fault handling code has also been upd
The SDR1 register was used on pre-POWER9 processors to store the location
of the hash page table, however now this information will be stored in the
partition table so we don't have SDR1 anymore. Additionally this register
was only applicable for powernv as it is a hypervisor resource and thus
shou
The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu.h| 18 ++
Add a pa-features definition which includes all of the new fields which
have been added, note we don't claim support for any of these new features
at this stage.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/ppc/
This is V2 of the patch series to implement tcg emulation support for a
POWER9 cpu model for the pseries machine type running a legacy kernel.
That is a kernel which doesn't use the new radix mmu mode or the new hash
mmu mode with segment tables.
To use a POWER9 cpu provide the command line option
POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu-qom.h| 5 -
target/ppc/mmu_helper.c | 2 ++
target/ppc/transl
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.
Signed-off-by: Suraj Jiti
The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b
On Thu, Feb 9, 2017 at 8:45 PM, Pranith Kumar wrote:
>
> The current method of executing atomic code in a guest uses
> cpu_exec_step_atomic() from the outermost loop. This causes an abort()
> when single stepping over atomic code since debug exception longjmp
> will point to the the setlongjmp in
David Gibson writes:
> [ Unknown signature status ]
> On Thu, Feb 09, 2017 at 04:04:04PM +0530, Nikunj A Dadhania wrote:
>> POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
>> and corresponding defines. Moreover, CA32 is set when CA is set and
>> OV32 is set when OV is set, t
On 02/09/2017 08:14 AM, Thomas Huth wrote:
hw_error() is for CPU related errors only (it prints out a
register dump and calls abort()), so we should not use it
if we just failed to load the bios image. Apart from that,
realize() functions should not exit directly but always set
the errp with erro
On Wed, Feb 08, 2017 at 08:39:36PM +, Nawrocki, Michael wrote:
> This patch extends support for the `dump-guest-memory` command to
> the 32-bit PowerPC architecture. It relies on the assumption that a
> 64-bit guest will not dump a 32-bit core file (and vice versa); if
> this assumption is inv
On 2017/2/9 20:53, Alexander Graf wrote:
> Fw-cfg recently learned how to directly access guest memory and does so in
> cache coherent fashion. Tell the guest about that fact when it's using ACPI.
>
> Signed-off-by: Alexander Graf
> ---
> hw/arm/virt-acpi-build.c | 1 +
> 1 file changed, 1 ins
On 2017/2/9 20:53, Alexander Graf wrote:
> Virtio-mmio devices can directly access guest memory and do so in cache
> coherent fashion. Tell the guest about that fact when it's using ACPI.
>
> Signed-off-by: Alexander Graf
> ---
> hw/arm/virt-acpi-build.c | 1 +
> 1 file changed, 1 insertion(+)
Hi guys:
Used the guest-exec function, I try to run the windows`s powershell scriptes,
but the failed.
The cmd and error message:
```
virsh # qemu-agent-command 0e25dcdc-7441-4fc4-8993-4469135a0223 '{"execute":
"guest-exec", "arguments": {"path": "powershell", "arg": ["-ExecutionPolicy",
"Rem
On Tue, Feb 07, 2017 at 04:28:18PM +0800, Peter Xu wrote:
> This is preparation work to finally enabled dynamic switching ON/OFF for
> VT-d protection. The old VT-d codes is using static IOMMU address space,
> and that won't satisfy vfio-pci device listeners.
>
> Let me explain.
>
> vfio-pci devi
On Tue, Feb 07, 2017 at 04:28:15PM +0800, Peter Xu wrote:
> Generalizing the notify logic in memory_region_notify_iommu() into a
> single function. This can be further used in customized replay()
> functions for IOMMUs.
>
> Signed-off-by: Peter Xu
Reviewed-by: David Gibson
> ---
> include/exe
On Fri, Feb 10, 2017 at 12:05:38PM +1100, Suraj Jitindar Singh wrote:
> On Fri, 2017-02-10 at 11:21 +1100, David Gibson wrote:
> > On Fri, Feb 10, 2017 at 10:47:15AM +1100, Suraj Jitindar Singh wrote:
> > >
> > > On Thu, 2017-02-09 at 14:08 +1100, Suraj Jitindar Singh wrote:
> > > >
> > > > On We
On Tue, Feb 07, 2017 at 04:28:17PM +0800, Peter Xu wrote:
> The default replay() don't work for VT-d since vt-d will have a huge
> default memory region which covers address range 0-(2^64-1). This will
> normally consumes a lot of time (which looks like a dead loop).
>
> The solution is simple - w
On Tue, Feb 07, 2017 at 04:28:13PM +0800, Peter Xu wrote:
> Signed-off-by: Peter Xu
Reviewed-by: David Gibson
> ---
> include/exec/memory.h | 3 +++
> memory.c | 4 ++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/include/exec/memory.h b/include/exec/memor
On Tue, Feb 07, 2017 at 04:28:14PM +0800, Peter Xu wrote:
> This is an "global" version of exising memory_region_iommu_replay() - we
> announce the translations to all the registered notifiers, instead of a
> specific one.
>
> Signed-off-by: Peter Xu
Reviewed-by: David Gibson
> ---
> include/
On Tue, Feb 07, 2017 at 04:28:16PM +0800, Peter Xu wrote:
> Originally we have one memory_region_iommu_replay() function, which is
> the default behavior to replay the translations of the whole IOMMU
> region. However, on some platform like x86, we may want our own replay
> logic for IOMMU regions.
On Tue, Feb 07, 2017 at 04:28:12PM +0800, Peter Xu wrote:
> In this patch, IOMMUNotifier.{start|end} are introduced to store section
> information for a specific notifier. When notification occurs, we not
> only check the notification type (MAP|UNMAP), but also check whether the
> notified iova ran
On Tue, Feb 07, 2017 at 04:28:10PM +0800, Peter Xu wrote:
> Another patch to convert the DPRINTF() stuffs. This patch focuses on the
> address translation path and caching.
>
> Signed-off-by: Peter Xu
Reviewed-by: David Gibson
> ---
> hw/i386/intel_iommu.c | 69
> ++--
On Tue, Feb 07, 2017 at 04:28:08PM +0800, Peter Xu wrote:
> There are lots of places in current intel_iommu.c codes that named
> "iova" as "gpa". It is really confusing to use a name "gpa" in these
> places (which is very easily to be understood as "Guest Physical
> Address", while it's not). To ma
On Tue, Feb 07, 2017 at 04:28:04PM +0800, Peter Xu wrote:
> A cleanup for vfio_iommu_map_notify(). Now we will fetch vaddr even if
> the operation is unmap, but it won't hurt much.
>
> One thing to mention is that we need the RCU read lock to protect the
> whole translation and map/unmap procedure
On Tue, Feb 07, 2017 at 04:28:05PM +0800, Peter Xu wrote:
> Linux vfio driver supports to do VFIO_IOMMU_UNMAP_DMA for a very big
> region. This can be leveraged by QEMU IOMMU implementation to cleanup
> existing page mappings for an entire iova address space (by notifying
> with an IOTLB with extre
On Thu, Feb 09, 2017 at 12:48:19PM +0100, Paolo Bonzini wrote:
>
>
> On 09/02/2017 06:43, Alexey Kardashevskiy wrote:
> > On 03/01/17 10:34, David Gibson wrote:
> >> On Thu, Dec 22, 2016 at 04:22:11PM +1100, Alexey Kardashevskiy wrote:
> >>> getrampagesize() returns the largest supported page siz
On Tue, Feb 07, 2017 at 04:28:09PM +0800, Peter Xu wrote:
> VT-d codes are still using static DEBUG_INTEL_IOMMU macro. That's not
> good, and we should end the day when we need to recompile the code
> before getting useful debugging information for vt-d. Time to switch to
> the trace system. This i
On Tue, Feb 07, 2017 at 04:28:11PM +0800, Peter Xu wrote:
> This helps in debugging incorrect level passed in.
>
> Reviewed-by: Jason Wang
> Signed-off-by: Peter Xu
Reviewed-by: David Gibson
> ---
> hw/i386/intel_iommu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/i386/intel
On Tue, Feb 07, 2017 at 04:28:06PM +0800, Peter Xu wrote:
> From: Aviv Ben-David
>
> This capability asks the guest to invalidate cache before each map operation.
> We can use this invalidation to trap map operations in the hypervisor.
>
> Signed-off-by: Aviv Ben-David
> [peterx: using "caching
On Tue, Feb 07, 2017 at 04:28:07PM +0800, Peter Xu wrote:
> Now we have a standalone memory region for MSI, all the irq region
> requests should be redirected there. Cleaning up the block with an
> assertion instead.
>
> Reviewed-by: Jason Wang
> Signed-off-by: Peter Xu
Reviewed-by: David Gibso
This issue is like the issue in e1000 network card addressed in
this commit:
e1000: eliminate infinite loops on out-of-bounds transfer start.
Signed-off-by: Li Qiang
---
Change since v2:
fix error in e1000e_ring_empty
eliminate unnecessory detect code in loop
Changes since v1:
make wraparound d
On Thu, Feb 09, 2017 at 04:27:07PM -0800, ashish mittal wrote:
> On Thu, Feb 9, 2017 at 10:45 AM, ashish mittal wrote:
> > On Thu, Feb 9, 2017 at 10:08 AM, ashish mittal wrote:
> >> On Thu, Feb 9, 2017 at 8:50 AM, Jeff Cody wrote:
> >>> On Thu, Feb 09, 2017 at 08:14:38AM -0800, ashish mittal wro
The current method of executing atomic code in a guest uses
cpu_exec_step_atomic() from the outermost loop. This causes an abort()
when single stepping over atomic code since debug exception longjmp
will point to the the setlongjmp in cpu_exec(). Another issue with
this mechanism is that the flags
Hello John,
2017-02-10 3:42 GMT+08:00 John Snow :
>
>
> On 02/09/2017 02:04 AM, Li Qiang wrote:
> > As the pci ahci can be hotplug and unplug, in the ahci unrealize
> > function it should free all the resource once allocated in the
> > realized function. This patch adds two cleanup function.
> >
On Fri, 2017-02-10 at 11:21 +1100, David Gibson wrote:
> On Fri, Feb 10, 2017 at 10:47:15AM +1100, Suraj Jitindar Singh wrote:
> >
> > On Thu, 2017-02-09 at 14:08 +1100, Suraj Jitindar Singh wrote:
> > >
> > > On Wed, 2017-02-01 at 15:28 +1100, David Gibson wrote:
> > > >
> > > >
> > > > On Fri
On 02/05/17 10:11, b...@skyportsystems.com wrote:
> +Or to change guid in runtime use:
> +
> + set-vm-generation-id guid=124e6eaf-d1d1-4bf6-bf41-b9bb6c91fb87
> + set-vm-generation-id guid=auto
>
Please drop the "guid=" prefix from the examples; the HMP command
doesn't need it / chokes on it. It
23/22 ?
:)
On Fri, Feb 10, 2017 at 10:01:22AM +1000, Richard Henderson wrote:
> Threads work much better when you set the TLS register.
> This was fixed in the upstream kernel for Linux 4.9.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/openrisc/target_cpu.h | 4 +---
> 1 file change
On Fri, Feb 10, 2017 at 10:47:15AM +1100, Suraj Jitindar Singh wrote:
> On Thu, 2017-02-09 at 14:08 +1100, Suraj Jitindar Singh wrote:
> > On Wed, 2017-02-01 at 15:28 +1100, David Gibson wrote:
> > >
> > > On Fri, Jan 13, 2017 at 05:28:17PM +1100, Suraj Jitindar Singh
> > > wrote:
> > > >
> > > >
On Thu, Feb 09, 2017 at 10:04:47AM +0100, Laszlo Ersek wrote:
> On 02/09/17 05:16, David Gibson wrote:
> > On Wed, Feb 08, 2017 at 11:40:50AM +0100, Laszlo Ersek wrote:
> >> On 02/08/17 07:16, David Gibson wrote:
> >>> Marcel,
> >>>
> >>> Your original patch adding PCIe support to virtio-pci.c has
On Thu, Feb 09, 2017 at 09:10:51AM -0500, G 3 wrote:
>
> On Feb 8, 2017, at 11:52 PM, qemu-devel-requ...@nongnu.org wrote:
>
> > Message: 6
> > Date: Wed, 8 Feb 2017 20:51:32 -0800
> > From: Richard Henderson
> > To: qemu-devel@nongnu.org
> > Cc: sho...@gmail.com
> > Subject: [Qemu-devel] [PATC
On Thu, Feb 09, 2017 at 04:03:59PM +0530, Nikunj A Dadhania wrote:
> This series contains 6 new instructions for POWER9 ISA3.0
I've merged 1-4, 5 has comments.
>
> Nikunj A Dadhania (6):
> target-ppc: generate exception for copy/paste
> target-ppc: add slbieg instruction
> target-ppc: add
On Thu, Feb 09, 2017 at 01:58:28PM +1100, Suraj Jitindar Singh wrote:
> On Wed, 2017-02-01 at 15:09 +1100, David Gibson wrote:
> > On Fri, Jan 13, 2017 at 05:28:14PM +1100, Suraj Jitindar Singh wrote:
> > >
> > > Similarly to how we have an external hpt pointer in the cpu state,
> > > add
> > > an
On Thu, Feb 09, 2017 at 12:08:38PM +0100, Igor Mammedov wrote:
> All callbacks FOO_query_hotpluggable_cpus() are practically
> the same except of setting vcpus_count to different values.
> Convert them to a generic machine_query_hotpluggable_cpus()
> callback by moving vcpus_count initialization to
On Thu, Feb 09, 2017 at 11:03:29AM +0530, Nikunj A Dadhania wrote:
> This series contains 4 new instructions for POWER9 ISA3.0
> Load/Store Atomic instructions
>
> Changelog:
> v0:
>Raise invalid execption for function codes that are not implemented,
>and data storage execption for in
On Thu, Feb 09, 2017 at 04:04:04PM +0530, Nikunj A Dadhania wrote:
> POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
> and corresponding defines. Moreover, CA32 is set when CA is set and
> OV32 is set when OV is set, there is no need to have a new
> fields in the CPUPPCState s
On Thu, Feb 09, 2017 at 01:57:58PM +1100, Suraj Jitindar Singh wrote:
> On Wed, 2017-02-01 at 15:04 +1100, David Gibson wrote:
> > On Fri, Jan 13, 2017 at 05:28:13PM +1100, Suraj Jitindar Singh wrote:
> > >
> > > POWER9 uses a partition table to store information relating to how
> > > address tran
On Thu, Feb 09, 2017 at 02:04:52PM +1100, Suraj Jitindar Singh wrote:
> On Wed, 2017-02-01 at 15:23 +1100, David Gibson wrote:
> > On Fri, Jan 13, 2017 at 05:28:16PM +1100, Suraj Jitindar Singh wrote:
> > >
> > > Add a new mmu fault handler for the POWER9 cpu and add it as the
> > > handler
> > >
On Thu, Feb 9, 2017 at 10:45 AM, ashish mittal wrote:
> On Thu, Feb 9, 2017 at 10:08 AM, ashish mittal wrote:
>> On Thu, Feb 9, 2017 at 8:50 AM, Jeff Cody wrote:
>>> On Thu, Feb 09, 2017 at 08:14:38AM -0800, ashish mittal wrote:
On Thu, Feb 9, 2017 at 6:32 AM, Jeff Cody wrote:
> On Th
Hello.
Ok. Not more bugs. The problem was in qemu-xen-4.8 missing "usb-redir: allocate
buffers before waking up the host adapter"
Martin
On Fri, 3 Feb 2017, Martin Cerveny wrote:
Hello.
Thanks for patch. I tested it.
Good news, does not assert() :-)
Bad news, not all works as expected (tra
Threads work much better when you set the TLS register.
This was fixed in the upstream kernel for Linux 4.9.
Signed-off-by: Richard Henderson
---
linux-user/openrisc/target_cpu.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/linux-user/openrisc/target_cpu.h b/linux-user/
On Thu, Feb 09, 2017 at 12:08:37PM +0100, Igor Mammedov wrote:
> Replace SPAPR specific cores[] array with generic
> machine->possible_cpus and store core objects there.
> It makes cores bookkeeping similar to x86 cpus and
> will allow to unify similar code.
> It would allow to replace cpu_index ba
On Thu, Feb 09, 2017 at 12:08:35PM +0100, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Reviewed-by: David Gibson
> ---
> hw/i386/pc.c | 16 +---
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index f03a555..ec6dded 100644
>
On Thu, Feb 09, 2017 at 12:08:36PM +0100, Igor Mammedov wrote:
> so it could be reused for SPAPR cores as well
>
> Signed-off-by: Igor Mammedov
Reviewed-by: David Gibson
> ---
> include/hw/boards.h | 2 +-
> hw/acpi/cpu.c | 2 +-
> hw/i386/pc.c| 8
> 3 files changed, 6
On Thu, Feb 09, 2017 at 12:08:32PM +0100, Igor Mammedov wrote:
> so that it would be possible to reuse it with
> spapr/virt-aarch64 targets.
>
> Signed-off-by: Igor Mammedov
Reviewed-by: David Gibson
> ---
> include/hw/boards.h | 1 +
> include/hw/i386/pc.h | 1 -
> hw/i386/pc.c |
On Thu, Feb 09, 2017 at 12:08:33PM +0100, Igor Mammedov wrote:
> possible_cpus could be initialized earlier then cpu objects,
> i.e. when -smp is parsed so move init code to possible_cpu_arch_ids()
> interface func and do initialization on the first call.
>
> it should help later with making -numa
On Thu, Feb 09, 2017 at 12:08:34PM +0100, Igor Mammedov wrote:
> Fill in CpuInstanceProperties once at board init time and
> just copy them whenever query_hotpluggable_cpus() is called.
> It will keep topology info always available without need
> to recalculate it every time it's needed.
> Consider
On Thu, Feb 09, 2017 at 02:37:26PM +, Peter Maydell wrote:
> On 9 February 2017 at 14:13, Thomas Huth wrote:
> > Peter Maydell recently ran into time-out problems with the
> > prom-env test on a rather slow ARM board. To tackle this issue,
> > we can speed up the test by running QEMU with "-no
On Thu, 2017-02-09 at 14:08 +1100, Suraj Jitindar Singh wrote:
> On Wed, 2017-02-01 at 15:28 +1100, David Gibson wrote:
> >
> > On Fri, Jan 13, 2017 at 05:28:17PM +1100, Suraj Jitindar Singh
> > wrote:
> > >
> > >
> > > The page table entry format was updated for the POWER9 processor.
> > >
> >
On 02/10/2017 07:58 AM, Peter Maydell wrote:
On 9 February 2017 at 20:03, Richard Henderson wrote:
On 02/09/2017 11:31 AM, Peter Maydell wrote:
Review from somebody who understands how the unassigned_access
hooks are supposed to work appreciated.
The unassigned_access hook was (unfortunatel
Le 09/02/2017 à 12:14, Thomas Huth a écrit :
hw_error() is for CPU related errors only (it prints out a
register dump and calls abort()), so we should not use it
if we just failed to load the bios image. Apart from that,
realize() functions should not exit directly but always set
the errp with er
On 01/27/2017 12:40 PM, Paolo Bonzini wrote:
If the vring has not been set up, it is not necessary for vring_used_idx
to do anything (as is already the case when the caller is virtio_load).
This is harmless for now, but it will be a problem when the
MemoryRegionCache has not been set up.
Signed-
On 01/27/2017 12:40 PM, Paolo Bonzini wrote:
Clear cache->mr so that address_space_cache_destroy does nothing
the second time it is called.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
---
exec.c | 1 +
1 file changed, 1 insertion(+)
diff
On 01/27/2017 12:40 PM, Paolo Bonzini wrote:
Make it easy to unregister a MemoryListener without tracking whether it
had been registered before.
Signed-off-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
---
v3: new
memory.c | 5 +
1 file changed, 5 insertions(+)
diff
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Thursday, 9 February 2017 14:02
> On 9 February 2017 at 20:46, John Snow wrote:
> > On 02/09/2017 07:46 AM, Peter Maydell wrote:
> >> Slightly late, but I had an idea last night: would "get
> >> Raspbian booting on our raspi2 board mo
On 9 February 2017 at 22:12, Andrew Baumann
wrote:
>> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
>> Sent: Thursday, 9 February 2017 14:02
>> On 9 February 2017 at 20:46, John Snow wrote:
>> > On 02/09/2017 07:46 AM, Peter Maydell wrote:
>> >> Slightly late, but I had an idea last night
On 02/05/2017 10:37 AM, xiaoqiang zhao wrote:
Drop the old SysBusDeviceClass::init and use instance_init
or DeviceClass::realize instead
Signed-off-by: xiaoqiang zhao
Reviewed-by: Philippe Mathieu-Daudé
---
hw/sparc64/sun4u.c | 20 +---
1 file changed, 9 insertions(+), 11
On 02/03/2017 03:59 PM, Peter Maydell wrote:
In float64_to_uint64_round_to_zero() a typo meant that we were
taking the uint64_t return value from float64_to_uint64() and
putting it into an int64_t variable before returning it as
uint64_t again. Use uint64_t instead of pointlessly casting it
back
On 02/04/2017 08:05 PM, Peter Maydell wrote:
Coverity doesn't like the code in load_symbols() which assumes
it can use 'int' for a variable that might hold an offset into
the guest ELF file, because in a 64-bit guest that could
overflow. Guest binaries with 2GB sections aren't very likely
and thi
On 02/05/2017 10:37 AM, xiaoqiang zhao wrote:
Drop the old SysBusDeviceClass::init and use instance_init
or DeviceClass::realize instead
Signed-off-by: xiaoqiang zhao
Reviewed-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 54 +++---
1 fi
On 02/05/2017 10:37 AM, xiaoqiang zhao wrote:
rename slavio_timer_init1 to slavio_timer_init and assign
it to slavio_timer_info.instance_init, then we drop the
SysBusDeviceClass::init
Signed-off-by: xiaoqiang zhao
Reviewed-by: Philippe Mathieu-Daudé
---
hw/timer/slavio_timer.c | 12 +-
On 02/05/2017 10:37 AM, xiaoqiang zhao wrote:
* split the old SysBus init function into an instance_init
and a Device realize function
* use DeviceClass::realize instead of SysBusDeviceClass::init
Signed-off-by: xiaoqiang zhao
Reviewed-by: Philippe Mathieu-Daudé
---
hw/timer/m48t59.c |
On 02/05/2017 10:37 AM, xiaoqiang zhao wrote:
Drop the old SysBus init function and use instance_init
and an realize function
Signed-off-by: xiaoqiang zhao
Reviewed-by: Philippe Mathieu-Daudé
---
hw/dma/sparc32_dma.c | 25 +++--
1 file changed, 15 insertions(+), 10 del
On 9 February 2017 at 20:46, John Snow wrote:
> On 02/09/2017 07:46 AM, Peter Maydell wrote:
>> Slightly late, but I had an idea last night: would "get
>> Raspbian booting on our raspi2 board model" be a good
>> project? Would involve some mix of bug fixing, cleaning
>> up and adding device models
On 9 February 2017 at 20:03, Richard Henderson wrote:
> On 02/09/2017 11:31 AM, Peter Maydell wrote:
>> Review from somebody who understands how the unassigned_access
>> hooks are supposed to work appreciated.
> The unassigned_access hook was (unfortunately) designed after the
> unaligned_access
On 02/09/2017 10:47 AM, Cédric Le Goater wrote:
The size of a segment is not necessarily a power of 2.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ssi/aspeed_smc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/
On 02/09/2017 10:47 AM, Cédric Le Goater wrote:
The flash devices used for the FMC controller (BMC firmware) are well
defined for each Aspeed machine and are all smaller than the default
mapping window size, at least for CE0 which is the chip the SoC boots
from.
Signed-off-by: Cédric Le Goater
On 01/31/2017 07:54 PM, Max Reitz wrote:
>>> Another thing: I'm not quite positive whether qcow2_cluster_zeroize()
>>> can actually handle a byte count greater than INT_MAX. If you could pass
>>> such a number to it, the multiplication "ret * s->cluster_size" might
>>> overflow. It's only caller q
1 - 100 of 304 matches
Mail list logo
