When user specify "intremap=on" with "-M kernel-irqchip=on", throw error
and then quit.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 00e6682..06cc94f 100644
--- a/hw/i386/int
Changing the original MSIMessage parameter in kvm_irqchip_add_msi_route
into the vector number. Vector index provides more information than the
MSIMessage, we can retrieve the MSIMessage using the vector easily. This
will avoid fetching MSIMessage every time before adding MSI routes.
Meanwhile, th
From: Radim Krčmář
Linux guests do not gracefully handle cases when the invalidation mask
they wanted is not supported, probably because real hardware always
allowed all.
We can just say that all 16 masks are supported, because both
ioapic_iec_notifier and kvm_update_msi_routes_all invalidate al
Let IOAPIC the first consumer of x86 IOMMU IEC invalidation
notifiers. This is only used for split irqchip case, when vIOMMU
receives IR invalidation requests, IOAPIC will be notified to update
kernel irq routes. For simplicity, we just update all IOAPIC routes,
even if the invalidated entries are
This patch introduces x86 IOMMU IEC (Interrupt Entry Cache)
invalidation notifier list. When vIOMMU receives IEC invalidate
request, all the registered units will be notified with specific
invalidation requests.
Intel IOMMU is the first provider that generates such a event.
Signed-off-by: Peter X
In split irqchip mode, IOAPIC is working in user space, only update
kernel irq routes when entry changed. When IR is enabled, we directly
update the kernel with translated messages. It works just like a kernel
cache for the remapping entries.
Since KVM irqfd is using kernel gsi routes to deliver i
Bharata B Rao writes:
> On Tue, Jul 12, 2016 at 11:33 PM, Nikunj A Dadhania
> wrote:
>> From: "Aneesh Kumar K.V"
>>
>> Signed-off-by: Aneesh Kumar K.V
>> [ rebased and added POWER9 alias ]
>> Signed-off-by: Nikunj A Dadhania
>> ---
>> target-ppc/cpu-models.c | 5 +++
>> target-ppc/cpu-m
Abstract IOAPIC entry parsing logic into a helper function.
Signed-off-by: Peter Xu
---
hw/intc/ioapic.c | 110 +++
1 file changed, 54 insertions(+), 56 deletions(-)
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 36dd42a..c4469e4 10064
Several data structs are defined to better support the rest of the
patches: IRTE to parse remapping table entries, and IOAPIC/MSI related
structure bits to parse interrupt entries to be filled in by guest
kernel.
Signed-off-by: Peter Xu
---
include/hw/i386/intel_iommu.h | 74
These will help us monitoring irqchip route activities more easily.
Signed-off-by: Peter Xu
Reviewed-by: Paolo Bonzini
---
kvm-all.c| 5 +
trace-events | 3 +++
2 files changed, 8 insertions(+)
diff --git a/kvm-all.c b/kvm-all.c
index 3764ba9..ef81ca5 100644
--- a/kvm-all.c
+++ b/kvm-a
In the past, we are doing gsi route commit for each irqchip route
update. This is not efficient if we are updating lots of routes in the
same time. This patch removes the committing phase in
kvm_irqchip_update_msi_route(). Instead, we do explicit commit after all
routes updated.
Signed-off-by: Pet
Defined Interrupt Remap Table Address register to store IR table
pointer. Also, do proper handling on global command register writes to
store table pointer and its size.
One more debug flag "DEBUG_IR" is added for interrupt remapping.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c |
This patch translates all IOAPIC interrupts into MSI ones. One pseudo
ioapic address space is added to transfer the MSI message. By default,
it will be system memory address space. When IR is enabled, it will be
IOMMU address space.
Currently, only emulated IOAPIC is supported.
Idea suggested by
Adding two hooks to be notified when adding/removing msi routes. There
are two kinds of MSI routes:
- in kvm_irqchip_add_irq_route(): before assigning IRQFD. Used by
vhost, vfio, etc.
- in kvm_irqchip_send_msi(): when sending direct MSI message, if
direct MSI not allowed, we will first create
One more IEC notifier is added to let msi routes know about the IEC
changes. When interrupt invalidation happens, all registered msi routes
will be updated for all PCI devices.
Since both vfio and vhost are possible gsi route consumers, this patch
will go one step further to keep them safe in spli
This patch enables interrupt remapping for PCI devices.
To play the trick, one memory region "iommu_ir" is added as child region
of the original iommu memory region, covering range 0xfeeX (which is
the address range for APIC). All the writes to this range will be taken
as MSI, and translation
In ACPI DMA remapping report structure, enable INTR flag when specified.
Signed-off-by: Peter Xu
---
hw/i386/acpi-build.c | 14 +-
include/hw/i386/intel_iommu.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.
Handle writting to IRE bit in global command register.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index bf74533..6a6cb3b 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386
This patch enables SID validation. Invalid interrupts will be dropped.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 69 ---
include/hw/i386/intel_iommu.h | 17 +++
2 files changed, 75 insertions(+), 11 deletions(-)
diff --git a/hw/i
Queued invalidation is required for IR. This patch add basic support for
interrupt cache invalidate requests. Since we currently have no IR cache
implemented yet, we can just skip all interrupt cache invalidation
requests for now.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 9 ++
Instead of searching the device tree every time, one static variable is
declared for the default system x86 IOMMU device.
Signed-off-by: Peter Xu
---
hw/i386/acpi-build.c| 9 ++---
hw/i386/x86-iommu.c | 23 +++
include/hw/i386/x86-iommu.h | 6 ++
3 f
From: Jan Kiszka
As neither QEMU nor KVM support more than 255 CPUs so far, this is
simple: we only need to switch the destination ID translation in
vtd_remap_irq_get if EIME is set.
Once CFI support is there, it will have to take EIM into account as
well. So far, nothing to do for this.
This p
Adding one property for intel-iommu devices to specify whether we should
support interrupt remapping. By default, IR is disabled. To enable it,
we should use (take Intel IOMMU as example):
-device intel_iommu,intremap=on
This property can be shared by Intel and future AMD IOMMUs.
Signed-off-by
Introducing parent class for intel-iommu devices named "x86-iommu". This
is preparation work to abstract shared functionalities out from Intel
and AMD IOMMUs. Currently, only the parent class is introduced. It does
nothing yet.
Signed-off-by: Peter Xu
---
hw/i386/Makefile.objs | 2 +-
h
To enable interrupt remapping for intel IOMMU device, each IOAPIC device
in the system reported via ACPI MADT must be explicitly enumerated under
one specific remapping hardware unit. This patch adds the root-complex
IOAPIC into the default DMAR device.
Please refer to VT-d spec 8.3.1.1 for more i
Adding translation fault definitions for interrupt remapping. Please
refer to VT-d spec section 7.1.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu_internal.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index
Enable IR in IOMMU Extended Capability register.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 6 ++
hw/i386/intel_iommu_internal.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 26e322a..9c7a084 100644
--- a/hw/i386/
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 11 +++
include/hw/i386/intel_iommu.h | 1 -
include/hw/i386/x86-iommu.h | 2 ++
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a430d7d..3ee5782 100644
--- a
This is v12 for Intel IR. Rebased to lastest master, with some tiny
tweaks from v11. Please check changelog below.
Michael, please choose either v11 or v12 if we are going to merge it.
v12 is preferred though. Thanks!
Online repo:
https://github.com/xzpeter/qemu vtd-intr-v12
v12 changes (usin
On 2016/7/14 0:12, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
Usage:
(qemu) migrate file:/path/to/vm_statefile
Signed-off-by: zhanghailiang
Signed-off-by: Benoit Canet
---
- With this patch, we can easily test memory snapshot
- Rebase on qemu 2.5
---
On Tue, Jul 12, 2016 at 11:33 PM, Nikunj A Dadhania
wrote:
> From: "Aneesh Kumar K.V"
>
> Signed-off-by: Aneesh Kumar K.V
> [ rebased and added POWER9 alias ]
> Signed-off-by: Nikunj A Dadhania
> ---
> target-ppc/cpu-models.c | 5 +++
> target-ppc/cpu-models.h | 2 ++
> target-ppc/cp
On Wed, Jul 13, 2016 at 04:17:01PM +0300, David Kiarie wrote:
[...]
> > +static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
> > + uint64_t *data, unsigned size,
> > + MemTxAttrs attrs)
> > +{
> > +addr += VTD_INTER
On Thu, 14 Jul 2016 12:05:42 +1000
David Gibson wrote:
> On Wed, Jul 13, 2016 at 02:34:32PM +0200, Greg Kurz wrote:
> > On Wed, 13 Jul 2016 11:10:21 +0200
> > Greg Kurz wrote:
> >
> > > Now that properties are set with -global, if we pass a bogus value for
> > > compat mode, a warning is prin
Signed-off-by: Michael Rolnik
---
target-avr/cpugen/CMakeLists.txt | 38 +++
target-avr/cpugen/README.md| 17 ++
target-avr/cpugen/cpu/avr.yaml | 214 ++
target-avr/cpugen/src/CMakeLists.txt | 63
target-avr/cpugen/src/cpugen.cpp
Signed-off-by: Michael Rolnik
---
target-avr/Makefile.objs|2 +-
target-avr/translate-inst.c | 2622 +++
target-avr/translate.h |1 +
3 files changed, 2624 insertions(+), 1 deletion(-)
create mode 100644 target-avr/translate-inst.c
diff -
Signed-off-by: Michael Rolnik
---
target-avr/cpu.h | 13 ++-
target-avr/helper.c| 284 ++---
target-avr/helper.h| 8 +-
target-avr/translate.c | 9 ++
4 files changed, 299 insertions(+), 15 deletions(-)
diff --git a/target-avr/cpu.h
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 6 ++
hw/avr/Makefile.objs | 21 ++
hw/avr/sample-io.c | 176 +++
hw/avr/sample.c | 137 +++
4 files changed, 340 insertions(+)
create mode 1
1. basic CPU structure
2. registers
3. no instructions
4. saving sreg, rampD, rampX, rampY, rampD, eind in HW representation
Signed-off-by: Michael Rolnik
---
arch_init.c | 2 +
configure | 5 +
default-configs/avr-softmmu.mak | 21 +
This patch adds a basic dd subcommand analogous to dd(1) to qemu-img.
For the start, this implements the bs, if, of and count options and requires
both if and of to be specified (no stdin/stdout if not specified) and doesn't
support tty, pipes, etc.
The image format must be specified with -O for
Signed-off-by: Michael Rolnik
---
target-avr/Makefile.objs | 1 +
target-avr/decode.c | 693 +++
target-avr/helper.c | 2 +
target-avr/helper.h | 1 +
target-avr/translate.c | 12 -
5 files changed, 697 insertions(+), 12 deletion
Signed-off-by: Michael Rolnik
---
target-avr/cpu.c | 313 ++-
target-avr/cpu.h | 48
target-avr/machine.c | 1 +
3 files changed, 361 insertions(+), 1 deletion(-)
diff --git a/target-avr/cpu.c b/target-avr/cpu.c
index 7e8d34b..0
Signed-off-by: Michael Rolnik
---
target-avr/helper.c | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index ffc9378..3e61193 100644
--- a/target-avr/helper.c
+++ b/target-avr/helper
Signed-off-by: Michael Rolnik
---
target-avr/translate-inst.h | 805
1 file changed, 805 insertions(+)
create mode 100644 target-avr/translate-inst.h
diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h
new file mode 100644
index 00
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet
On 07/05/2016 07:11 AM, Daniel P. Berrange wrote:
> The current -object command line syntax only allows for
> creation of objects with scalar properties, or a list
> with a fixed scalar element type. Objects which have
> properties that are represented as structs in the QAPI
> schema cannot be crea
This is a mostly-mechanical conversion that creates a new flat
union 'Netdev' QAPI type that covers all the branches of the
former 'NetClientOptions' simple union, where the branches are
now listed in a new 'NetClientDriver' enum rather than generated
from the simple union. The existence of a flat
From: "Daniel P. Berrange"
The opts-visitor.c opts_type_bool() method has code for
parsing a string to set a bool value, as does the
qemu-option.c parse_option_bool() method, except it
handles fewer cases.
To enable consistency across the codebase, extend
parse_option_bool() to handle "yes", "no
When we converted 'netdev_add' to a fully-introspectible QMP,
we temporarily lost the ability to parse strings in place of
integers, the way the old QemuOpts code had done. But now that
we have autocast, we can restore that behavior, by adding a
new 'autocast':true marker in QAPI.
Signed-off-by:
Now that we can support boxed commands, use it to greatly
reduce the number of parameters (and likelihood of getting
out of sync) when adjusting drive-mirror parameters.
Signed-off-by: Eric Blake
Reviewed-by: John Snow
---
v9: s/box/boxed/, trivial enough to keep R-b
v8: rebase, drop stale sent
is_netdev is only used as a bool, so make it one.
Signed-off-by: Eric Blake
---
v9: no change
v8: no change
v7: no change
v6: rebase to latest context
---
include/net/net.h| 2 +-
hw/usb/dev-network.c | 2 +-
net/net.c| 12 ++--
3 files changed, 8 insertions(+), 8 dele
Currently the QmpInputVisitor assumes that all scalar
values are directly represented as their final types.
ie it assumes an 'int' is using QInt, and a 'bool' is
using QBool.
This adds an alternative mode where a QString can also
be parsed in place of the native type, by adding a parameter
and upd
Ever since commit 12f254f removed the last parameterization
of gen_err_check(), it no longer makes sense to hide the three
lines of generated C code behind a macro call. Just inline it
into the remaining users.
No change to generated code.
Signed-off-by: Eric Blake
---
v9: new patch
v8: new pat
The next patch will add support for passing a qapi union type
as the 'data' of a command. But to do that, the user function
for implementing the command, as called by the generated
marshal command, must take the corresponding C struct as a
single boxed pointer, rather than a breakdown into one
par
Now that we can support boxed commands, use it to greatly
reduce the number of parameters (and likelihood of getting
out of sync) when adjusting throttle parameters.
Signed-off-by: Eric Blake
Reviewed-by: Alberto Garcia
---
v9: s/box/boxed/, trivial enough to keep R-b
v8: tweak doc wording
v7:
We finally have all the required pieces for doing a type-safe
representation of netdev_add as a flat union, where the
discriminator 'type' now selects which additional members may
appear in the "arguments" JSON object sent over QMP, and exposes
those types through introspection, and without breakin
Turn on the ability to pass command and event arguments in
a single boxed parameter, which must name a non-empty type
(although the type can be a struct with all optional members).
For structs, it makes it possible to pass a single qapi type
instead of a breakout of all struct members (useful if th
Commit 7ce106a9 documented why we don't generated a visit_type_FOO()
for implicit types; and therefore events with an anonymous type for
'data' have to open-code a visit. Note that the open-coded visit in
qapi-event.c is slightly different from what is done in
qapi-visit.c for normal types, in par
Clean up the only remaining external use of the tag_name field of
QAPISchemaObjectTypeVariants, by explicitly listing the generated
'type' tag for all variants in the testsuite (you can still tell
simple unions by the -wrapper types). Then we can mark the
tag_name field as private by adding a lead
It's time to expose QMP 'netdev_add' through introspection, and
to add boxed commands/events so that we can drastically reduce
the number of C parameters needed to implement a command that
matches a large QAPI type.
Prerequistes:
Markus' qapi-next branch (weak; series also applies on master)
avai
From: Kővágó, Zoltán
This way we no longer need NetClientOptions and can convert Netdev
into a flat union.
Signed-off-by: Kővágó, Zoltán
Reviewed-by: Eric Blake
Message-Id:
<93ffdfed7054529635e6acb935150d95dc173a12.1441627176.git.dirty.ice...@gmail.com>
[rework net_client_init1() to pass Net
In the near future, we want to lift our artificial restriction of
no variants at the top level of an event, at which point the
currently open-coded check for empty members will become
insufficient. Factor it out into a new helper method is_empty()
now, and future-proof it by checking variants, too
We were previously enforcing that all flat union branches were
found in the corresponding enum, but not that all enum values
were covered by branches. The resulting generated code would
abort() if the user passes the uncovered enum value.
We don't automatically treat non-present branches in a fla
Commit 7ce106a rendered QAPISchemaObjectType.c_name() redundant,
since it now does nothing more than delegate to its superclass.
However, rather than deleting it, we can restore part of the
assertion that was removed in that commit, to prove that we never
emit the empty type directly in generated c
On Wed, Jul 13, 2016 at 02:34:32PM +0200, Greg Kurz wrote:
> On Wed, 13 Jul 2016 11:10:21 +0200
> Greg Kurz wrote:
>
> > Now that properties are set with -global, if we pass a bogus value for
> > compat mode, a warning is printed and the property is simply ignored.
> > For example, if the host is
On Wed, Jul 13, 2016 at 12:00:17PM +0200, Greg Kurz wrote:
> It is not possible to set the compat property to an unknown value with
> powerpc_set_compat(). Something must have gone terribly wrong in QEMU,
> if we detect an "Internal error" in powerpc_get_compat(). Let's abort then.
>
> This patch
On Wed, Jul 13, 2016 at 08:05:03PM +0200, Greg Kurz wrote:
> When passing '-global driver=host-powerpc64-cpu,property=compat,value=foo'
> on the command line, without this patch, we get the following warning per
> device (which means many lines if the guests has many cpus):
>
> qemu-system-ppc64:
On 07/05/2016 07:11 AM, Daniel P. Berrange wrote:
> Currently the QmpInputVisitor assumes that all scalar
> values are directly represented as their final types.
> ie it assumes an 'int' is using QInt, and a 'bool' is
> using QBool.
>
> This adds an alternative constructor for QmpInputVisitor
> th
On 07/05/2016 07:11 AM, Daniel P. Berrange wrote:
> The opts-visitor.c opts_type_bool() method has code for
> parsing a string to set a bool value, as does the
> qemu-option.c parse_option_bool() method, except it
> handles fewer cases.
>
> To enable consistency across the codebase, extend
> parse
On Wed, Jul 13, 2016 at 12:20:20PM +0530, Bharata B Rao wrote:
> If CPU core addition or removal is allowed in random order leading to
> holes in the core id range (and hence in the cpu_index range), migration
> can fail as migration with holes in cpu_index range isn't yet handled
> correctly.
>
>
Eduardo Habkost writes:
> On Wed, Jul 13, 2016 at 06:59:21PM -0400, Bandan Das wrote:
>> Eduardo Habkost writes:
>>
>> > On Wed, Jul 13, 2016 at 06:32:27PM -0400, Bandan Das wrote:
>> >> Igor Mammedov writes:
>> >>
>> >> > consolidate possible_cpus array management in pc_cpu_plug()
>> >> > fo
Signed-off-by: Alistair Francis
---
V9:
- Clarify the image loading options
V8:
- Improve documentation
V6:
- Fixup documentation
V4:
- Re-write to be more comprehensive
docs/generic-loader.txt | 63 +
1 file changed, 63 insertions(+)
create m
Add a new function load_elf_as() that allows the caller to specify an
AddressSpace to use when loading the ELF. The original load_elf()
function doesn't have any change in functionality.
Signed-off-by: Alistair Francis
---
V8:
- Introduce an RFC version of AddressSpace support
hw/core/loader.c
Eduardo Habkost writes:
> On Wed, Jul 13, 2016 at 06:47:20PM -0400, Bandan Das wrote:
>> Igor Mammedov writes:
>>
>> > MAX_APICS is only used by child 'apic' class and not
>> > by its parent TYPE_APIC_COMMON or any other derived
>> > class.
>> > Move check into end user 'apic' class so it won't
Add a new function load_image_targphys_as() that allows the caller
to specify an AddressSpace to use when loading a targphys. The
original load_image_targphys() function doesn't have any change in
functionality.
Signed-off-by: Alistair Francis
---
hw/core/loader.c| 10 --
include/hw
Add a generic loader to QEMU which can be used to load images or set
memory values.
Signed-off-by: Alistair Francis
---
V9:
- Fix error messages
- Updated some incorrect logic
- Add address space loading support for all image types
- Explain why the reset is manually registered
V8:
- Code co
When loading ROMs allow the caller to specify an AddressSpace to use for
the load.
Signed-off-by: Alistair Francis
---
V9:
- Fixup the ROM ordering
- Don't allow address space and memory region to be specified
V8:
- Introduce an RFC version of AddressSpace loading support
hw/core/loader.c
Add a new function load_uimage_as() that allows the caller to
specify an AddressSpace to use when loading the uImage. The
original load_uimage() function doesn't have any change in
functionality.
Signed-off-by: Alistair Francis
---
hw/core/loader.c| 17 +
include/hw/loader.h
Prevously the specified MemoryRegion was ignored during the rom register
reset. This patch uses the rom MemoryRegion is avaliable.
Signed-off-by: Alistair Francis
---
hw/core/loader.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index
This work is based on the original work by Li Guang with extra
features added by Peter C and myself.
The idea of this loader is to allow the user to load multiple images
or values into QEMU at startup.
Memory values can be loaded like this: -device
loader,addr=0xfd1a0104,data=0x800e,data-len
If the caller didn't specify an architecture for the ELF machine
the load_elf() function will auto detect it based on the ELF file.
Signed-off-by: Alistair Francis
---
V9:
- Update documentation
V8:
- Move into load_elf64/load_elf32
V7:
- Fix typo
include/hw/elf_ops.h | 5 +
include/hw/l
On Wed, Jul 13, 2016 at 06:47:20PM -0400, Bandan Das wrote:
> Igor Mammedov writes:
>
> > MAX_APICS is only used by child 'apic' class and not
> > by its parent TYPE_APIC_COMMON or any other derived
> > class.
> > Move check into end user 'apic' class so it won't
> > get in the way of other APIC
On Wed, Jul 13, 2016 at 06:59:21PM -0400, Bandan Das wrote:
> Eduardo Habkost writes:
>
> > On Wed, Jul 13, 2016 at 06:32:27PM -0400, Bandan Das wrote:
> >> Igor Mammedov writes:
> >>
> >> > consolidate possible_cpus array management in pc_cpu_plug()
> >> > for smp_cpus, coldplugged with -devic
Eduardo Habkost writes:
> On Wed, Jul 13, 2016 at 06:32:27PM -0400, Bandan Das wrote:
>> Igor Mammedov writes:
>>
>> > consolidate possible_cpus array management in pc_cpu_plug()
>> > for smp_cpus, coldplugged with -device and hotplugged with
>> > device_add.
>>
>> So, this takes care of the h
Eduardo Habkost writes:
> On Wed, Jul 13, 2016 at 06:24:17PM -0400, Bandan Das wrote:
>> Igor Mammedov writes:
>>
>> > CPU added with device_add help won't have APIC ID set,
>> > so set it according to socket/core/thread ids provided
>> > with device_add command.
>> >
>> > Signed-off-by: Igor M
Igor Mammedov writes:
> Signed-off-by: Igor Mammedov
> ---
> target-i386/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 04c0b79..2fa445d 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2765,6 +2765,7 @@ static void x
Igor Mammedov writes:
> MAX_APICS is only used by child 'apic' class and not
> by its parent TYPE_APIC_COMMON or any other derived
> class.
> Move check into end user 'apic' class so it won't
> get in the way of other APIC implementations
> if they support more then MAX_APICS.
>
> Signed-off-by:
On Wed, Jul 13, 2016 at 06:32:27PM -0400, Bandan Das wrote:
> Igor Mammedov writes:
>
> > consolidate possible_cpus array management in pc_cpu_plug()
> > for smp_cpus, coldplugged with -device and hotplugged with
> > device_add.
>
> So, this takes care of the hotplug case and 09/19 took care of
On Wed, Jul 13, 2016 at 06:24:17PM -0400, Bandan Das wrote:
> Igor Mammedov writes:
>
> > CPU added with device_add help won't have APIC ID set,
> > so set it according to socket/core/thread ids provided
> > with device_add command.
> >
> > Signed-off-by: Igor Mammedov
> > ---
> > v3:
> > - use
Igor Mammedov writes:
> consolidate possible_cpus array management in pc_cpu_plug()
> for smp_cpus, coldplugged with -device and hotplugged with
> device_add.
So, this takes care of the hotplug case and 09/19 took care of the
coldplug case, right ? If yes, we should probably modify this commit
m
Igor Mammedov writes:
> CPU added with device_add help won't have APIC ID set,
> so set it according to socket/core/thread ids provided
> with device_add command.
>
> Signed-off-by: Igor Mammedov
> ---
> v3:
> - use %u for printing topo ids
> v2:
> - add validity checks for socket-id/core-id/t
Igor Mammedov writes:
> these properties will be used by as address where to plug
> CPU with help -device/device_add commands.
>
> Signed-off-by: Igor Mammedov
> ---
> v3:
> - use %u for printing topo ids
> - add to error message topo ids from set apic_id
> v2:
> - rename socket/core/threa
On Wed, Jul 13, 2016 at 2:09 PM, Peter Maydell wrote:
> On 13 July 2016 at 21:30, Alistair Francis
> wrote:
>> On Wed, Jul 13, 2016 at 12:44 PM, Peter Maydell
>> wrote:
>>> On 13 July 2016 at 18:45, Alistair Francis
>>> wrote:
On Tue, Jul 12, 2016 at 9:39 AM, Peter Maydell
wrote:
Igor Mammedov writes:
> Machine code knows about all possible APIC IDs so use that
> instead of hack which does O(n^2) complexity duplicate
> checks, interating over global CPUs list.
> As result duplicate check is done only once with O(log n) complexity.
>
> Signed-off-by: Igor Mammedov
> ---
>
I know some of these have already been pulled. I just have some minor
questions/comments that shouldn't conflict.
Igor Mammedov writes:
> Redo 9886e834 (target-i386: Require APIC ID to be explicitly set before
> CPU realize) in another way that doesn't use int64_t to detect
> if apic-id propert
On 13 July 2016 at 21:30, Alistair Francis wrote:
> On Wed, Jul 13, 2016 at 12:44 PM, Peter Maydell
> wrote:
>> On 13 July 2016 at 18:45, Alistair Francis
>> wrote:
>>> On Tue, Jul 12, 2016 at 9:39 AM, Peter Maydell
>>> wrote:
On 2 July 2016 at 02:07, Alistair Francis
wrote:
>
From: Sergey Fedorov
Use async_safe_run_on_cpu() to make tb_flush() thread safe.
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
---
Changes in v3:
- 'tb_flushed' removed
Changes in v2:
- stale comment about unsafe tb_flush() removed
---
cpu-exec.c| 14 +-
i
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
---
linux-user/main.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index 5ff0b20bad89..a8790ac63f68 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@
From: Sergey Fedorov
Make CPU work core functions common between system and user-mode
emulation. User-mode does not have BQL, so process_queued_cpu_work() is
protected by 'exclusive_lock'.
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
---
Changes in v2:
- 'qemu_work_cond' defin
From: Sergey Fedorov
Move the code common between run_on_cpu() and async_run_on_cpu() into a
new function queue_work_on_cpu().
Signed-off-by: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Reviewed-by: Alex Bennée
---
cpus.c | 42 ++
1 file changed, 18 i
On 07/07/2016 05:37 AM, Markus Armbruster wrote:
> Eric Blake writes:
>
>> When an unboxed event has accompanying data, we are exposing all
>> of its members alongside our local variables in the generated
>> qapi_event_send_FOO() function. So far, we haven't hit a
>> collision, but it may be a m
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