On 06/14/2016 08:15 AM, David Gibson wrote:
> On Mon, Jun 13, 2016 at 07:24:48AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
>> to it. This allows us to add a few more things such as disabling setting
>
On Tue, Jun 14, 2016 at 11:28:52AM +1000, David Gibson wrote:
> On Fri, Jun 10, 2016 at 07:40:13PM +0200, Andrew Jones wrote:
> > smp_parse computes missing smp options. Unfortunately cores and
> > threads are computed by dividing smp_cpus, instead of max_cpus.
> > This is incorrect because the top
On 06/14/2016 08:34 AM, David Gibson wrote:
> On Mon, Jun 13, 2016 at 07:24:51AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> Under some circumstances, we need to direct ISI and DSI interrupts
>> at the hypervisor, turning them into HISI/HDSI, and using different
>> SPRs (H
On Mon, Jun 13, 2016 at 07:24:51AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> Under some circumstances, we need to direct ISI and DSI interrupts
> at the hypervisor, turning them into HISI/HDSI, and using different
> SPRs (HDSISR and HDAR) depending on the combination of MS
On Mon, Jun 13, 2016 at 07:24:49AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> Properly implement LPES0/1 handling for HV vs. !HV mode.
>
> Signed-off-by: Benjamin Herrenschmidt
> [clg: AIL implementation was fixed in commit 5c94b2a5e5ef
> fixed checkpatch.pl errors
On Mon, Jun 13, 2016 at 07:24:48AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
> to it. This allows us to add a few more things such as disabling setting
> of MSR:HV and appropriate LPCR bits which will b
On 2016/5/26 22:55, Peter Maydell wrote:
> Implement the registers in the GICv3 CPU interface which generate
> new SGI interrupts.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Shannon Zhao
> ---
> hw/intc/arm_gicv3_cpuif.c | 125
> +
> hw/intc/a
On Tue, Jun 14, 2016 at 01:03:41PM +1000, David Gibson wrote:
> On Fri, Jun 10, 2016 at 07:40:21PM +0200, Andrew Jones wrote:
> > Use CPUState nr_cores,nr_threads and MachineState
> > cores,threads instead.
> >
> > Signed-off-by: Andrew Jones
> > ---
> > hw/ppc/spapr.c | 9 +
> > hw
On Tue, Jun 14, 2016 at 12:12:16PM +1000, David Gibson wrote:
> On Sun, Jun 12, 2016 at 03:48:10PM +0200, Andrew Jones wrote:
> > On Sat, Jun 11, 2016 at 08:54:35AM +0200, Thomas Huth wrote:
> > > On 10.06.2016 19:40, Andrew Jones wrote:
> > > > Signed-off-by: Andrew Jones
> > > > ---
> > > > qom
On Tue, Jun 14, 2016 at 12:00:26PM +1000, David Gibson wrote:
> On Fri, Jun 10, 2016 at 07:40:16PM +0200, Andrew Jones wrote:
> > Signed-off-by: Andrew Jones
> > ---
> > hw/core/machine.c | 81
> > +
> > include/hw/boards.h | 6
> > 2 f
On Tue, Jun 14, 2016 at 11:30:37AM +1000, David Gibson wrote:
> On Fri, Jun 10, 2016 at 07:40:15PM +0200, Andrew Jones wrote:
> > From: Igor Mammedov
> >
> > Signed-off-by: Igor Mammedov
> > Signed-off-by: Andrew Jones
>
> I think this needs some kind of rationale.
>
> Since with this patch i
From: Anton Blanchard
We need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so
add the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Anton Blanchard
Signed-off-by: David Gibson
---
include/elf.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/elf.h b/include/e
The following changes since commit 2c96c379ac7a22424c25d65b73e81b860f902868:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20160613-1' into
staging (2016-06-13 15:15:03 +0100)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.
From: Thomas Huth
The current pcr_mask values are ambiguous: Should these be the mask
that defines valid bits in the PCR register? Or should these rather
indicate which compatibility levels are possible? Anyway, POWER6 and
POWER7 should certainly not use the same values here. So let's
introduce a
From: Bharata B Rao
Memory hotplug can fail for some combinations of RAM and maxmem when
DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends
on maximum addressable memory returned by guest and this value is currently
being calculated wrongly by the guest kernel routine memory
From: Thomas Huth
Make sure that guests can use the PowerISA 2.07 CPU sPAPR
compatibility mode when they request it and the target CPU
supports it.
Signed-off-by: Thomas Huth
Signed-off-by: David Gibson
---
hw/ppc/spapr_hcall.c| 6 --
target-ppc/translate_init.c | 3 +++
2 files c
From: Thomas Huth
When using an olderr PowerISA level, all the upper compatibility
bits have to be enabled, too. For example when we want to run
something in PowerISA 2.05 compatibility mode on POWER8, the bit
for 2.06 has to be set beside the bit for 2.05.
Additionally, to make sure that we do n
From: Thomas Huth
The h_client_architecture_support() function has become quite big
and nested already. So factor out the code that takes care of the
sPAPR compatibility PVRs (which will be modified by the following
patches).
Signed-off-by: Thomas Huth
Reviewed-by: Michael Roth
Signed-off-by:
From: Mark Cave-Ayland
This ensures that the underlying memory is marked dirty once the transfer
is complete and resolves cache coherency problems under MacOS 9.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: David Gibson
---
hw/ide/macio.c | 46 ++-
From: Thomas Huth
When running with KVM, we might be interested in some details
of the host CPU class, too, so provide a function to get the
corresponding CPU class.
Signed-off-by: Thomas Huth
Reviewed-by: Michael Roth
Signed-off-by: David Gibson
---
target-ppc/kvm.c | 19 ++-
On Fri, 2016-06-10 at 11:42 +0100, Peter Maydell wrote:
> On 10 June 2016 at 01:59, Andrew Jeffery wrote:
> >
> > On Thu, 2016-06-09 at 19:15 +0100, Peter Maydell wrote:
> > >
> > > On 27 May 2016 at 06:08, Andrew Jeffery wrote:
> > > >
> > > >
> > > > Value matching allows Linux to boot with
On Mon, Jun 13, 2016 at 12:02:41PM +0200, Paolo Bonzini wrote:
>
>
> On 13/06/2016 04:21, Chao Peng wrote:
> > KVM_GET_SUPPORTED_CPUID ioctl is called frequently when initializing
> > CPU. Depends on CPU features and CPU count, the number of calls can be
> > extremely high which slows down QEMU b
On 06/07/2016 04:08 AM, Kevin Wolf wrote:
>> Found it; squash this in (or use it as an argument why we don't want
>> request_alignment in bs->bl after all):
>
> This hunk doesn't make sense to me. For the correctness of the code it
> shouldn't make a difference whether the alignment happens befor
On 2016年06月13日 16:35, Aurelien Jarno wrote:
On 2016-06-02 10:28, Peter Maydell wrote:
On 2 June 2016 at 07:44, P J P wrote:
From: Prasad J Pandit
When processing MIPSnet I/O port write operation, it uses a
transmit buffer tx_buffer[MAX_ETH_FRAME_SIZE=1514]. Two indices
's->tx_written' and
Hi Mark,
Attached is the new link:
https://mega.nz/#!94ZVXBra!8QMsQ2d9eKKkMuawg_0YelfyWTy47CyyD1f6tvSv1bQ
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https://bugs.launchpad.net/bugs/1588328
Title:
Qemu 2.6 Solaris 9 Sparc Segm
On Fri, Jun 10, 2016 at 10:44:48AM +0530, Bharata B Rao wrote:
> Memory hotplug can fail for some combinations of RAM and maxmem when
> DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends
> on maximum addressable memory returned by guest and this value is currently
> being calc
On 2016/5/26 22:55, Peter Maydell wrote:
> From: Shlomo Pongratz
>
> Implement the redistributor registers of a GICv3.
>
> Signed-off-by: Shlomo Pongratz
> [PMM: significantly overhauled/rewritten:
> * use the new data structures
> * restructure register read/write to handle different width
On Fri, Jun 10, 2016 at 07:40:21PM +0200, Andrew Jones wrote:
> Use CPUState nr_cores,nr_threads and MachineState
> cores,threads instead.
>
> Signed-off-by: Andrew Jones
> ---
> hw/ppc/spapr.c | 9 +
> hw/ppc/spapr_rtas.c | 2 +-
> 2 files changed, 6 insertions(+), 5 deletions(-)
>
On Sun, Jun 12, 2016 at 03:48:10PM +0200, Andrew Jones wrote:
> On Sat, Jun 11, 2016 at 08:54:35AM +0200, Thomas Huth wrote:
> > On 10.06.2016 19:40, Andrew Jones wrote:
> > > Signed-off-by: Andrew Jones
> > > ---
> > > qom/cpu.c | 8
> > > 1 file changed, 8 insertions(+)
> > >
> > > di
On Fri, Jun 10, 2016 at 07:40:16PM +0200, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
> ---
> hw/core/machine.c | 81
> +
> include/hw/boards.h | 6
> 2 files changed, 87 insertions(+)
>
> diff --git a/hw/core/machine.c b/hw/core
On 2016/5/26 22:55, Peter Maydell wrote:
> The GICv3 CPU interface needs to know when the CPU it is attached
> to makes an exception level or mode transition that changes the
> security state, because whether it is asserting IRQ or FIQ can change
> depending on these things. Provide a mechanism f
On Fri, Jun 10, 2016 at 07:40:13PM +0200, Andrew Jones wrote:
> smp_parse computes missing smp options. Unfortunately cores and
> threads are computed by dividing smp_cpus, instead of max_cpus.
> This is incorrect because the topology doesn't leave room for
> hotplug. More unfortunately, we can't c
On Fri, Jun 10, 2016 at 07:40:15PM +0200, Andrew Jones wrote:
> From: Igor Mammedov
>
> Signed-off-by: Igor Mammedov
> Signed-off-by: Andrew Jones
I think this needs some kind of rationale.
Since with this patch it is called immediately before ->init, I'm not
really seeing the point of this.
On Fri, Jun 10, 2016 at 07:40:12PM +0200, Andrew Jones wrote:
> No functional changes; only some code movement and removal of
> dead code (impossible conditions). Also, max_cpus can be
> initialized to 1, like smp_cpus, because it's either set by the
> user or set to smp_cpus, when smp_cpus is set
On Mon, 06/13 17:33, John Snow wrote:
>
>
> On 06/12/2016 02:56 AM, Fam Zheng wrote:
> > We only care about the associated backend, so blk_drain is more
> > appropriate here.
> >
> > Signed-off-by: Fam Zheng
> > ---
> > hw/ide/macio.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Mon, 06/13 11:39, Kevin Wolf wrote:
> Am 12.06.2016 um 08:56 hat Fam Zheng geschrieben:
> > We only care about the associated backend, so blk_drain is more
> > appropriate here.
> >
> > Signed-off-by: Fam Zheng
>
> [ Cc: John ]
>
> > ---
> > hw/ide/macio.c | 2 +-
> > 1 file changed, 1 inse
> * Li, Liang Z (liang.z...@intel.com) wrote:
> > > Because writing to this file is a nondestructive operation and dirty
> > > objects are not freeable, the user should run sync(1) first.
> > > [/quote]
> > >
> > > IOW, by 'slab' you mean dentries and inodes ?
> > >
> > Yes.
> >
> > > > +##
> > > >
On Mon, Jun 13, 2016 at 03:10:29PM +0200, Gerd Hoffmann wrote:
> From: Eduardo Habkost
>
> This wrapper for machine_usb(current_machine) is not necessary,
> replace all usages of usb_enabled() with machine_usb().
>
> Cc: Peter Maydell
> Cc: "Michael S. Tsirkin"
> Cc: Alexander Graf
> Cc: qemu
On Fri, Jun 10, 2016 at 07:26:37PM +0100, Mark Cave-Ayland wrote:
> This ensures that the underlying memory is marked dirty once the transfer
> is complete and resolves cache coherency problems under MacOS 9.
>
> Signed-off-by: Mark Cave-Ayland
Applied to ppc-for-2.7, thanks.
> ---
> hw/ide/ma
The architecture manual is unclear about this, but the or1ksim
does writeback before the exception. This requires splitting
the helpers in half, with the exception raised by the second.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/fpu_helper.c | 252
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 348 ++--
1 file changed, 173 insertions(+), 175 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index cb9267d..4d29d22 100644
--- a/target-openrisc/tran
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 31f4307..3102190 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@
Signed-off-by: Richard Henderson
---
target-openrisc/cpu.h| 12 +---
target-openrisc/gdbstub.c| 2 +-
target-openrisc/interrupt.c | 4 ++--
target-openrisc/sys_helper.c | 2 +-
target-openrisc/translate.c | 40
5 files changed, 25
True, this is unused so far, but commented out is worse than
actually implemented properly.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/int_helper.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-open
Signed-off-by: Richard Henderson
---
linux-user/main.c | 45
target-openrisc/cpu.c | 1 +
target-openrisc/cpu.h | 9 +
target-openrisc/interrupt.c| 1 +
target-openrisc/interrupt_helper.c | 1 +
target-openrisc/mm
The NPC SPR is really only supposed to be used for FPGA debugging.
It contains the same contents as PC, unless one plays games. Follow
the or1ksim implementation in flushing delayed branch state when it
is changed.
The PPC SPR need not be updated every instruction, merely when we
exit the TB or a
The architecture manual is consistent in using "I" for signed
fields and "K" for unsigned fields. Mirror that.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 200 +---
1 file changed, 75 insertions(+),
This allows the tcg optimizer to see, and fold, all of the
constants involved in a GOT base register load sequence.
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target-openrisc/translate.c b/target-openr
Signed-off-by: Richard Henderson
---
target-openrisc/cpu.h | 5 +++-
target-openrisc/exception_helper.c | 1 +
target-openrisc/translate.c| 47 ++
3 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/target-openrisc/cpu.h b/targ
The architecture manual doesn't say these opcodes are user only.
Leaving them disabled excludes user mode from accessing interesting
SPRs like MACLO/MACHI.
Signed-off-by: Richard Henderson
---
target-openrisc/helper.h | 4 +--
target-openrisc/sys_helper.c | 77 +-
Not part of the v1.1 standard, but a proposed extension
to vastly simplify both PIC and 64-bit mode.
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate
This significantly streamlines carry and overflow production.
Signed-off-by: Richard Henderson
---
target-openrisc/cpu.h | 13 +++-
target-openrisc/exception_helper.c | 33 ---
target-openrisc/helper.h | 4 +-
target-openrisc/translate.c| 118 ++
This avoids having to keep merging and extracting the flag from SR.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/cpu.h | 15 +-
target-openrisc/gdbstub.c | 4 +-
target-openrisc/interrupt.c| 2 +-
target-openrisc/interr
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/helper.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
index 136ec39..4b0a935 100644
--- a/target-openrisc
Note that the specification for lf.madd.s is confused. It's
the only mention of supposed FPMADDHI/FPMADDLO special registers.
On the other hand, or1ksim implements a somewhat normal non-fused
multiply and add. Mirror that.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
t
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 54 +++--
1 file changed, 28 insertions(+), 26 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 4d29d22..be95248 100644
--- a/target-openrisc/transl
Simplify overflow calculation. Move overflow exception check
to a helper function, to eliminate inline branches. Remove
some incorrect special casing of R0. Implement multiply inline.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/exception_helper.c | 1
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 2421b92..48bd5f7 100644
--- a/target
Significantly simplifies the implementation of the use of MAC.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/cpu.h| 3 +-
target-openrisc/sys_helper.c | 13 +
target-openrisc/translate.c | 120 +++
3
Removes a call at execution time for overflow exceptions.
Signed-off-by: Richard Henderson
---
target-openrisc/cpu.h | 4 ++--
target-openrisc/exception_helper.c | 2 +-
target-openrisc/translate.c| 24 +++-
3 files changed, 18 insertions(+), 12 deletio
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 106
1 file changed, 106 insertions(+)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index d028612..4ce51ea 100644
--- a/targe
This is an update of a patch set last posted in September,
and partially reviewed by Bastian at the time.
r~
Richard Henderson (25):
target-openrisc: Always enable OPENRISC_DISAS
target-openrisc: Streamline arithmetic and OVE
target-openrisc: Invert the decoding in dec_calc
target-openr
Not documented as disabled for user mode.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 32
1 file changed, 32 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 4dde531
Avoids warnings from unused variables etc.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index c
Decoding the opcodes in the right order reduces by 100+ lines.
Also, it happens to put the opcodes in the same order as Chapter 17.
Reviewed-by: Bastian Koppelmann
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 300 ++--
1 file changed
We've used older versions of QEMU for several years as a virtual
target for our OS. Many thanks to the community for providing this
platform.
We've been working to get our OS running under QEMU 2.x and have
identified a few bugs in QEMU, have made some enhancements, and are
still tracking down so
On Mon, Jun 13, 2016 at 04:16:02PM +0100, Peter Maydell wrote:
> On 13 June 2016 at 15:45, Daniel P. Berrange wrote:
> > On Mon, Jun 13, 2016 at 03:11:08PM +0100, Peter Maydell wrote:
> >> QEMU currently allocates coroutine stacks with a plain g_malloc(),
> >> which makes them r/w but not exec. T
On 06/13/2016 03:57 PM, Eduardo Habkost wrote:
> This patch simplifies code that uses a local_err variable just to
> immediately use it for an error_propagate() call.
>
> Coccinelle patch used to perform the changes added to
> scripts/coccinelle/remove_local_err.cocci.
>
> Reviewed-by: Eric Blake
On 13 June 2016 at 23:38, Richard Henderson wrote:
> On 06/13/2016 03:28 PM, Peter Maydell wrote:
>> glibc's syscall() takes the system parameter as an int and
>> does a sign-extending move into x0 with an uxtw.
>> safe_syscall() takes a long, so it's already 64 bits.
>
>
> Well, uxtw is a zero-ex
On 06/13/2016 03:28 PM, Peter Maydell wrote:
On 13 June 2016 at 23:21, Richard Henderson wrote:
On 06/13/2016 03:04 PM, Peter Maydell wrote:
+.global safe_syscall_base
+.global safe_syscall_start
+.global safe_syscall_end
+.type safe_syscall_base, #function
+
On 13 June 2016 at 23:21, Richard Henderson wrote:
> On 06/13/2016 03:04 PM, Peter Maydell wrote:
>>>
>>> +.global safe_syscall_base
>>> +.global safe_syscall_start
>>> +.global safe_syscall_end
>>> +.type safe_syscall_base, #function
>>> +.type safe_sys
On 13 June 2016 at 23:28, Peter Maydell wrote:
> glibc's syscall() takes the system parameter as an int and
> does a sign-extending move into x0 with an uxtw.
...zero-extending...
-- PMM
On 13 June 2016 at 22:45, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/ppc64/hostdep.h | 34 +
> linux-user/host/ppc64/safe-syscall.inc.S | 87
>
> 2 files changed, 121 insertions(+)
> create mode 1006
On 06/13/2016 03:04 PM, Peter Maydell wrote:
+.global safe_syscall_base
+.global safe_syscall_start
+.global safe_syscall_end
+.type safe_syscall_base, #function
+.type safe_syscall_start, #function
+.type safe_syscall_end, #function
_start
On 13 June 2016 at 22:53, Peter Maydell wrote:
> On 13 June 2016 at 22:45, Richard Henderson wrote:
>> Richard Henderson (6):
>> linux-user: fix x86_64 safe_syscall
>> linux-user: Provide safe_syscall for i386
>> linux-user: Provide safe_syscall for arm
>> linux-user: Provide safe_syscall
On 06/13/2016 02:26 AM, Peter Maydell wrote:
Currently our configure script allows linux-user targets to be built
for "unknown" host CPU architectures (which must be using the TCI
interpreter). However, code like user-exec.c has host-architecture
#ifdef ladders which in practice mean you can't bu
On 13 June 2016 at 22:45, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/aarch64/hostdep.h | 34 ++
> linux-user/host/aarch64/safe-syscall.inc.S | 72
> ++
> 2 files changed, 106 insertions(+)
> create mode 1
This patch simplifies code that uses a local_err variable just to
immediately use it for an error_propagate() call.
Coccinelle patch used to perform the changes added to
scripts/coccinelle/remove_local_err.cocci.
Reviewed-by: Eric Blake
Acked-by: Cornelia Huck
Signed-off-by: Eduardo Habkost
--
Use Coccinelle script to replace 'ret = E; return ret' with
'return E'. The script will do the substitution only when the
function return type and variable type are the same.
Sending as RFC because the patch looks more intrusive than the
others. Probably better to split it per subsystem and let ea
Changes v1 -> v2:
* The Coccinelle scripts were simplified by using "when"
constraints to detect when a variable is not used elsewhere
inside the function.
* Added script to remove unnecessary variables for function
return value.
* Coccinelle scripts added to scripts/coccinelle.
Changes v2
error_propagate() already ignores local_err==NULL, so there's no
need to check it before calling.
Coccinelle patch used to perform the changes added to
scripts/coccinelle/error_propagate_null.cocci.
Reviewed-by: Eric Blake
Acked-by: Cornelia Huck
Reviewed-by: Markus Armbruster
Signed-off-by: E
the latest commit i can works with with qemu is 70f87e0
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https://bugs.launchpad.net/bugs/1589272
Title:
qemu-system-x86_64: There is no option group 'vnc'
Status in QEMU:
New
Bug d
Signed-off-by: Richard Henderson
---
linux-user/host/i386/hostdep.h | 34 ++
linux-user/host/i386/safe-syscall.inc.S | 110
2 files changed, 144 insertions(+)
create mode 100644 linux-user/host/i386/hostdep.h
create mode 100644 linux-user/host/
On 13 June 2016 at 22:45, Richard Henderson wrote:
> We added support for x86_64 in 4d330cee37a2; this adds support
> for 5 more hosts. Also, tweak the signal_pending test for x86_64.
>
>
> r~
>
>
> Richard Henderson (6):
> linux-user: fix x86_64 safe_syscall
> linux-user: Provide safe_syscal
Signed-off-by: Richard Henderson
---
linux-user/host/arm/hostdep.h | 34 ++
linux-user/host/arm/safe-syscall.inc.S | 86 ++
2 files changed, 120 insertions(+)
create mode 100644 linux-user/host/arm/hostdep.h
create mode 100644 linux-user/host
Signed-off-by: Richard Henderson
---
linux-user/host/ppc64/hostdep.h | 34 +
linux-user/host/ppc64/safe-syscall.inc.S | 87
2 files changed, 121 insertions(+)
create mode 100644 linux-user/host/ppc64/hostdep.h
create mode 100644 linux-user/h
any notice of this?
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https://bugs.launchpad.net/bugs/1589272
Title:
qemu-system-x86_64: There is no option group 'vnc'
Status in QEMU:
New
Bug description:
build qemu from git (6
Signed-off-by: Richard Henderson
---
linux-user/host/s390x/hostdep.h | 34 +
linux-user/host/s390x/safe-syscall.inc.S | 87
2 files changed, 121 insertions(+)
create mode 100644 linux-user/host/s390x/hostdep.h
create mode 100644 linux-user/h
Do what the comment says, test for signal_pending non-zero,
rather than the current coe which tests for bit 0 non-zero.
Signed-off-by: Richard Henderson
---
linux-user/host/x86_64/safe-syscall.inc.S | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/linux-user/host/x86_64/
Signed-off-by: Richard Henderson
---
linux-user/host/aarch64/hostdep.h | 34 ++
linux-user/host/aarch64/safe-syscall.inc.S | 72 ++
2 files changed, 106 insertions(+)
create mode 100644 linux-user/host/aarch64/hostdep.h
create mode 100644 linux-u
We added support for x86_64 in 4d330cee37a2; this adds support
for 5 more hosts. Also, tweak the signal_pending test for x86_64.
r~
Richard Henderson (6):
linux-user: fix x86_64 safe_syscall
linux-user: Provide safe_syscall for i386
linux-user: Provide safe_syscall for arm
linux-user:
On 13 Jun 2016, at 13:25, Eric Blake wrote:
> On 06/13/2016 06:10 AM, Paolo Bonzini wrote:
>>
>>
>> On 12/05/2016 00:39, Eric Blake wrote:
>>> - If we report an error to NBD_CMD_READ, we are not writing out
>>> any data payload; but the protocol says that a client can expect
>>> to read the pa
On 05/09/2016 08:47 AM, Stefan Hajnoczi wrote:
> v2:
> * Fix missing s/X/(1u << X)/ conversion in Patch 3 [Marc]
>
> This patch series eliminates code duplication in libqos virtio.
> include/standard-headers/ contains the Linux virtio header files so we don't
> need to define our own version of
On Mon, Jun 13, 2016 at 01:29:47PM +0200, Markus Armbruster wrote:
> Eduardo Habkost writes:
>
> > Use Coccinelle script to replace 'ret = E; return ret' with
> > 'return E'. The script will do the substitution only when the
> > function return type and variable type are the same.
> >
> > Sending
On 06/12/2016 02:56 AM, Fam Zheng wrote:
> We only care about the associated backend, so blk_drain is more
> appropriate here.
>
> Signed-off-by: Fam Zheng
> ---
> hw/ide/macio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ide/macio.c b/hw/ide/macio.c
> index 7
On 06/13/2016 01:25 PM, Michael Rolnik wrote:
what is the difference between tcg_gen_qemu_st16 and tcg_gen_qemu_st_tl
st16 is a legacy interface; st_tl is newer and has an argument that is a mask
of MO_* bits. MO_BEUW is a convenience name for MO_BE | MO_16.
r~
From: Xiao Guangrong
It describes the basic concepts of NVDIMM ACPI and the interfaces
between QEMU and the ACPI BIOS
Signed-off-by: Xiao Guangrong
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
docs/specs/acpi_nvdimm.txt | 132 +++
From: Xiao Guangrong
Function 5 is used to get Namespace Label Data
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Xiao Guangrong
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/acpi/nvdimm.c | 83 ++
On Fri, Jun 10, 2016 at 4:53 AM, Peter Maydell wrote:
> On 9 June 2016 at 01:30, Alistair Francis wrote:
>> On Thu, May 12, 2016 at 3:45 PM, Alistair Francis
>> wrote:
>>> This patch series is based on Peter C's original register API. His
>>> original cover letter is below.
>>
>> Ping!
>
> I've
On Thu, Jun 9, 2016 at 11:55 AM, Peter Maydell wrote:
> On 12 May 2016 at 23:45, Alistair Francis wrote:
>> This API provides some encapsulation of registers and factors our some
>
> "out"
>
>> common functionality to common code. Bits of device state (usually MMIO
>> registers), often have all s
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