On 2016/4/25 1:28, Andrew Jones wrote:
> On Sat, Apr 23, 2016 at 06:04:14PM +0800, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > Add a virtual PMU device for virt machine while use PPI 7 for PMU
>> > overflow interrupt number.
>> >
>> > Signed-off-by: Shannon Zhao
>> > ---
>> > hw/ar
On (Tue) 19 Apr 2016 [22:34:32], Liang Li wrote:
> Current QEMU live migration implementation mark all guest's RAM pages
> as dirtied in the ram bulk stage, all these pages will be processed
> and it consumes quite a lot of CPU cycles and network bandwidth.
>
> From guest's point of view, it doesn
On 2016-04-19 10:38, Peter Xu wrote:
> Jan, Michael,
>
> Still haven't got your response from v3 review comments, but I
> decided to move on to provide a workable version first (v3 is
> missing the first patch, so it is not working). Also, misc issues
> are addressed from Radim. Anyway, I am alway
On 2016-04-18 10:55, Peter Xu wrote:
> On Sun, Apr 17, 2016 at 12:45:03PM +0300, Michael S. Tsirkin wrote:
>> On Sat, Apr 16, 2016 at 07:44:12PM -0700, Jan Kiszka wrote:
>>> On 2016-04-14 20:31, Peter Xu wrote:
> [...]
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 84e8948..b993bd
This patch adds check for negative return value from get_image_size(),
where it is missing. It avoids unnecessary two function calls.
Signed-off-by: Zhou Jie
---
hw/ppc/spapr.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index feaab08..ccea633 100644
-
> On Fri, Apr 22, 2016 at 10:48:38AM +0100, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Tue, Apr 19, 2016 at 03:02:09PM +, Li, Liang Z wrote:
> > > > > On Tue, 2016-04-19 at 22:34 +0800, Liang Li wrote:
> > > > > > The free page bitmap will be sent t
On Mon, Apr 25, 2016 at 01:12:57AM +0300, David Kiarie wrote:
> Add AMD IOMMU emulation support to q35 chipset
>
> Signed-off-by: David Kiarie
> ---
> hw/pci-host/q35.c | 21 +++--
> include/hw/i386/intel_iommu.h | 2 +-
> 2 files changed, 20 insertions(+), 3 deletio
On Mon, Apr 25, 2016 at 01:12:56AM +0300, David Kiarie wrote:
> Added a bool, subject to review to machine properties which
> it used to override iommu emulated from Intel to AMD.
>
> Signed-off-by: David Kiarie
> ---
> hw/core/machine.c | 32 +---
> inclu
On Fri, 04/22 18:55, Matthew Schumacher wrote:
> Running master as of this morning 4/22 and I'm not getting any more
> crashes, and I'm flat beating on it. RC3 still crashes on me, so
> whatever the fix is, came after rc3.
Matthew, It was bcd82a9..ab27c3b from last Friday (yes, after -rc3).
Than
On Fri, 04/22 08:23, Janne Karhunen wrote:
> On Wed, Apr 20, 2016 at 9:44 PM, Fam Zheng wrote:
>
> >> That's certainly doable and kind of makes sense, but I'm not entirely
> >> sure that compat6 flag makes any sense to begin with. Does it?
> >
> > I don't know VMware products well enough to tell,
On Fri, 04/22 21:57, Jason Dillaman wrote:
> Since this cannot automatically recover from a crashed QEMU client with an
> RBD image, perhaps this RBD locking should not default to enabled.
> Additionally, this will conflict with the "exclusive-lock" feature
> available since the Ceph Hammer-release
On 04/21/2016 05:01 PM, Emilio G. Cota wrote:
Signed-off-by: Emilio G. Cota
---
translate-all.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Applied to tcg-next. Thanks.
r~
On 04/21/2016 05:01 PM, Emilio G. Cota wrote:
The setting of tcg_ctx.code_gen_buffer_size is done by the only caller of
size_code_gen_buffer(), which is code_gen_alloc():
$ git grep size_code_gen_buffer
translate-all.c:static inline size_t size_code_gen_buffer(size_t tb_size)
translate-
Sorry, I keep missing Jan's email...
On Mon, Apr 25, 2016 at 1:12 AM, David Kiarie wrote:
> Hi all,
>
> The current AMD IOMMU patches that fixes Igor's comments. I got rid of
> structs and instead
> added individual integer fields into the table data directly, as suggested.
>
> I have also got r
Add AMD IOMMU emulation support to q35 chipset
Signed-off-by: David Kiarie
---
hw/pci-host/q35.c | 21 +++--
include/hw/i386/intel_iommu.h | 2 +-
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 70f897e..37f
Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU
The IOMMU does basic translation, error checking and has a
minimal IOTLB implementation
Signed-off-by: David Kiarie
---
hw/i386/Makefile.objs |1 +
hw/i386/amd_iommu.c | 1426 +
hw/i38
Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
depending on emulated IOMMU
Signed-off-by: David Kiarie
---
hw/acpi/aml-build.c | 2 +-
hw/acpi/core.c | 13 --
hw/i386/acpi-build.c| 101 +++-
include/hw/acpi/acpi-def
Hi all,
The current AMD IOMMU patches that fixes Igor's comments. I got rid of structs
and instead
added individual integer fields into the table data directly, as suggested.
I have also got rid of some un-used macros and fixed a few other miscellaneous
things.
David Kiarie (4):
hw/i386: I
Added a bool, subject to review to machine properties which
it used to override iommu emulated from Intel to AMD.
Signed-off-by: David Kiarie
---
hw/core/machine.c | 32 +---
include/hw/boards.h | 1 +
include/hw/i386/intel_iommu.h | 1 +
qemu-
On Sun, Apr 24, 2016 at 12:46:08 -0700, Richard Henderson wrote:
> On 04/22/2016 04:57 PM, Emilio G. Cota wrote:
> >On Fri, Apr 22, 2016 at 12:59:52 -0700, Richard Henderson wrote:
> >>FWIW, so that I could get an idea of how the stats change as we improve the
> >>hashing, I inserted the attachment
On Sun, Apr 24, 2016 at 13:01:31 -0700, Richard Henderson wrote:
> On 04/19/2016 04:07 PM, Emilio G. Cota wrote:
> >+static void qht_insert__locked(struct qht *ht, struct qht_map *map,
> >+ struct qht_bucket *head, void *p, uint32_t
> >hash)
> >+{
> >+struct qht_b
On 04/22/2016 09:08 AM, Sergey Fedorov wrote:
When patching translated code for direct block chaining/unchaining,
modification of concurrently executing code can happen in multi-threaded
execution. Currently only user-mode is affected. To make direct block patching
safe, some care must be taken
** Changed in: qemu
Status: New => Confirmed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1574346
Title:
TCG: mov to segment register is incorrectly emulated for AMD CPUs
Status in QEMU:
On 04/19/2016 04:07 PM, Emilio G. Cota wrote:
+static void qht_insert__locked(struct qht *ht, struct qht_map *map,
+ struct qht_bucket *head, void *p, uint32_t hash)
+{
+struct qht_bucket *b = head;
+struct qht_bucket *prev = NULL;
+struct qht_bucket *new
On 04/22/2016 04:57 PM, Emilio G. Cota wrote:
On Fri, Apr 22, 2016 at 12:59:52 -0700, Richard Henderson wrote:
FWIW, so that I could get an idea of how the stats change as we improve the
hashing, I inserted the attachment 1 patch between patches 5 and 6, and with
attachment 2 attempting to fix t
On 04/23/2016 08:27 PM, Emilio G. Cota wrote:
[ Applies on top of bennee/mttcg/enable-mttcg-for-armv7-v1 after
reverting "translate-all: introduces tb_flush_safe". A trivial
conflict must be solved after applying. ]
This is a first attempt at making tb_flush not have to stop all CPUs.
There are
Public bug reported:
In TCG mode, the effect of:
xorl %eax, %eax
movl %eax, %gs
is to mark the GS segment unusable and set its base to zero. After
doing this, reading MSR_GS_BASE will return zero and using a GS prefix
in long mode will treat the GS base as zero.
This is correct for Intel CPUs
On Fri, 22 Apr 2016 14:02:28 +0100
"Richard W.M. Jones" wrote:
> From: Marc Marí
>
> This optionrom is based on linuxboot.S.
>
> Signed-off-by: Marc Marí
> Signed-off-by: Richard W.M. Jones
> ---
> .gitignore| 4 +
> hw/i386/pc.c | 9 +-
> hw
On Sat, Apr 23, 2016 at 06:04:15PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add PMU IRQ number in ACPI table, then we can use PMU in guest through
> ACPI.
>
> Signed-off-by: Shannon Zhao
> ---
> hw/arm/virt-acpi-build.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Andrew
On Sat, Apr 23, 2016 at 06:04:14PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add a virtual PMU device for virt machine while use PPI 7 for PMU
> overflow interrupt number.
>
> Signed-off-by: Shannon Zhao
> ---
> hw/arm/virt.c | 31 +++
> include/hw
On Sat, Apr 23, 2016 at 06:04:13PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Check if kvm supports guest PMUv3. If so, set the corresponding feature
> bit for vcpu.
>
> Signed-off-by: Shannon Zhao
> ---
> target-arm/cpu-qom.h | 2 ++
> target-arm/kvm64.c | 5 +
> 2 files change
On Sat, Apr 23, 2016 at 05:06:31PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add NUMA support for machine virt. Tested successfully running a guest
> Linux kernel with the following patch applied:
>
> - [PATCH v16 0/6] arm64, numa: Add numa support for arm64 platforms
> https://lkml.or
On Sat, Apr 23, 2016 at 05:06:36PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> To support NUMA, it needs to generate SRAT ACPI table.
>
> Signed-off-by: Shannon Zhao
> ---
> hw/arm/virt-acpi-build.c | 52
>
> 1 file changed, 52 insertio
On Sat, Apr 23, 2016 at 05:06:35PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Move acpi_build_srat_memory to common place so that it could be reused
> by ARM.
>
> Cc: Michael S. Tsirkin
> Cc: Igor Mammedov
> Signed-off-by: Shannon Zhao
> ---
> hw/acpi/aml-build.c | 12 ++
On Sat, Apr 23, 2016 at 05:06:33PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> When specifying NUMA for ARM machine, generate /memory node according to
> NUMA topology.
>
> Signed-off-by: Shannon Zhao
> ---
> hw/arm/boot.c | 43 +--
> 1 file chan
Public bug reported:
qemu-system-x86_64 -net nic,model=help
output comes to stderr instead of std
qemu-system-x86_64 -net nic,model=help -> stdout
qemu-system-x86_64 -machine help -> stdout
qemu-system-x86_64 -cpu help -> stdout
as of
https://github.com/qemu/qemu/blob/044d65525f6ac2093042ae18
Public bug reported:
QEMU 2.5.0, SeaBIOS 1.9.1; I've been noticing this bug for quite a
while, though.
Steps to reproduce:
# Create a VM image, install DOS in it (doesn't matter which) and launch it.
# Launch a "bare DOS" DPMI host (not an operating system) in it; I tested with
CWSDPMI and HDPM
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