Public bug reported:
In TCG mode, the effect of:
xorl %eax, %eax
movl %eax, %gs
is to mark the GS segment unusable and set its base to zero. After
doing this, reading MSR_GS_BASE will return zero and using a GS prefix
in long mode will treat the GS base as zero.
This is correct for Intel CPUs but is incorrect for AMD CPUs. On an AMD
CPU, writing 0 to %gs using mov, pop, or (I think) lgs will leave the
base unchanged.
To make it easier to use TCG to validate behavior on different CPUs,
please consider changing the TCG behavior to match actual CPU behavior
when emulating an AMD CPU.
** Affects: qemu
Importance: Undecided
Status: New
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https://bugs.launchpad.net/bugs/1574346
Title:
TCG: mov to segment register is incorrectly emulated for AMD CPUs
Status in QEMU:
New
Bug description:
In TCG mode, the effect of:
xorl %eax, %eax
movl %eax, %gs
is to mark the GS segment unusable and set its base to zero. After
doing this, reading MSR_GS_BASE will return zero and using a GS prefix
in long mode will treat the GS base as zero.
This is correct for Intel CPUs but is incorrect for AMD CPUs. On an
AMD CPU, writing 0 to %gs using mov, pop, or (I think) lgs will leave
the base unchanged.
To make it easier to use TCG to validate behavior on different CPUs,
please consider changing the TCG behavior to match actual CPU behavior
when emulating an AMD CPU.
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https://bugs.launchpad.net/qemu/+bug/1574346/+subscriptions
