> Am 14.09.2015 um 08:38 schrieb Fam Zheng :
>
>> On Fri, 09/11 08:27, ronnie sahlberg wrote:
>>> On Fri, Sep 11, 2015 at 8:20 AM, Eric Blake wrote:
On 09/11/2015 12:00 AM, Fam Zheng wrote:
Previously we use "-iscsi id=target-iqn,user=foo,password=bar,..." to
specify iscsi connec
On Fri, 09/11 08:27, ronnie sahlberg wrote:
> On Fri, Sep 11, 2015 at 8:20 AM, Eric Blake wrote:
> > On 09/11/2015 12:00 AM, Fam Zheng wrote:
> >> Previously we use "-iscsi id=target-iqn,user=foo,password=bar,..." to
> >> specify iscsi connection parameters, unfortunately it doesn't work with
> >>
On 14/09/15 04:15, David Gibson wrote:
> On Fri, Sep 11, 2015 at 11:17:01AM +0200, Thomas Huth wrote:
>> The PAPR interface defines a hypercall to pass high-quality
>> hardware generated random numbers to guests. Recent kernels can
>> already provide this hypercall to the guest if the right hardwar
On Mon, Sep 14, 2015 at 11:41:52AM +1000, David Gibson wrote:
> The sPAPRDRConnector pseudo-device contains an owner field which is
> set in spapr_dr_connector_new(). However, that function also calls
> object_property_add_child() to set the DRConnector as the QOM child of
> the owner object. Tha
On Fri 11 Sep 2015 07:33:41 PM CEST, Max Reitz wrote:
>>> So why do we need the new flag? Because "backing: ''" is ugly?
>>
>> I guess it's just because you're the only one who actually reads the
>> documentation. When discussing this, I didn't remember that we
>> already had a way to express th
On Thu, Sep 10, 2015 at 02:54:02PM +0800, Jason Wang wrote:
>
>
> On 09/10/2015 02:18 PM, Yuanhan Liu wrote:
> > On Thu, Sep 10, 2015 at 01:52:30PM +0800, Jason Wang wrote:
> >>
> >> On 09/10/2015 01:17 PM, Yuanhan Liu wrote:
> >>> On Thu, Sep 10, 2015 at 12:46:00PM +0800, Jason Wang wrote:
> >>>
On 09/14/2015 01:22 PM, Jason Wang wrote:
On 09/14/2015 01:09 PM, Yang Hongyang wrote:
Hi Stefan,Jason,
I've convert this series to base on QOM, and introducing NetQueue apis
instead of using Netqueue internals as Stefan suggested. Could you
please take a
look at it?
Will go through this
On 09/14/2015 01:09 PM, Yang Hongyang wrote:
> Hi Stefan,Jason,
>
> I've convert this series to base on QOM, and introducing NetQueue apis
> instead of using Netqueue internals as Stefan suggested. Could you
> please take a
> look at it?
Will go through this in next few days.
> Most of the deta
On Mon, Sep 14, 2015 at 10:11:50AM +0530, Bharata B Rao wrote:
> On Mon, Sep 14, 2015 at 02:14:59PM +1000, David Gibson wrote:
> > On Mon, Sep 14, 2015 at 09:37:16AM +0530, Bharata B Rao wrote:
> > > On Mon, Sep 14, 2015 at 11:41:53AM +1000, David Gibson wrote:
> > > > The dynamic reconfiguration (
On Fri, Sep 11, 2015 at 7:51 AM, Markus Armbruster wrote:
> Not nice:
>
> $ qemu-system-x86_64 -m 1000
> Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
> upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
> Aborted (core dumped)
>
On Fri, Sep 11, 2015 at 7:51 AM, Markus Armbruster wrote:
> Symptom:
>
> $ qemu-system-x86_64 -m 1000
> Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
> upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
> Aborted (core dumped)
>
>
Hi Stefan,Jason,
I've convert this series to base on QOM, and introducing NetQueue apis
instead of using Netqueue internals as Stefan suggested. Could you please take a
look at it?
Most of the details have been reviewed by Jason, and the whole filter logic
isn't changed.
One missing feature compa
On Mon, Sep 14, 2015 at 02:14:59PM +1000, David Gibson wrote:
> On Mon, Sep 14, 2015 at 09:37:16AM +0530, Bharata B Rao wrote:
> > On Mon, Sep 14, 2015 at 11:41:53AM +1000, David Gibson wrote:
> > > The dynamic reconfiguration (hotplug) code for the pseries machine type
> > > uses a "DR connector"
On Mon, Sep 14, 2015 at 09:37:16AM +0530, Bharata B Rao wrote:
> On Mon, Sep 14, 2015 at 11:41:53AM +1000, David Gibson wrote:
> > The dynamic reconfiguration (hotplug) code for the pseries machine type
> > uses a "DR connector" QOM object for each resource it will be possible
> > to hotplug. Each
On Mon, Sep 14, 2015 at 11:36:11AM +1000, Gavin Shan wrote:
> This submits changes with formatted commit log while updating Linux
> headers using scripts/update-linux-headers.sh.
>
> Signed-off-by: Gavin Shan
Reviewed-by: David Gibson
> ---
> scripts/update-linux-headers.sh | 30
On Mon, Sep 14, 2015 at 11:36:08AM +1000, Gavin Shan wrote:
> The patchset depends on below Linux upstream commits:
>
> commit ed3e81f ("powerpc/eeh: Move PE state constants around")
> commit ec33d36 ("powerpc/eeh: Introduce eeh_pe_inject_err()")
>
> According to PAPR specification 2.7, there
On Mon, Sep 14, 2015 at 11:41:53AM +1000, David Gibson wrote:
> The dynamic reconfiguration (hotplug) code for the pseries machine type
> uses a "DR connector" QOM object for each resource it will be possible
> to hotplug. Each of these is added to its owner using
> object_property_add_child(o
On Fri, Sep 11, 2015 at 02:03:38PM -0600, Alex Williamson wrote:
> On Wed, 2015-09-09 at 20:43 -0600, Alex Williamson wrote:
> > On Thu, 2015-09-03 at 14:40 +1000, Alexey Kardashevskiy wrote:
> > > So far there were 2 limitations enforced on an emulated PHB
> > > regarding VFIO:
> > > 1) only one I
On Fri, Sep 11, 2015 at 09:30:28AM +0200, Thomas Huth wrote:
> On 11/09/15 02:45, David Gibson wrote:
> > On Thu, Sep 10, 2015 at 02:03:39PM +0200, Thomas Huth wrote:
> >> On 10/09/15 12:40, David Gibson wrote:
> >>> On Thu, Sep 10, 2015 at 09:33:21AM +0200, Thomas Huth wrote:
> On 09/09/15 23
On Fri, Sep 11, 2015 at 11:43:02AM +0200, Alexander Graf wrote:
>
>
> On 11.09.15 02:46, David Gibson wrote:
> > On Thu, Sep 10, 2015 at 02:13:26PM +0200, Alexander Graf wrote:
> >>
> >>
> >>> Am 10.09.2015 um 14:03 schrieb Thomas Huth :
> >>>
> On 10/09/15 12:40, David Gibson wrote:
> >
On Fri, Sep 11, 2015 at 11:17:01AM +0200, Thomas Huth wrote:
> The PAPR interface defines a hypercall to pass high-quality
> hardware generated random numbers to guests. Recent kernels can
> already provide this hypercall to the guest if the right hardware
> random number generator is available. Bu
On Sun, Sep 13, 2015 at 2:07 AM, Edgar E. Iglesias
wrote:
> From: "Edgar E. Iglesias"
>
> Handle missing CPU support for EL3 gracefully.
>
What is the use case here? A9 and A15 should be able to not have EL3,
but in this case the property should still exist but be set false. No
prop should only
On Fri, Sep 11, 2015 at 02:43:43PM +0200, Paolo Bonzini wrote:
>
>
> On 10/09/2015 08:28, David Gibson wrote:
> > The dynamic reconfiguration (hotplug) code for the pseries machine type
> > uses a "DR connector" QOM object for each resource it will be possible
> > to hotplug. Each of these is ad
The dynamic reconfiguration (hotplug) code for the pseries machine type
uses a "DR connector" QOM object for each resource it will be possible
to hotplug. Each of these is added to its owner using
object_property_add_child(owner, "dr-connector[*], ...);
That works ok, mostly, but it means tha
The patch supports RTAS call "ibm,errinjct" to allow injecting
EEH errors to VFIO PCI devices. The implementation is similiar
to EEH support for VFIO PCI devices: The RTAS request is captured
by QEMU and routed to spapr_phb_vfio_eeh_inject_error() where the
request is translated to VFIO container I
Here are some cleanups and improvements to the "dynamic
reconfiguration" (hotplug) infrastructure for the "pseries" machine
type.
There's an improved version of my patch to mitigate the O(n^3) time
for large maxmem values, and another small cleanup to remove a
redundant field in the structure.
Da
On Fri, Sep 11, 2015 at 09:42:06PM +0530, Bharata B Rao wrote:
> On Thu, Sep 10, 2015 at 04:28:25PM +1000, David Gibson wrote:
> > The dynamic reconfiguration (hotplug) code for the pseries machine type
> > uses a "DR connector" QOM object for each resource it will be possible
> > to hotplug. Each
The sPAPRDRConnector pseudo-device contains an owner field which is
set in spapr_dr_connector_new(). However, that function also calls
object_property_add_child() to set the DRConnector as the QOM child of
the owner object. That means that owner is always the same as the QOM
parent, and so redund
This replaces PCI_MSIX_FLAGS_BIRMASK with PCI_MSIX_TABLE_BIR. Also,
3 more macros regarding MSIx table offset, MSIx PBA BAR index and
MSIx PBA offset and this uses them. Besides, PCI_ERR_UNC_TRAIN is
replaced with PCI_ERR_UNC_UND. The changes were introduced by
below Linux upstream commits:
comm
This allows to include "stdint.h" in virtio header files. Otherwise,
scripts/update-linux-headers.sh fails when updating headers from
Linux 4.2.rc8 kernel. include/uapi/linux/virtio_ring.h starts to
include "stdint.h" from commit d768f32a ("virtio: Fix typecast of
pointer in vring_init()").
Signed
This supports RTAS calls "ibm,{open,close}-errinjct" to manupliate
the token, which is passed to RTAS call "ibm,errinjct" to indicate
the valid context for error injection. Each VM is permitted to have
only one token at once and we simply have sequential number for that.
The token is resetted in pp
The patchset depends on below Linux upstream commits:
commit ed3e81f ("powerpc/eeh: Move PE state constants around")
commit ec33d36 ("powerpc/eeh: Introduce eeh_pe_inject_err()")
According to PAPR specification 2.7, there're 3 RTAS calls relevent to error
injection: "ibm,open-errinjct", "ibm,
Synchronize the Linux headers from kernel version 4.3.0-rc1
(commit 6ff33f3)
This commit was created automatically by update-linux-headers.sh.
Signed-off-by: Gavin Shan
---
include/standard-headers/linux/pci_regs.h| 381 ---
include/standard-headers/linux/virtio_ring
This submits changes with formatted commit log while updating Linux
headers using scripts/update-linux-headers.sh.
Signed-off-by: Gavin Shan
---
scripts/update-linux-headers.sh | 30 ++
1 file changed, 30 insertions(+)
diff --git a/scripts/update-linux-headers.sh b/s
This includes linux/arch/powerpc/include/uapi/asm/eeh.h while
updating linux header files. The specific header file, introduced
by the following Linux upstream commits for EEH on sPAPR platform:
ed3e81f ("powerpc/eeh: Move PE state constants around")
ec33d36 ("powerpc/eeh: Introduce eeh_pe_inj
Michael S. Tsirkin wrote on 2015-09-13:
> On Fri, Sep 11, 2015 at 05:39:07PM +0200, Claudio Fontana wrote:
>> On 09.09.2015 09:06, Michael S. Tsirkin wrote:
>>
>> There are many consequences to this, offset within BAR alone is not
>> enough, there are multiple things at the virtio level that need
On Sun, Sep 13, 2015 at 1:47 PM, Peter Maydell wrote:
> On 13 September 2015 at 21:22, Peter Crosthwaite
> wrote:
>> On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote:
>>> The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and
>>> may crash if the actual clock rate is too lo
Peter,
On 09/13/2015 01:47 PM, Peter Maydell wrote:
On 13 September 2015 at 21:22, Peter Crosthwaite
wrote:
On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote:
The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and
may crash if the actual clock rate is too low. The clock
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index be0cb32..50043cf 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translat
Instead of testing bytes one by one, we can use the following trick
from https://graphics.stanford.edu/~seander/bithacks.html:
haszero(v) = (v - 0x01010101) & ~v & 0x80808080
The subexpression v - 0x01010101, evaluates to a high bit set in any
byte whenever the corresponding byte in v is zero o
From: Guenter Roeck
If host and target endianness does not match, loding an initramfs does not work.
Fix by writing boot parameters with appropriate endianness conversion.
Signed-off-by: Guenter Roeck
Signed-off-by: Aurelien Jarno
---
hw/sh4/r2d.c | 6 +++---
1 file changed, 3 insertions(+),
Most floating point helpers can trigger an exception, but don't change
the globals. Mark these helpers as TCG_CALL_NO_WG.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/helper.h | 34 +-
1 file changed, 17 insertions(+), 17 deletions(
l-sh4-next-20150913
for you to fetch changes up to cdd14a8cf25c34ff8d0777530e8d16565f6bf7a1:
sh4: Fix initramfs initialization for endiannes-mismatched targets
(2015-09-13 23:08:51 +0200)
sh4-next:
- TCG optimizations
- fix initramfs
The SH4 shad instruction can shift in both direction, depending on the
sign of the shift. This is currently implemented using branches, which
is not really efficient and prevents the optimizer to do its job. In
practice it is often used with a constant loaded in a register just
before.
Simplify th
The SH4 shld instruction can shift in both direction, depending on the
sign of the shift. This is currently implemented using branches, which
is not really efficient and prevents the optimizer to do its job. In
practice it is often used with a constant loaded in a register just
before.
Simplify th
MIPS_DEBUG is a define used to dump the instruction disassembling. It
has to be defined at compile time. In practice I believe it's more
efficient to just look at the instruction disassembly and op dump using
-d in_asm,op. This patch therefore removes the corresponding code, which
clutters translat
This patchset get rid of old debugging code in translate.c, that has
been superseded by other debugging way (e.g. (-d in_asm,op). It comes
from the discussion there:
https://lists.gnu.org/archive/html/qemu-devel/2015-07/msg03162.html
I had it ready for some time, now that 2.4 has been release,
MIPS_DEBUG_SIGN_EXTENSIONS was used sometimes ago to verify that 32-bit
instructions correctly sign extend their results. It's now not need
anymore, remove it.
Cc: Leon Alrae
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 39 ---
1 file changed,
For vector instructions, the helpers get pointers to the vector register
in arguments. Some operands might point to the same register, including
the operand holding the result.
When emulating instructions which access the vector elements in a
non-linear way, we need to store the result in an tempo
The xscmpodp and xscmpudp instructions only have the AX, BX bits in
there encoding, the lowest bit (usually TX) is marked as an invalid
bit. We therefore can't decode them with GEN_XX2FORM, which decodes
the two lowest bit.
Introduce a new form GEN_XX2FORM, which decodes AX and BX and mark
the low
This patchset fixes some vector instructions which are incorrectly
decoded or implemented. The first patch is needed to run recent version
of openssl, as it enabled POWER8 instrutctions when it detects such a
CPU.
Aurelien Jarno (2):
target-ppc: fix vcipher, vcipherlast, vncipherlast and vpermxo
On 2015-09-10 19:48, Aurelien Jarno wrote:
> On 2015-09-01 22:51, Richard Henderson wrote:
> > I've been looking at this problem off and on for the last week or so,
> > prompted by the sparc performance work. Although I havn't been able
> > to get a proper sparc64 guest install working, I see the
On 13 September 2015 at 21:22, Peter Crosthwaite
wrote:
> On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote:
>> The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and
>> may crash if the actual clock rate is too low. The clock rate used to be
>> (ps-clk-frequency * 26 / 4), w
On 09/13/2015 01:22 PM, Peter Crosthwaite wrote:
On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote:
The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and
may crash if the actual clock rate is too low. The clock rate used to be
(ps-clk-frequency * 26 / 4), which resulted in
On Fri, Sep 11, 2015 at 3:30 AM, Sai Pavan Boddu
wrote:
> From: Peter Crosthwaite
>
> This should be a shifted MASKED_WRITE like all other instances of
> non-word aligned registers.
>
> Signed-off-by: Peter Crosthwaite
As the sender, this requires your signed-off-by line (in addition to
any or
On Sat, Sep 12, 2015 at 2:06 PM, Guenter Roeck wrote:
> The Linux kernel only accepts 34 Khz and 67 Khz clock rates, and
> may crash if the actual clock rate is too low. The clock rate used to be
> (ps-clk-frequency * 26 / 4), which resulted in a CPU frequency of
> 21 Khz if ps-clk-fre
On Fri, Sep 11, 2015 at 12:37 AM, Michael Tokarev wrote:
>
> Can we please have some r-b or ACK for this? :)
>
> 20.08.2015 18:52, Guenter Roeck wrote:
>> Generate an interrupt if the tx buffer is empty and the tx empty interrupt
>> is enabled. This fixes a problem seen when running a Linux image
On Sun, 13 Sep 2015 13:28:24 -0400
"Gabriel L. Somlo" wrote:
> On Sun, Sep 13, 2015 at 12:51:53PM +0200, Marc Marí wrote:
> > On Sat, 12 Sep 2015 19:30:40 -0400
> > "Gabriel L. Somlo" wrote:
> >
> > > Move BIOS_CFG_IOPORT define from pc.c to pc.h, and rename
> > > it to FW_CFG_IO_BASE. Also, ad
On Sat, Sep 12, 2015 at 2:08 PM, Guenter Roeck wrote:
> Add support for the Xilinx XADC core used in Zynq 7000.
>
> References:
> - Zynq-7000 All Programmable SoC Technical Reference Manual
> - 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC
> Dual 12-Bit 1 MSPS Analog-to-Digital Converte
On Sun, Sep 13, 2015 at 12:51:53PM +0200, Marc Marí wrote:
> On Sat, 12 Sep 2015 19:30:40 -0400
> "Gabriel L. Somlo" wrote:
>
> > Move BIOS_CFG_IOPORT define from pc.c to pc.h, and rename
> > it to FW_CFG_IO_BASE. Also, add FW_CFG_IO_SIZE define (set
> > to 0x02, to cover the overlapping 16-bit c
On Sun, Sep 13, 2015 at 02:45:23PM +0300, Michael S. Tsirkin wrote:
> On Sat, Sep 12, 2015 at 07:30:41PM -0400, Gabriel L. Somlo wrote:
> > Add a fw_cfg device node to the ACPI SSDT. While the guest-side
> > BIOS can't utilize this information (since it has to access the
> > hard-coded fw_cfg devic
Add a DBG2 table, describing the pl011 UART.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 60 +++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9088248..0ea7023 1
The Debug Port Table 2 (DBG2) is mandated by the ARM Server Base Boot
Requirements specification. Add the DBG2 table definitions, and set up
an entry in the ARM virt machine for the pl011 UART.
Changes since v1:
- Static structure replaced with separate Header/Device structs.
- Missing cpu_to_le*(
The DBG2 table can be considered a "companion" to SPCR - it points out
debug consoles available in the system.
Also update SPCR comments to reflect DBG2 is now described in this file,
and update the supported SPCR specification revision (no functional
change).
Signed-off-by: Leif Lindholm
---
i
On Sep 13, 2015, at 7:28 AM, Peter Maydell wrote:
> On 13 September 2015 at 03:19, Programmingkid
> wrote:
>> Excellent. This fixed the problem. Thank you very much. The minimum
>> version of python QEMU supports is 2.6?
>
> At the moment it should be 2.4, apart from this bug. However we're ab
On 09/13/15 14:34, Michael S. Tsirkin wrote:
> On Sun, Sep 13, 2015 at 01:56:44PM +0200, Laszlo Ersek wrote:
>> As the subject suggests, I have terrible news.
>>
>> I'll preserve the full context here, so that it's easy to scroll back to
>> the ASL for reference.
>>
>> I'm also CC'ing edk2-devel, b
We'll build the UEFI ACPI Data Table for the VMGENID device in a separate
fw_cfg blob (see "docs/vmgenid.txt").
When introducing a new fw_cfg blob for ACPI linker/loader purposes, we
have to decide first if the new blob will be subject to patching on first
guest access.
(1) If so, then the blob m
The AccessAs(AccessType) macro can be used inside the Field() operator in
ASL, for diverging from the Field's default access type, for the fields
that follow AccessAs(). The new helper function allows us to generate the
matching AML.
The AccessAttribute parameter of the macro (described in the spe
acpi_add_table() and build_header() hardcode a number of traits that we'd
like to pass in later on, on a table-by-table basis. These are:
- The fw_cfg file name of the blob that contains the ACPI table.
ACPI_BUILD_TABLE_FILE is hard-coded at the moment.
- The OEM Table ID field. Due to the way
Using the tools
- acpi_add_table2(),
- build_header2()
and the blob
- ACPI_BUILD_QEMUPARAM_FILE
that have been added in the previous patches, we can now implement the
UEFI ACPI Data Table (and the related linker/loader commands) that are
specified in "docs/vmgenid.txt".
At this point the UEFI AC
This patch implements the "ACPI device, control methods" section of
"docs/vmgenid.txt", with dynamic AML generation.
A small portion of this patch was inspired by Gal Hammer's
[PATCH V15 4/5] i386: add a Virtual Machine Generation ID device
http://thread.gmane.org/gmane.comp.emulators.qemu/33
It follows the pattern of CreateDWordField() / aml_create_dword_field().
Cc: Paolo Bonzini
Cc: Gal Hammer
Cc: Igor Mammedov
Cc: "Michael S. Tsirkin"
Signed-off-by: Laszlo Ersek
---
include/hw/acpi/aml-build.h | 1 +
hw/acpi/aml-build.c | 11 +++
2 files changed, 12 insertion
This ASL operator (and the underlying AML) enables named ACPI data tables
to be located from AML code, and to be accessed field-wise, like an
operation region. This is useful for passing down "parameter tables" to
the guest; the ACPI linker/loader can relocate pointers in them, and then
the AML cod
ACPI 1.0b defines the SerializeFlag in MethodFlags. We have not exposed
this until now, but serializing methods that create named objects is
warmly recommended by (recent versions of) the ACPI spec, and recent iasl
actually warns about it. Therefore expose SerializeFlag in a new function.
The old a
The identifier "table_data" is used in wildly different name spaces and
scopes, which makes it practically impossible to grep for uses of
"AcpiBuildTables.table_data" specifically. Rename the field to "main_blob"
(which is a unique identifier across the tree), and update all references
with the hel
Add a new method called "vm_generation_id_changed" to the
AcpiDeviceIfClass interface. The new method sends an ACPI notfication when
the VM generation ID is changed. This contributes to the implementation of
requirement R5, from "docs/vmgenid.txt".
This patch is a slight modification of Gal Hammer
The build_rsdt() function can relocate RSDT entries only to ACPI tables
that exist inside the same ACPI_BUILD_TABLE_FILE blob.
In order to relax this limitation, change the element type of the
"table_offsets" array from plain offset (always into
ACPI_BUILD_TABLE_FILE) to a (pointed-to-blob, offset
This ACPI table is supposed to carry various parameters for OSPM. We
introduce it with a single parameter field, "vmgenid_addr_base_ptr", which
is described as ADBP / "ADDR base pointer" in "docs/vmgenid.txt" (along
with the general structure of the table).
Cc: Paolo Bonzini
Cc: Gal Hammer
Cc: I
Cc: Paolo Bonzini
Cc: Gal Hammer
Cc: Igor Mammedov
Cc: "Michael S. Tsirkin"
Signed-off-by: Laszlo Ersek
Acked-by: Michael S. Tsirkin
---
Notes:
fyi:
- move from docs/specs/ to docs/ [Eric, Paolo]
- fix grammar [Eric]
- clarify that requirement R1e covers ROM and MMIO too [Mic
So, as I wrote in the parent, this does not actually work in Windows,
because Windows doesn't support the DataTableRegion() operator; not even
modern Windows versions.
I'm nonetheless posting the series for the following purposes:
- Posterity. I think the series is worth preserving in the mailing
On Sun, Sep 13, 2015 at 01:56:44PM +0200, Laszlo Ersek wrote:
> As the subject suggests, I have terrible news.
>
> I'll preserve the full context here, so that it's easy to scroll back to
> the ASL for reference.
>
> I'm also CC'ing edk2-devel, because a number of BIOS developers should
> be cong
As the subject suggests, I have terrible news.
I'll preserve the full context here, so that it's easy to scroll back to
the ASL for reference.
I'm also CC'ing edk2-devel, because a number of BIOS developers should
be congregating there.
On 08/28/15 22:18, Laszlo Ersek wrote:
> Cc: Paolo Bonzini
On Sat, Sep 12, 2015 at 07:30:41PM -0400, Gabriel L. Somlo wrote:
> Add a fw_cfg device node to the ACPI SSDT. While the guest-side
> BIOS can't utilize this information (since it has to access the
> hard-coded fw_cfg device to extract ACPI tables to begin with),
> having fw_cfg listed in ACPI will
On 13 September 2015 at 03:19, Programmingkid wrote:
> Excellent. This fixed the problem. Thank you very much. The minimum
> version of python QEMU supports is 2.6?
At the moment it should be 2.4, apart from this bug. However we're about
to raise it to 2.6 (and there's a patch on the list that up
On Sat, 12 Sep 2015 19:30:40 -0400
"Gabriel L. Somlo" wrote:
> Move BIOS_CFG_IOPORT define from pc.c to pc.h, and rename
> it to FW_CFG_IO_BASE. Also, add FW_CFG_IO_SIZE define (set
> to 0x02, to cover the overlapping 16-bit control and 8-bit
> data ports).
>
> Signed-off-by: Gabriel Somlo
> --
On Fri, Sep 11, 2015 at 03:44:47PM -0300, Eduardo Habkost wrote:
> Ping?
>
> So, what's the reason we are still keeping those old machines in the
> code?
Victor also wanted to clean out some very old machine types for
the PIIX, too.
But if someone created a machine with libvirt, these machine ty
On Fri, Sep 11, 2015 at 05:39:07PM +0200, Claudio Fontana wrote:
> On 09.09.2015 09:06, Michael S. Tsirkin wrote:
> > On Mon, Sep 07, 2015 at 02:38:34PM +0200, Claudio Fontana wrote:
> >> Coming late to the party,
> >>
> >> On 31.08.2015 16:11, Michael S. Tsirkin wrote:
> >>> Hello!
> >>> During t
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 26 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index bef898f..95886ff 100644
--- a/target-arm/cpu.
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 42 +-
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c10e4ee..bef898f 100644
--- a/
From: "Edgar E. Iglesias"
Break out mpidr_read_val() to allow future sharing of the
code that conditionally sets the M and U bits of MPIDR.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a
From: "Edgar E. Iglesias"
Stage-2 translations, EL2 and EL3 regimes don't have the
EPD control.
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9977062..6c67ce2 10
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 43 +--
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5abd8ba..f45fd05 100644
---
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 34 --
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f45fd05..c10e4ee 100644
--- a/target-
From: "Edgar E. Iglesias"
Hi,
This is another series with small steps towards EL2 emulation.
Patch 1 is a fix to allow easier testing of EL3-less cores.
Patches 2 and on add regs and a few small steps towards 2-stage MMU.
Comments welcome!
Best regards,
Edgar
v1 -> v2:
* Add fix for graceful
From: "Edgar E. Iglesias"
Stage-2 MMU translations do not have configurable TBI as
the top byte is always 0 (48-bit IPAs).
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
i
From: "Edgar E. Iglesias"
Handle missing CPU support for EL3 gracefully.
Signed-off-by: Edgar E. Iglesias
---
hw/cpu/a15mpcore.c | 2 +-
hw/cpu/a9mpcore.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 4ef8db1..94e8cc1 1006
On 09/06/2015 10:36 PM, Richard Henderson wrote:
On Sep 5, 2015 14:35, Bastian Koppelmann wrote:
IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and
the manual is fairly clear about that. User mode cpu ought not to read
these registers unconditionally.
When I last discuss
On 09/03/2015 02:17 AM, Richard Henderson wrote:
Note that the specification for lf.madd.s is confused. It's
the only mention of supposed FPMADDHI/FPMADDLO special registers.
On the other hand, or1ksim implements a somewhat normal non-fused
multiply and add. Mirror that.
Signed-off-by: Richa
On Sun, 2015-09-13 at 09:12 +1000, Benjamin Herrenschmidt wrote:
> On Sat, 2015-09-12 at 20:37 +0200, Knut Omang wrote:
> > As the thread went silent after our conclusions, I have made a
> > second
> > implementation for the Intel IOMMU according to this alternate
> > scheme,
> > It keeps the curre
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