On Mon, Jun 01, 2015 at 08:32:55PM -0400, Stefan Berger wrote:
> This patch adds the missing common SSDT TPM file.
>
> Signed-off-by: Stefan Berger
I posted this too. But we really should just get rid of all this: we
have already removed most ASL code except for the DSDT.
> ---
> hw/i386/ssdt-
Hi!
> You mean that I put your patch
https://lists.gnu.org/archive/html/qemu-devel/201505/msg04495.html
Yes. You can of course further modify it, like changing #define to a variable
which can
be set from outside.
> The first patch of my V3 patch series, with the sole exception of fixing the
On 2015/5/30 21:54, Michael Tokarev wrote:
> Signed-off-by: Michael Tokarev
Reviewed-by: Shannon Zhao
> ---
> hw/display/tcx.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/hw/display/tcx.c b/hw/display/tcx.c
> index a9f9f66..c2b32c3 100644
> --- a/hw/dis
On 2015/5/30 21:49, Michael Tokarev wrote:
> Signed-off-by: Michael Tokarev
Reviewed-by: Shannon Zhao
> ---
> hw/display/cg3.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/hw/display/cg3.c b/hw/display/cg3.c
> index 1e6ff2b..5f869a7 100644
> --- a/hw/disp
Shannon Zhao: can you please add your s-o-b or r-o-b for this
version, for this and the next patch?
This started from your original patch which just adds g_free(),
later you also added error message improvements to this piece,
on my request, but apparently this place needs more tweeking,
since fai
29.05.2015 19:29, Paolo Bonzini wrote:
> On 29/05/2015 16:14, Alex Bennée wrote:
>> You mean just do:
>>
>> diff --git a/configure b/configure
>> index b707429..f13831a 100755
>> --- a/configure
>> +++ b/configure
>> @@ -353,7 +353,7 @@ for opt do
>>;;
>>--cpu=*) cpu="$optarg"
>>;;
>> -
In this version I used mkdtemp(3) which is:
_BSD_SOURCE
|| /* Since glibc 2.10: */
(_POSIX_C_SOURCE >= 200809L || _XOPEN_SOURCE >= 700)
(POSIX.1-2008), so should be available on systems we care about.
While at it, reset the resulting directory name within smb structur
01.06.2015 10:53, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> translate-all.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/translate-all.h b/translate-all.h
> index ef9166c..0384640 100644
> --- a/translate-all.h
> +++ b/translate-all.h
> @@ -24,7 +24,6 @@ void tb_inva
29.05.2015 21:52, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> The help/man text for
>
> -incoming defer
>
> didn't make it through the merge of the code that implemented it.
Applied to -trivial, with the more verbose text for the documentation.
Thank you very much
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
It is part of the basic zArchitecture instructions. Allow it to be call
from EXECUTE.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/m
On 05/29/2015 12:24 AM, Dr. David Alan Gilbert wrote:
> * zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
>> This is the 5th version of COLO, here is only COLO frame part, include: VM
>> checkpoint,
>> failover, proxy API, block replication API, not include block replication.
>> The block pa
When a disk is attached to scsi-bus, virtio_scsi_hotplug will take care
of protecting the block device with op blockers. Currently we haven't
enabled block jobs (like what's done in virtio_blk_data_plane_create),
but it is better to disable ioeventfd when backend is locked. This is
useful to make
So that NBD export will not process more requests.
Signed-off-by: Fam Zheng
---
nbd.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/nbd.c b/nbd.c
index 06b501b..854d6a5 100644
--- a/nbd.c
+++ b/nbd.c
@@ -160,6 +160,8 @@ struct NBDExport {
uint32_t nbdflags;
virtio-blk now listens to locking and unlocking of the associated block
backend.
Up on locking:
non-dataplane:
1) Set VirtIOBlock.paused
2) In virtio_blk_handle_output, do nothing if VirtIOBlock.paused
dataplane:
1) Clear the host event notifier
2) In handle_notify, do nothing if
Should more ops be added to differentiate code between dataplane and
non-dataplane, the new saved_ops approach will be cleaner than messing
with N pointers.
Signed-off-by: Fam Zheng
Reviewed-by: Max Reitz
---
hw/block/dataplane/virtio-blk.c | 13 -
hw/block/virtio-blk.c |
Forward the call to bdrv_add_lock_unlock_notifier.
Signed-off-by: Fam Zheng
---
block/block-backend.c | 6 ++
include/sysemu/block-backend.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index 93e46f3..79fdf75 100644
--- a/block/
To save the bs pointer for drive_backup_clean, pull the assignment to
state->bs up. It will not be a problem for drive_backup_abort because
state->job will still be NULL.
Signed-off-by: Fam Zheng
---
blockdev.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/blockdev.c b/b
Callers will be notified upon bdrv_lock if it was not locked, and
bdrv_unlock if it becomes unlocked.
It can be used to pause and resume devices.
Signed-off-by: Fam Zheng
---
block.c | 1 +
block/io.c| 19 +++
include/block/block.h | 12 +++
The change is similar to drive-backup in last patch.
Signed-off-by: Fam Zheng
---
blockdev.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/blockdev.c b/blockdev.c
index d7526f6..e112a18 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1667,6 +1667,8 @@ static void blockdev_b
For various purposes, BDS users call bdrv_drain or bdrv_drain_all to make sure
there are no pending requests during a series of operations on the BDS. But in
the middle of operations, the caller may 1) yield from a coroutine (mirror_run);
2) defer the next part of work to a BH (mirror_run); 3) call
Signed-off-by: Fam Zheng
---
blockdev.c | 4
1 file changed, 4 insertions(+)
diff --git a/blockdev.c b/blockdev.c
index 5eaf77e..fdc5a17 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1356,6 +1356,7 @@ static void internal_snapshot_prepare(BlkTransactionState
*common,
}
/* 4. suc
Source and target are in sync when we leave the mirror_run loop, they
should remain so until bdrv_swap. Before block_job_defer_to_main_loop
was introduced, it has been easy to prove that. Now that tricky things
can happen after mirror_run returns and before mirror_exit runs, for
example, ioeventfd
Lock immediately follows aio_context_acquire, so unlock right before
the corresponding aio_context_release.
Signed-off-by: Fam Zheng
---
blockdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/blockdev.c b/blockdev.c
index fdc5a17..a8d5b10 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1
There callers work on a single BlockDriverState subtree, where using
bdrv_drain() is more accurate.
Signed-off-by: Fam Zheng
Reviewed-by: Paolo Bonzini
---
block.c | 6 +++---
block/snapshot.c | 2 +-
migration/block.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --
v2: Fix typo in commit message. (Eric)
Reorder patches as Paolo suggested.
This is the partial work to introduce bdrv_lock / bdrv_unlock and use them in
block jobs where exclusive access to a BDS is necessary. It address the same
category of problems as [1] with a different API, as the idea pr
On 05/31/2015 02:11 PM, Michael S. Tsirkin wrote:
On Tue, May 26, 2015 at 05:33:41PM -0400, Stefan Berger wrote:
For automated management of a TPM device, implement the TCG Physical Presence
Interface Specification that allows a root user on Linux (for example) to set
an opcode for a sequence of
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
+/* LOAD FP INTEGER */
+C(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0)
+C(0xb35f, FIDBR, RRF_e, Z, 0, f2_o, f1, 0, fidb, 0)
+C(0xb347, FIXBR, RRF_e, Z, 0, f2_o, x1, 0, fixb, 0)
That should be x2_o for FIXBR.
r~
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
It belongs to the DFP rounding facility.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 i
Reviewed-by: Richard Henderson
r~
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
STORE CLOCK FAST should be in the SCF facility.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On Mon, Jun 01, 2015 at 05:09:29PM +0100, Peter Maydell wrote:
> On 29 May 2015 at 07:43, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-arm/cpu.h| 1 +
> > target-arm/helper.c | 47
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
Change to match the PoP. In practice both format RIL-a and RIL-b have
the same fields. They differ on the way we decode the fields, and it's
done correctly in QEMU.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
D(0x8400, BRXH,RSI, Z, 0, 0, 0, 0, bx32, 0, 0)
D(0x8500, BRXLE, RSI, Z, 0, 0, 0, 0, bx32, 0, 1)
D(0xec44, BRXHG, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 0)
-D(0xec45, BRXHLE, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 1)
+D(0
From: Shannon Zhao
Since commit e353102(target-arm: cpu64: Add support for Cortex-A53) has
added Cortex-A53 cpu support for target-arm, this patch just enables it
for kvm-arm.
Here adding XGENE_POTENZA just makes the enum continuous.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
From: Shannon Zhao
This first patch adds cortex-a53 cpu support in kvm-arm and the second
adds cortex-a53 cpu support in machine virt.
changes since v1:
* adding XGENE_POTENZA just makes the enum continuous (Peter)
* add R-b from Peter
Shannon Zhao (2):
target-arm/kvm64: Add cortex-a53 cp
From: Shannon Zhao
Add cortex-a53 cpu support in machine virt, so it can be used for TCG
and KVM.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index
On 2015/6/1 2:11, Michael S. Tsirkin wrote:
On Thu, Mar 19, 2015 at 09:01:27AM +0800, Chen, Tiejun wrote:
On 2015/3/18 18:21, Gerd Hoffmann wrote:
On Mi, 2015-03-18 at 17:06 +0800, Tiejun Chen wrote:
Implement a pci host bridge specific to passthrough. Actually
this just inherits the standard
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
The COMPARE LOGICAL IMMEDIATE AND TRAP instruction should compare the
numbers as unsigned, as its name implies.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 inserti
This patch adds the missing common SSDT TPM file.
Signed-off-by: Stefan Berger
---
hw/i386/ssdt-tpm-common.dsl | 36
1 file changed, 36 insertions(+)
create mode 100644 hw/i386/ssdt-tpm-common.dsl
diff --git a/hw/i386/ssdt-tpm-common.dsl b/hw/i386/ssdt-tpm-
v1 -> v2:
* some cleanup
* add test for TCO_LOCK bit
v2 -> v3:
* add tests for TCO control & status bits
* fix check of SECOND_TO_STS bit (it's set in TCO2_STS reg)
Signed-off-by: Paulo Alcantara
---
tests/Makefile | 2 +
tests/tco-test.c | 475 +++
v1 -> v2:
* s/PDRC/CCR/ for clarity and match ICH9 spec
* remove unnecessary OperationRegion for RCRB
Signed-off-by: Paulo Alcantara
---
hw/i386/q35-acpi-dsdt.dsl | 14 ++
tests/acpi-test-data/q35/DSDT | Bin 7666 -> 7723 bytes
2 files changed, 14 insertions(+)
diff --git a
This interface provides some registers within a 32-byte range and can be
acessed through PCI-to-LPC bridge interface (PMBASE + 0x60).
It's commonly used as a watchdog timer to detect system lockups through
SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If
NO_REBOOT bit is not
On 06/01/2015 01:39 PM, Daniel P. Berrange wrote:
On Mon, Jun 01, 2015 at 05:33:24PM +0100, Peter Maydell wrote:
On 1 June 2015 at 13:22, Michael S. Tsirkin wrote:
The following changes since commit 97af820f539efe80b87615a04f9de11ea585f725:
Merge remote-tracking branch
'remotes/pmaydell/t
On 06/01/2015 07:18 PM, Mark Cave-Ayland wrote:
> On 02/06/15 00:09, John Snow wrote:
>
>> On 05/31/2015 04:05 PM, Mark Cave-Ayland wrote:
>>> This patchset follows on from my recent work on fixing issues with the
>>> macio controller, and remodels the new pmac_dma_read() and pmac_dma_write()
>>
On 02/06/15 00:09, John Snow wrote:
> On 05/31/2015 04:05 PM, Mark Cave-Ayland wrote:
>> This patchset follows on from my recent work on fixing issues with the
>> macio controller, and remodels the new pmac_dma_read() and pmac_dma_write()
>> functions in a similar manner to the unaligned block fun
On 05/31/2015 04:05 PM, Mark Cave-Ayland wrote:
> This patchset follows on from my recent work on fixing issues with the
> macio controller, and remodels the new pmac_dma_read() and pmac_dma_write()
> functions in a similar manner to the unaligned block functions.
>
> With this in place, long ch
By default, IPv4 prefixes will be derived by matching the address
to those returned by GetAdaptersInfo. IPv6 prefixes can not be
matched this way due to the unpredictable order of entries.
In Windows Vista/2008 guests and newer, both IPv4 and IPv6 prefixes
can be retrieved from OnLinkPrefixLength
Changes from v4:
- Fixed up the commit messages to remove the utf-8 characters.
Changes from v3:
- Patch 1/2 removed setting ARCH_$ARCH
- Patch 2/2 implemented feedback from v3. Use WSAAddressToString for
inet_ntop functionality. WSAStringToAddress is available in all versions
of Windows.
This p
Test if --extra-cflags is being used to include flags such as
_WIN32_WINVER and WINVER to gain additional functionality offered
by Windows Vista/2008 and newer. If not, default WINVER to 0x501.
Add the iphlpapi library to use APIs such as GetAdaptersInfo and
GetAdaptersAddresses.
Signed-off-by:
On Mon, 2015-06-01 at 15:10 +0200, Philipp Hahn wrote:
> Hello,
>
> On 31.05.2015 12:58, Vadim Rozenfeld wrote:
> > On Sun, 2015-05-31 at 11:26 +0300, Yan Vugenfirer wrote:
> >>> On May 29, 2015, at 5:43 PM, Philipp Hahn
> >>> wrote:
> ...
> >>> we tried to migrate some Windows 2008 and 2012 VMs
In preparation for more efficient setting of this field.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c | 4 +-
target-sh4/helper.c| 2 +-
target-sh4/op_helper.c | 32 ++--
target-sh4/translate.c | 212
On Mon, 1 Jun 2015 10:38:32 -0300
"Paulo Alcantara" wrote:
> On Mon, June 1, 2015 6:05 am, Paolo Bonzini wrote:
> >
> >
> > On 31/05/2015 00:04, Paulo Alcantara wrote:
> >> +case TCO_RLD:
> >> +tr->timeouts_no = 0;
> >> +if (can_start_tco_timer(tr)) {
> >> +tr->tco
Splitting Q and M out of SR, it's possible to optimize div1 by using
TCG code instead of an helper.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 12 +++--
target-sh4/helper.h| 1 -
target-sh4/op_helper.c | 118 -
target-sh4/tra
The following changes since commit f5790c3bc81702c98c7ddadedb274758cff8cbe7:
Revert "target-alpha: Add vector implementation for CMPBGE" (2015-05-22
12:30:13 +0100)
are available in the git repository at:
git://git.aurel32.net/qemu.git tags/pull-qemu-sh4-2015-06-01
for you to fetch changes
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 30 ++--
target-sh4/gdbstub.c |
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 882c8d8..38d4a6f 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -18,7 +18,6 @@
*
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index d5b448e..250632a 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -795,12 +795,12 @@ s
At the same time move the trap code from op_ct into gen_trap and use it
for all new functions. The value needs to be stored back to register
before the exception, but also before the brcond (as we don't use
temp locals). That's why we can't use wout helper.
Cc: Alexander Graf
Cc: Richard Henderso
This is needed to pass the gcc.c-torture/execute/ieee/20010114-2.c test
in the gcc testsuite.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/fpu_helper.c | 31 +++
target-s390x/helper.h | 3 +++
target-s390x/insn-data.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index a7a8f39..d5b448e 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index daea268..882c8d8 100644
--- a/target-sh4/translate.c
+++ b/target-
RISBGN is the same as RISBG, but without setting the condition code.
CLT and CLGT are the same as CLRT and CLGRT, but using memory for the
second operand.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 3 +++
target-s390x/translate.c |
When an operation code is not recognized (ie invalid instruction) an
operation exception should be generated instead of a specification
exception. The latter is for valid opcode, with invalid operands or
modifiers.
This give a very basic GDB support in the guest, as it uses the invalid
opcode 0x00
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index f9bc24c..a7a8f39 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -642,17 +642,15 @@
Besides RISBHG and RISBLG, all high-word instructions are not
implemented. Fix that.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 47 ++
target-s390x/translate.c | 51 ++
Change to match the PoP. In practice both format RIL-a and RIL-b have
the same fields. They differ on the way we decode the fields, and it's
done correctly in QEMU.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 4 ++--
1 file changed, 2
This complete the floating point support sign handling facility.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index faaedf8..85
It is part of the basic zArchitecture instructions. Allow it to be call
from EXECUTE.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/mem_helper.c | 24
targ
It is part of the basic zArchitecture instructions.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/mem_helper.c | 39 +++
target-s390x/translate.
The COMPARE LOGICAL IMMEDIATE AND TRAP instruction should compare the
numbers as unsigned, as its name implies.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x
STORE CLOCK FAST should be in the SCF facility.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index 7649098..68c46
The two first patches fixes bugs in the target-s390x TCG emulation.
The 4 next patches fix some instruction definition. Given we don't
emulate a given CPU model and check the instruction availability,
they don't provide any functional change.
The last patches emulate some missing instructions, ei
Use the same name than in PoP and binutils.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index 3955443..f83445a 1
It belongs to the DFP rounding facility.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index 68c46c7..bc99fb5 1006
>>>
>
> On 01/06/2015 20:56, Kirk Allan wrote:
>> Test if *-extra-cflags is being used to include flags such as
>> _WIN32_WINVER and WINVER to gain additional functionality offered
>> by Windows Vista/2008 and newer. If not, default WINVER to 0x501.
>>
>> Add the iphlpapi library to use APIs
On 5/27/15 05:39, Chen Gang wrote:
> On 5/12/15 05:26, Chen Gang wrote:
>> +}
>> +
>> +/*
>> + * Functional Description
>> + *
>> + *uint64_t output = 0;
>> + *uint32_t counter;
>> + *for (counter = 0; counter < (WORD_SIZE / 32); counter++)
>>
Firstly, thank you very much for your valuable work and quick response.
On 6/2/15 02:40, Richard Henderson wrote:
> First, what happened to the decoding skeleton patch? You seem to have merged
> it with patch 9 here. That said, see the bottom of this message.
>
Yes, I merged them together. Fo
> > He later #defines target_{,u}long to e.g. arm_target_{,u}long.
>
> Ok, here's where I'm not liking things. It shouldn't be a typedef in some
> places and a define others. From this description, it sounds like it ought
> to always be a define.
target_long expands to arm_target_long, which i
> On 01 Jun 2015, at 03:14, Liviu Ionescu wrote:
>
>> I have added your git branch to my to-review queue. I'll have a look
>> over next few days.
>
> thank you, any comments/suggestions are highly appreciated, but, again, as it
> is now, it is preliminary work, only STM32-H103 and STM32F103RB
On 06/01/2015 12:51 PM, Paolo Bonzini wrote:
On 01/06/2015 21:24, Richard Henderson wrote:
On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
This is currently provided by cpu-defs and is a target specific
definition. However, to prepare for multi-arch only the bare minimum
content from cpu-def
On Mon, Jun 01, 2015 at 02:00:22PM -0400, Gabriel L. Somlo wrote:
> On Mon, Jun 01, 2015 at 05:44:47PM +0200, Michael S. Tsirkin wrote:
> > > > Shouldn't we migrate the fw cfg data that the source host generates
> > > > originally, rather than trying to play games make sure the way it
> > > > is r
On 06/01/2015 04:26 PM, Peter Maydell wrote:
> On 1 June 2015 at 21:10, John Snow wrote:
>>
>>
>> On 05/29/2015 02:43 AM, Edgar E. Iglesias wrote:
>>> From: "Edgar E. Iglesias"
>>>
>>> Signed-off-by: Edgar E. Iglesias
>>> ---
>>> target-arm/op_helper.c | 2 +-
>>> 1 file changed, 1 insertion(
On 01/06/2015 20:56, Kirk Allan wrote:
> Test if –-extra-cflags is being used to include flags such as
> _WIN32_WINVER and WINVER to gain additional functionality offered
> by Windows Vista/2008 and newer. If not, default WINVER to 0x501.
>
> Add the iphlpapi library to use APIs such as GetAdap
- Original Message -
> From: "Peter Maydell"
> To: "Paolo Bonzini"
> Cc: "Richard Henderson" , "Peter Crosthwaite"
> , "QEMU Developers"
> , "Edgar E. Iglesias" ,
> "Peter Crosthwaite"
> , "Andreas Färber"
> Sent: Monday, June 1, 2015 10:25:03 PM
> Subject: Re: [RFC v2 10/34] include
On 1 June 2015 at 20:51, Paolo Bonzini wrote:
> He later #defines target_{,u}long to e.g. arm_target_{,u}long.
Yikes.
-- PMM
On 1 June 2015 at 21:10, John Snow wrote:
>
>
> On 05/29/2015 02:43 AM, Edgar E. Iglesias wrote:
>> From: "Edgar E. Iglesias"
>>
>> Signed-off-by: Edgar E. Iglesias
>> ---
>> target-arm/op_helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target-arm/op_helper.
On 01.06.15 15:51, Michael Mueller wrote:
> As the implementation of const_le16 and const_le32 is not build time constant
> on big endian systems this need to be fixed.
>
> CChw/input/virtio-input-hid.o
> hw/input/virtio-input-hid.c:340:13: error: initializer element is not constant
> hw/i
On 05/29/2015 02:43 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/op_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 3f5b9ab..7583ae7 1
On Fri, May 29, 2015 at 09:27:19PM +0200, Paolo Bonzini wrote:
> On 29/05/2015 20:04, Eduardo Habkost wrote:
> > static int apic_no;
> > -static bool mmio_registered;
> > +CPUState *cpu = CPU(s->cpu);
> > +MemoryRegion *root;
> >
> > if (apic_no >= MAX_APICS) {
> >
On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
> The tcg_ctx global is tricky. It needs to become part of the cpu state.
> This is done via a pointer.
Why does it need to be virtualized? We already have one for each arch-obj-y.
Is it really accessed from outside arch-obj-y?
r~
On 01/06/2015 21:24, Richard Henderson wrote:
> On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
>> This is currently provided by cpu-defs and is a target specific
>> definition. However, to prepare for multi-arch only the bare minimum
>> content from cpu-defs.h should be exported to core code. A
On 01.06.2015 20:02, Peter Maydell wrote:
> On 28 May 2015 at 12:00, Sergey Fedorov wrote:
>> ---
>> target-arm/helper.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 5d0f011..fc3f192 100644
>> --- a/target-arm/helper.c
>> +++ b/t
commit 5cb18b3d7bff2a83275ee98af2a14eb9e21c93ab
TPM2 ACPI table support
was missing a file, so build with iasl fails
(build without iasl works since it uses the generated
hex files).
Reported-by: "Daniel P. Berrange"
Signed-off-by: Michael S. Tsirkin
---
hw/i386/ssdt-tpm-common.dsl | 36 +
The following changes since commit 830d70db692e374b5f4407f96a1ceefdcc97:
vhost-user: add multi queue support (2015-06-01 14:18:55 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
for you to fetch changes up to 9e472263b0
On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
> Move the architecture agnostic function prototypes for exec.c out of
> cputlb.h to exec-all.h. This allows hiding of the arch specific
> cputlb.h from exec.c which should be getting close to having no
> architecture specifics. Prepares support for
On 06/01/2015 12:59 AM, Paolo Bonzini wrote:
>
>
> On 31/05/2015 08:11, Peter Crosthwaite wrote:
>> Allow subsequent inclusion of cpu-defs.h. This allows including
>> multiple cpu.h's and each getting the right set of definitions for
>> its env structure definition. All define symbols are undeffe
On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
> These are not Architecture specific in any way so move them out of
> cpu-defs.h. tb-hash.h is an appropriate place as a leading user and
> their strong relationship to TB hashing and caching.
>
> Signed-off-by: Peter Crosthwaite
> ---
> include/
On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
> This is one of very few things in exec-all with a genuine CPU
> architecture dependency. Move these hashing helpers to a new
> header to trim exec-all.h down to a near architecture-agnostic
> header.
>
> The defs are only used by cpu-exec and tran
On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
> This is currently provided by cpu-defs and is a target specific
> definition. However, to prepare for multi-arch only the bare minimum
> content from cpu-defs.h should be exported to core code. And this is
> all we need. So split it to a new header
On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
> These exception indicies are generic and don't have any reliance on the
> per-arch cpu.h defs. Move them to cpu-all.h so they can be used by core
> code that does not have access to cpu-defs.h.
>
> Signed-off-by: Peter Crosthwaite
> ---
> includ
On 05/30/2015 11:11 PM, Peter Crosthwaite wrote:
> Move this function to common code. It has no arch specific
> dependencies. Prepares support for multi-arch where the translate-all
> interface needs to be virtualised. One less thing to virtualise.
>
> Signed-off-by: Peter Crosthwaite
> ---
> tr
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