Alexey Kardashevskiy writes:
> On 05/19/2015 02:51 PM, Nikunj A Dadhania wrote:
>> Alexey Kardashevskiy writes:
>>
>>> On 05/07/2015 05:21 PM, Nikunj A Dadhania wrote:
Each hardware instance has a platform unique location code. The OF
device tree that describes a part of a hardware en
On Mon, May 18, 2015 at 03:36:54PM -0300, Eduardo Habkost wrote:
> On Tue, May 12, 2015 at 11:06:25AM +0530, Bharata B Rao wrote:
> > Currently CPUState.cpu_index is monotonically increasing and a newly
> > created CPU always gets the next higher index. The next available
> > index is calculated by
On (Tue) 19 May 2015 [11:32:56], Amit Shah wrote:
> On (Tue) 19 May 2015 [10:50:59], Fam Zheng wrote:
> > Achieved by:
> >
> > - Remembering the server fd with a global variable, in order to access
> > it from nbd_client_closed.
> >
> > - Checking nbd_can_accept() and updating server_fd handler
On 2015/5/19 0:48, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
Besides normal checkpoint which according to the result of net packets
comparing, We do additional checkpoint periodically, it will reduce the number
of dirty pages when do one checkpoint, if
On (Tue) 19 May 2015 [10:50:59], Fam Zheng wrote:
> Achieved by:
>
> - Remembering the server fd with a global variable, in order to access
> it from nbd_client_closed.
>
> - Checking nbd_can_accept() and updating server_fd handler whenever
> client connects or disconnects.
>
> Signed-off-by
On Mon, May 18, 2015 at 04:09:49PM -0300, Eduardo Habkost wrote:
> On Tue, May 12, 2015 at 11:06:23AM +0530, Bharata B Rao wrote:
> > This patch changes the way cpu_index is handed out to newly created
> > CPUs by tracking the allocted CPUs in a bitmap. More information and
> > the need for this pa
Alexey Kardashevskiy writes:
> On 05/19/2015 02:51 PM, Nikunj A Dadhania wrote:
>> Alexey Kardashevskiy writes:
>>
>>> On 05/07/2015 05:21 PM, Nikunj A Dadhania wrote:
Each hardware instance has a platform unique location code. The OF
device tree that describes a part of a hardware en
On 05/19/2015 02:51 PM, Nikunj A Dadhania wrote:
Alexey Kardashevskiy writes:
On 05/07/2015 05:21 PM, Nikunj A Dadhania wrote:
Each hardware instance has a platform unique location code. The OF
device tree that describes a part of a hardware entity must include
the “ibm,loc-code” property wi
Alexey Kardashevskiy writes:
> On 05/07/2015 05:21 PM, Nikunj A Dadhania wrote:
>> Each hardware instance has a platform unique location code. The OF
>> device tree that describes a part of a hardware entity must include
>> the “ibm,loc-code” property with a value that represents the location
>>
add 'aer' property to let user able to decide whether expose
the aer capability. by default we should disable aer feature,
because it needs configuration restrictions.
Signed-off-by: Chen Fan
---
hw/i386/pc_q35.c| 4 +++
hw/vfio/pci.c | 84 +
when the vfio device encounters an uncorrectable error in host,
the vfio_pci driver will signal the eventfd registered by this
vfio device, the results in the qemu eventfd handler getting
invoked.
this patch is to pass the error to guest and have the guest driver
recover from the error.
Signed-of
For vfio pcie device, we could expose the extended capability on
PCIE bus. in order to avoid config space broken, we introduce
a copy config for parsing extended caps. and rebuild the pcie
extended config space.
Signed-off-by: Chen Fan
---
hw/vfio/pci.c | 73 +
pcie_aer_init was used to emulate an aer capability for pcie device,
but for vfio device, the aer config space size is mutable and is not
always equal to PCI_ERR_SIZEOF(0x48). it depends on where the TLP Prefix
register required, so here we add a size argument.
Signed-off-by: Chen Fan
---
hw/pci
when do virtual secondary bus reset, the vfio device under
this bus need to do host bus reset to reset the device.
so add this case.
Signed-off-by: Chen Fan
---
hw/vfio/pci.c | 12 +++-
include/hw/vfio/vfio-common.h | 1 -
2 files changed, 11 insertions(+), 2 deletions(-
For now, for vfio pci passthough devices when qemu receives
an error from host aer report, there just terminate the guest,
but usually user want to know what error occurred but stop the
guest, so this patches add aer capability support for vfio device,
and pass the error to guest, and have guest dr
when machine is done, we should check the all vfio devices
whether support host bus reset, then when need virtual secondary
bus reset, we should reset host bus.
Signed-off-by: Chen Fan
---
hw/vfio/pci.c | 83 +++
1 file changed, 83 insertio
Calling pcie_aer_init to initilize aer related registers for
vfio device, then reload physical related registers to expose
device capability.
Signed-off-by: Chen Fan
---
hw/vfio/pci.c | 49 -
1 file changed, 48 insertions(+), 1 deletion(-)
diff --
For vfio device, we need to propagate the aer error to
Guest OS. we use the pcie_aer_msg() to send aer error
to guest.
Signed-off-by: Chen Fan
---
hw/pci/pcie_aer.c | 2 +-
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie_aer.c b/
Particularly, For vfio device, Once need to recovery devices
by bus reset such as AER, we always need to reset the host bus
to recovery the devices under the bus, so we need to add pci bus
callbacks to specify to do host bus reset.
Signed-off-by: Chen Fan
---
hw/pci/pci.c | 6 +
the function is used to get affected devices by bus reset.
so here extract it, and can used for aer soon.
Signed-off-by: Chen Fan
---
hw/vfio/pci.c | 63 +++
1 file changed, 46 insertions(+), 17 deletions(-)
diff --git a/hw/vfio/pci.c b/hw
squeeze out vfio_pci_do_hot_reset to do host bus reset when AER recovery.
Signed-off-by: Chen Fan
---
hw/vfio/pci.c | 75 +++
1 file changed, 44 insertions(+), 31 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index fe4963f..037a2
When block job mirror is finished, the source and target is synced. But
we call bdrv_swap() later in main loop bh. If the guest write before
that, target will not get the new data.
Reported-by: Wen Congyang
Signed-off-by: Fam Zheng
---
block/mirror.c | 8 +++-
1 file changed, 7 insertions(+
We don't want new requests from guest, so block the operation around the
nested poll.
It also avoids looping forever when iothread is submitting a lot of requests.
Signed-off-by: Fam Zheng
---
block/io.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a
Signed-off-by: Fam Zheng
---
blockdev.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/blockdev.c b/blockdev.c
index 923fc90..ae52d27 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1575,6 +1575,7 @@ typedef struct DriveBackupState {
BlockDriverState *bs;
AioCo
Signed-off-by: Fam Zheng
---
blockdev.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index 7f763d9..923fc90 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1404,6 +1404,7 @@ typedef struct ExternalSnapshotState {
BlockDriverStat
Signed-off-by: Fam Zheng
---
blockdev.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/blockdev.c b/blockdev.c
index ae52d27..bd28183 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1649,6 +1649,7 @@ typedef struct BlockdevBackupState {
BlockDriverState *bs;
So that NBD export cannot submit IO during bdrv_drain_all().
Signed-off-by: Fam Zheng
---
nbd.c | 24
1 file changed, 24 insertions(+)
diff --git a/nbd.c b/nbd.c
index 06b501b..b5026af 100644
--- a/nbd.c
+++ b/nbd.c
@@ -160,6 +160,8 @@ struct NBDExport {
uint32_t n
When a disk is attached to scsi-bus, virtio_scsi_hotplug will take care
of protecting the block device with op blockers. Currently we haven't
enabled block jobs (like what's done in virtio_blk_data_plane_create),
but it is necessary to honor "device IO" op blocker first before we do.
This is useful
Signed-off-by: Fam Zheng
---
blockdev.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index 5eaf77e..7f763d9 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -1262,6 +1262,7 @@ typedef struct InternalSnapshotState {
BlockDriverState *bs;
It blocks device IO.
All bdrv_op_block_all/blk_op_block_all callers are taken care of:
- virtio_blk_data_plane_create
- virtio_scsi_hotplug
Device creation, unblock it.
- bdrv_set_backing_hd
Backing hd is not used by device, so blocking is OK.
- backup_start
Blocking target when backup
Forward the call to bdrv_op_blocker_add_notifier.
Signed-off-by: Fam Zheng
Reviewed-by: Max Reitz
---
block/block-backend.c | 6 ++
include/sysemu/block-backend.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index 93e46f3..16e
BDS users can register a notifier and get notified about op blocker
changes.
Signed-off-by: Fam Zheng
Reviewed-by: Max Reitz
---
block.c | 35 +++
include/block/block.h | 8
include/block/block_int.h | 3 +++
3 files changed, 46 i
virtio-blk now listens to op blocker change of the associated block
backend.
Up on setting op blocker on BLOCK_OP_TYPE_DEVICE_IO:
non-dataplane:
1) Set VirtIOBlock.paused
2) In virtio_blk_handle_output, do nothing if VirtIOBlock.paused
dataplane:
1) Clear the host event notifier
Should more ops be added to differentiate code between dataplane and
non-dataplane, the new saved_ops approach will be cleaner than messing
with N pointers.
Signed-off-by: Fam Zheng
Reviewed-by: Max Reitz
---
hw/block/dataplane/virtio-blk.c | 13 -
hw/block/virtio-blk.c |
v4: virtio-scsi-dataplane: Use assert in ctrl/event queue handler. [Paolo]
Protect mirror complete in new patch 13. [Wen]
Add Max's rev-by in 02, 03, 04.
Fix 05, 06 per Max's comments.
Reported by Paolo.
Unlike the iohandler in main loop, iothreads currently process the event
notifier
Hi,
On 2015/5/19 10:40, Shannon Zhao wrote:
> Hi,
>
> I'm testing PCIe root port (ioh3420) on ARM64. Firstly I use following
> simple command line to check whether it works.
>
> qemu-system-aarch64 -M virt -device ioh3420
>
> But it fails with below log:
>
> qemu-system-aarch64: -device ioh342
On Mon, 05/18 20:19, Max Reitz wrote:
> On 15.05.2015 08:04, Fam Zheng wrote:
>
> Indentation is off if you intended to indent based on the opening
> parenthesis.
Will fix.
>
> Different question: Since event->type == BLOCK_OP_TYPE_DEVICE_IO, when will
> event->blocking ever be not equal to blk
The function cannot fail, so the check is superfluous.
Signed-off-by: Fam Zheng
---
hw/xen/xen_backend.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/xen/xen_backend.c b/hw/xen/xen_backend.c
index b2cb22b..2510e2e 100644
--- a/hw/xen/xen_backend.c
+++ b/hw/xen/xen_ba
The function cannot fail, so the check is superfluous.
Signed-off-by: Fam Zheng
---
audio/ossaudio.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/audio/ossaudio.c b/audio/ossaudio.c
index 4db2ca6..b9c6b30 100644
--- a/audio/ossaudio.c
+++ b/audio/ossaudio.c
All users are converted to qemu_set_fd_handler now, drop
qemu_set_fd_handler2 and IOHandlerRecord.fd_read_poll.
Signed-off-by: Fam Zheng
---
include/block/aio.h | 2 +-
include/qemu/main-loop.h | 49 +---
iohandler.c | 26 +--
The function cannot fail, so the check is superfluous.
Signed-off-by: Fam Zheng
---
audio/alsaaudio.c | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/audio/alsaaudio.c b/audio/alsaaudio.c
index 74ead97..ed7655d 100644
--- a/audio/alsaaudio.c
+++ b/audio/alsa
Some qemu_set_fd_handler2 stub callers will be converted to
call qemu_set_fd_handler, add this stub for them before making the
change.
Signed-off-by: Fam Zheng
---
stubs/set-fd-handler.c | 8
1 file changed, 8 insertions(+)
diff --git a/stubs/set-fd-handler.c b/stubs/set-fd-handler.c
i
Done with following Coccinelle semantic patch, plus manual cosmetic changes in
net/*.c.
@@
expression E1, E2, E3, E4;
@@
- qemu_set_fd_handler2(E1, NULL, E2, E3, E4);
+ qemu_set_fd_handler(E1, E2, E3, E4);
Signed-off-by: Fam Zheng
---
blockdev-nbd.c | 4 ++--
ma
Signed-off-by: Fam Zheng
---
include/qemu/main-loop.h | 8
iohandler.c | 9 -
stubs/set-fd-handler.c | 8
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h
index 7da1d63..0f4a0fd 100644
---
This callback is called by main loop before polling s->fd, if it returns
false, the fd will not be polled in this iteration.
This is redundant with checks inside read callback. After this patch,
the data will be sent to peer when it arrives. If the device can't
receive, it will be queued to incomi
This callback is called by main loop before polling s->fd, if it returns
false, the fd will not be polled in this iteration.
This is redundant with checks inside read callback. After this patch,
the data will be sent to peer when it arrives. If the device can't
receive, it will be queued to incomi
This callback is called by main loop before polling s->fd, if it returns
false, the fd will not be polled in this iteration.
This is redundant with checks inside read callback. After this patch,
the data will be copied from s->fd to s->msgvec when it arrives. If the
device can't receive, it will b
qemu_set_fd_handler cannot fail, let's always return 0.
Signed-off-by: Fam Zheng
---
util/event_notifier-posix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/util/event_notifier-posix.c b/util/event_notifier-posix.c
index 8442c6e..ed4ca2b 100644
--- a/util/event_notifier
This callback is called by main loop before polling s->fd, if it returns
false, the fd will not be polled in this iteration.
This is redundant with checks inside read callback. After this patch,
the data will be copied from s->fd to s->iov when it arrives. If the
device can't receive, it will be q
v3: Replace previous 13 with a simple return type conversion patch.
Drop RFC.
This carries out the mandate in the comment of qemu_set_fd_handler2 and removes
fd_read_poll from the code base, because it will make the work easier to
convert ppoll to epoll in main loop. Also, the aio interface d
Achieved by:
- Remembering the server fd with a global variable, in order to access
it from nbd_client_closed.
- Checking nbd_can_accept() and updating server_fd handler whenever
client connects or disconnects.
Signed-off-by: Fam Zheng
Reviewed-by: Paolo Bonzini
---
qemu-nbd.c | 21 ++
Hello All:
I also found another bug: I did not set the system call error number to
r1 register, which will cause new_heap() fail although mmap64 succeed.
Hope it is my last bug for printing "Hello world" executable binary.
Thanks.
On 05/12/2015 07:16 PM, Chen Gang wrote:
> On 05/12/2015 07:08 P
If passwordless "sudo" works, use it in the qemu-io cmd.
Signed-off-by: Fam Zheng
---
tests/qemu-iotests/128 | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/128 b/tests/qemu-iotests/128
index 249a865..e2a0f2f 100755
--- a/tests/qemu-iotests/128
+++ b/tes
Hi,
I'm testing PCIe root port (ioh3420) on ARM64. Firstly I use following
simple command line to check whether it works.
qemu-system-aarch64 -M virt -device ioh3420
But it fails with below log:
qemu-system-aarch64: -device ioh3420: Device initialization failed
qemu-system-aarch64: -device ioh3
On Mon, 05/18 20:35, Max Reitz wrote:
> On 15.05.2015 08:04, Fam Zheng wrote:
> >So that NBD export cannot submit IO during bdrv_drain_all().
> >
> >Signed-off-by: Fam Zheng
> >---
> > nbd.c | 18 ++
> > 1 file changed, 18 insertions(+)
>
> But can_read is not cleared until nbd_u
On 2015/5/19 0:17, Michael S. Tsirkin wrote:
> On Thu, May 14, 2015 at 05:19:33PM +0800, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > Add ToUUID macro, this is useful for generating PCIe ACPI table.
>> >
>> > Signed-off-by: Shannon Zhao
>> > Signed-off-by: Shannon Zhao
>> > ---
>> >
On Mon, May 18, 2015 at 07:53:05PM +0100, Peter Maydell wrote:
> On 13 May 2015 at 07:52, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Hi,
> >
> > This is round 3 of our series towards support for EL2 for AArch64.
> > This series depends on Gregs exception target el infrastructu
On Mon, May 18, 2015 at 07:41:29PM +0100, Peter Maydell wrote:
> On 13 May 2015 at 07:52, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-arm/helper.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/target-arm/
On Tue, May 19, 2015 at 9:11 AM, Alistair Francis
wrote:
> Firstly this patch series tidies up some code and removes
> a "xlnx." prefix.
>
Sorry about the spam. Not all of the emails went through the first
time, so I swapped SMTP servers and am re-sending.
Thanks,
Alistair
> Then it moves the
Originally the use-fpu PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
---
Changes since RFC:
- Tidy up the if logic
hw/microblaze/petalogix_ml605_mmu.c |4 ++--
target-microb
On 04/20/2015 10:57 AM, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
RDMA migration currently relies on the source and destination RAMBlocks
having the same offsets within ram_addr_t space; unfortunately that's
just not true when:
a) You hotplug on the source but then
Hello,
I am a newcomer on QEMU so I would like to ask a few questions about the way
QEMU works before beginning to develop.
After some experiments and after having read the source code I understood that
the time (the clocks) on which the timers are based in QEMU depends:
on the host clock
on t
Save the timer target value in the SPT helper, so that the STPT helper
can compute the remaining time.
This allow the Linux kernel to correctly do time accounting.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/misc_helper.c | 7 ---
1 file changed
The STCKC instruction just returns the last written clock comparator
value and KVM already provides the corresponding variable.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/misc_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff
The clock comparator and the QEMU timer work the same way, triggering
at a given time, they just differ by the origin and the scale. It is
therefore possible to go from one to another without using the current
clock value. This spares two calls to qemu_clock_get_ns, which probably
return slightly d
Now that clock_value is only used in one place, we can inline it in
the STCK helper.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/misc_helper.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target-s390x/misc_helper.c b/t
This patch series cleans and improves the time-of-day clock and CPU
timer. Most notably it implements the STPT instruction, which allow
the Linux kernel to do time accouting (so top reports correct values).
Aurelien Jarno (5):
target-s390x: add a tod2time function
target-s390x: simplify SCKC h
Add a tod2time function similar to the time2tod one, instead of open
coding the conversion.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-s390x/cpu.h | 5 +
target-s390x/misc_helper.c | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
di
On POWER8 systems, KVM checks if VCPU is running on primary threads,
and that secondary threads are offline. If this is not the case,
ioctl() fails with errno set to EBUSY.
QEMU aborts with a non explicit error message:
$ ./qemu-system-ppc64 --nographic -machine pseries,accel=kvm
error: kvm run fa
From: Prem Mallappa
ARM SMMU requires PCI read/write memory requestors' Identification. This
will propogate the "Device" information all the way till IOMMU device.
ARM SMMU uses the device's ARID to index into tables on a per device basis.
The ARM SMMU v3 device emulation will follow this patch s
From: Prem Mallappa
ARM SMMU requires PCI read/write memory requestors' Identification. This
will propogate the "Device" information all the way till IOMMU device.
ARM SMMU uses the device's ARID to index into tables on a per device basis.
The ARM SMMU v3 device emulation will follow this patch s
From: Prem Mallappa
Signed-off-by: Prem Mallappa
---
exec.c| 48 +---
include/exec/memory.h | 9 +
include/hw/pci/pci.h | 8 +++-
include/sysemu/dma.h | 17 +
4 files changed, 74 insertions(+), 8 deletio
From: Prem Mallappa
Signed-off-by: Prem Mallappa
---
exec.c| 48 +---
include/exec/memory.h | 9 +
include/hw/pci/pci.h | 8 +++-
include/sysemu/dma.h | 17 +
4 files changed, 74 insertions(+), 8 deletio
Hi...
This is still a problem with the latest build(qemu-wXX-setup-20150510.exe).
I've tried with several different versions from the MinGW, neither work
So, which is the correct NinGW version ?
Thanks
JR
--
You received this bug notification because you are a member of qemu-
devel-ml, whi
On Thu, May 14, 2015 at 02:46:44PM +0100, Andrew Jones wrote:
> On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
> > On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote:
> > > Provide a method to change normal, cacheable memory to non-cacheable.
> > > KVM will make use of
On 03/09/2015 06:24 PM, Mark Cave-Ayland wrote:
> This patchset attempts to separate out the IDE/ATAPI logic from the unaligned
> DMA access logic for macio which provides the following benefits:
>
> 1) Reduced code complexity
>
> The existing macio IDE/ATAPI functions were becoming extremely d
On 18 May 2015 at 17:42, Peter Maydell wrote:
> Thanks for this patch; it's a dup of this one already on-list
> and reviewed:
> http://patchwork.ozlabs.org/patch/459490/
>
> Riku: ping? or should I just take this via target-arm?
I went ahead and did the latter, since I'm doing a pullreq anyway.
From: Peter Crosthwaite
Create a new header for Cadence GEM to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Te
On 8 April 2015 at 22:05, Peter Maydell wrote:
> On 8 April 2015 at 21:40, Timothy E Baldwin
> wrote:
>> Misspelled system call name in macro was causing timerfd_create not
>> to be supported for the ARM target.
>>
>> Signed-off-by: Timothy Edward Baldwin
>
> Thanks for the respin.
Now applied
From: Peter Crosthwaite
With quad Cortex-A53 CPUs.
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Tested-by: Alistair Francis
Reviewed-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
Message-id:
a16202a6c7b79e446e5289d38cb1
From: Peter Crosthwaite
Cleanup some variable names in preparation for migrating the state
struct and type cast macro to a public header. The acronym "GEM" on
its own is not specific enough to be used in a more global namespace
so preface with "cadence". Fix the capitalisation of "gem" in the
sta
From: Peter Crosthwaite
Clean up some variable names in preparation for migrating the state struct
and type cast macro to a public header. The acronym "UART" on it's own is
not specific enough to be used in a more global namespace so preface with
"cadence". Fix the capitalisation of "uart" in the
From: Peter Crosthwaite
There are 4x Cadence GEMs in ZynqMP. Add them.
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
Message-id:
7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
---
h
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
Message-id: 1431499963-1019-3-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b6d2310..21b
From: Peter Crosthwaite
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
Message-id:
a7866a4f0c903c91fa3034210b4d2879aa4bfcb9.1431381507.git.peter.crosthwa...@xilinx.com
Si
0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20150518-3
for you to fetch changes up to 18084b2f71b22b3ec3bf4828b8cb83d1d39e8502:
target-arm: Remove unneeded '+' (2015-
From: Peter Crosthwaite
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
Message-id:
2c25e2a4198402a6477aef2975d5df7c415dd341.1431381507.git.peter.crosthwa...@xilinx.com
Signed-off-by
From: Timothy Baldwin
Misspelled system call name in macro was causing timerfd_create not
to be supported for the ARM target.
Signed-off-by: Timothy Edward Baldwin
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
linux-user/arm/syscall_nr.h | 2 +-
1 file changed, 1 insertion(+),
From: Peter Crosthwaite
Rename some A57 CP register variables in preparation for support for
Cortex A53. Use "a57_a53" to describe the shareable features. Some of
the CP15 registers (such as ACTLR) are specific to implementation, but
we currently just RAZ them so continue with that as the policy
From: Peter Crosthwaite
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
under-decoded through a 64k address region so implement aliases
accordingly.
Signed-off-by: Peter Crosthwaite
Message-id:
5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwa...@xilin
From: Greg Bellows
Adds a utility function for creating a WFx exception syndrome
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
Acked-by: Edgar E. Iglesias
Message-id: 1429722561-12651-9-git-send-email-greg.bell...@linaro.org
Signed-off-by: Peter Maydell
---
target-arm/internals.h |
From: Peter Crosthwaite
Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
T
From: Peter Crosthwaite
Add bootloader support using standard ARM bootloader.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
Message-id:
b829abaf2b70d02b28e79301553cbd74afc416a1.1431381507.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Mayde
From: Greg Bellows
Add a utility function for choosing the correct TTBR system register based on
the specified MMU index. Add use of function on physical address lookup.
Signed-off-by: Greg Bellows
Acked-by: Edgar E. Iglesias
Message-id: 1429722561-12651-7-git-send-email-greg.bell...@linaro.or
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alex Bennée
Message-id: 1431499963-1019-4-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.
From: Peter Crosthwaite
There are 2x Cadence UARTs in Zynq MP. Add them.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
Message-id:
e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwa...@xilinx.com
Sig
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
Message-id: 1431499963-1019-2-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
From: Peter Crosthwaite
Add the ARM Cortex-A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
con
From: Peter Crosthwaite
Add a machine model for the Xilinx ZynqMP SoC EP108 board.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
Message-id:
3896b34c862f370dc0679e4428bf3848d1f9f83c.14313
From: Greg Bellows
Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the
current EL. Support includes using the different TCR format as well as checks to
insure TTBR1 is not used when in EL2 or EL3.
Signed-off-by: Greg Bellows
Acked-by: Edgar E. Iglesias
Message-id: 14
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