24.04.2015 20:41, Jan Kiszka wrote:
> The subtle difference between "property not found" and "property not
> set" is already confusing enough.
Applied to -trivial, thanks!
/mjt
15.04.2015 17:18, Stefan Berger wrote:
> Fix coding style in one instance.
Applied to -trivial, thanks!
/mjt
09.04.2015 21:32, Stefan Weil wrote:
> All of them were reported by codespell.
> Most typos are in comments, one is in an error message.
Applied to -trivial, thank you!
/mjt
08.04.2015 21:04, Chih-Min Chao wrote:
> patch 1-2
> fix the coding style related to space indent and brance position
>
> patch 3-5
> remove the 'struct' from the type which has been typedef
>
> Chih-Min Chao (5):
> bitops : fix coding style
> ui/vnc : fix coding sty
31.03.2015 20:32, Luiz Capitulino wrote:
> A VM supports only one balloon device, but due to several changes
> in infrastructure the error message got messed up when trying
> to add a second device. Fix it.
...
Heh. Such a huge commit message ;)
Applied to -trivial now. In the large commit text
Applied both patches to -trivial, thank you!
/mjt
Hi Peter,
Does the equation which is mentioned in
http://vm-kernel.org/blog/2009/07/10/qemu-internal-part-2-softmmu/ means
something?
host_virtual_address = phys_ram_base(qemu variable) +
guest_physical_address – guest_physical_address_base(0 in MIPS)
Currently I have the guest physical address and
On 04/24/2015 04:57 PM, Noel Burton-Krahn wrote:
> Thanks, Corey.
>
> How does the lan_config_program in lan.conf work? I couldn't find an
> example in the OpenIPMI-2.0.21 tarball. Our central controller
> expects each node's ipmi module to dhcp for an address. I'm trying to
> decide if I need t
Hi Brendan,
On 04/24/2015 03:50 PM, Brendan Dolan-Gavitt wrote:
> One possible option that has come up in the past is disabling the TLB
> for your testing. It is slower, though, and would only work on TCG,
> not KVM.
>
> The way I'm currently doing this is by changing the conditional jump
> here
Thanks, Corey.
How does the lan_config_program in lan.conf work? I couldn't find an
example in the OpenIPMI-2.0.21 tarball. Our central controller expects
each node's ipmi module to dhcp for an address. I'm trying to decide if I
need to run dhcpc on the interface that ipmi_sim runs on. Can I j
Somehow these GPUs manage not to respond to a PCI bus reset, removing
our primary mechanism for resetting graphics cards. The result is
that these devices typically work well for a single VM boot. If the
VM is rebooted or restarted, the guest driver is not able to init the
card from the dirty sta
On 04/24/2015 10:20 AM, Kashyap Chamarthy wrote:
> On Fri, Apr 24, 2015 at 11:52:00AM -0400, John Snow wrote:
>>
>> On 04/24/2015 04:32 AM, Kashyap Chamarthy wrote:
>
> [. . .]
>
>> These:
>>
>>> block-dirty-bitmap-add
>>> block-dirty-bitmap-clear
>>>
>>
>> Aren't merged yet, so it might
Windows seems to send two separate calls to NVMe controller configuration. The
first sends configuration info and the second the enable bit. I couldn't
enable the Windows 8.1 in-box NVMe driver with base Qemu. I made the
following change to store the configuration data and then handle enable and
NV
Clean up some variable names in preparation for migrating the state struct
and type cast macro to a public header. The acronym "UART" on it's own is
not specific enough to be used in a more global namespace so preface with
"cadence". Fix the capitalisation of "uart" in the state type while touching
Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwai
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use macro for GIC_INTERNAL
hw/arm/xlnx-zynqmp.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw/arm/xlnx-zyn
Create a new header for Cadence GEM to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwait
Add a machine model for the Xilinx ZynqMP SoC EP108 board.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Chaned since v1:
Change board name to ep108
hw/arm/Makefile.objs | 2 +-
hw/arm/xlnx-ep108.c | 53 +++
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
board.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs are added. The
pre-existing models for GEM and UART are not SoC friendly (no vis
Cleanup some variable names in preparation for migrating the state
struct and type cast macro to a public header. The acronym "GEM" on
its own is not specific enough to be used in a more global namespace
so preface with "cadence". Fix the capitalisation of "gem" in the
state type while touching the
With quad Cortex-A53 CPUs.
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Tested-by: Alistair Francis
Reviewed-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4 (PMM review):
Squashed in PSCI stuffs.
Add (c) info to new header
Remove extra
Add bootloader support using standard ARM bootloader.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Add loader_start field
Make commit message body standalone.
hw/arm/xlnx-ep108.c | 9 +
1 file changed, 9 insertions(+)
Rename some A57 CP register variables in preparation for support for
Cortex A53. Use "a57_a53" to describe the shareable features. Some of
the CP15 registers (such as ACTLR) are specific to implementation, but
we currently just RAZ them so continue with that as the policy for both
A57 and A53 proce
Add the ARM cortex A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.
Si
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use memory_region_allocate_system_memory
Change too-small warning to be qemu_log
changed since v1:
Add ram size cla
On Fri, Apr 24, 2015 at 12:31 PM, Peter Crosthwaite
wrote:
> Hi Peter and all,
>
> Xilinx's next gen SoC has been announced. This series adds a SoC and
> board.
>
> Series start with addition of ARM cortex A53 support (P1 and P2). The
> Soc skeleton is then added with GIC, EMACs and UARTs are adde
On 04/24/2015 07:35 AM, Fam Zheng wrote:
Signed-off-by: Fam Zheng
---
tests/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefile b/tests/Makefile
index 55aa745..b6c0f18 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -343,7 +343,7 @@ tests/virtio-b
On 04/24/2015 07:35 AM, Fam Zheng wrote:
Signed-off-by: Fam Zheng
---
tests/libqos/malloc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/libqos/malloc.c b/tests/libqos/malloc.c
index 67f3190..c15be89 100644
--- a/tests/libqos/malloc.c
+++ b/tests/libqos/malloc.c
@@ -283,6 +2
One possible option that has come up in the past is disabling the TLB
for your testing. It is slower, though, and would only work on TCG,
not KVM.
The way I'm currently doing this is by changing the conditional jump
here to an absolute one inside of the TCG code generator for i386 (and
of course y
Cc: Blue Swirl
Cc: Riku Voipio
Cc: "Michael S. Tsirkin"
Signed-off-by: Eduardo Habkost
---
hw/i386/kvm/clock.c | 4 +-
hw/i386/pc.c | 2 +-
linux-user/elfload.c | 2 +-
linux-user/main.c | 4 +-
target-i386/cpu-qom.h | 11 +++
target-i386/cpu.c
checkpatch.pl doesn't like the extra spaces inside the square brackets,
but the alignment makes the code easier to read. Add a "+ 0" to keep
alignment while making checkpatch.pl happy.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
Instead of using the next field in the struct (that's a moving target
because we are gradually moving fields to X86CPU), add an empty struct
as a marker (like we already did with {start,end}_init_save).
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 2 +-
target-i386/cpu.h | 1 +
2 files
This patch depends on the X86CPU conversion patches I have sent earlier today.
The full series can be seen on the git branch at:
git://github.com/ehabkost/qemu-hacks.git work/x86-cpu-move-cpuid-fields
Eduardo Habkost (3):
target-i386: Coding style fix on x86_cpuid_set_vendor()
target-i386:
Add a machine model for the Xilinx ZynqMP SoC EP108 board.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Chaned since v1:
Change board name to ep108
hw/arm/Makefile.objs | 2 +-
hw/arm/xlnx-ep108.c | 53 +++
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use memory_region_allocate_system_memory
Change too-small warning to be qemu_log
changed since v1:
Add ram size cla
Create a new header for Cadence GEM to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwait
Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwai
Add bootloader support using standard ARM bootloader.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Add loader_start field
Make commit message body standalone.
hw/arm/xlnx-ep108.c | 9 +
1 file changed, 9 insertions(+)
Add the GIC and connect IRQ outputs to the CPUs.
Signed-off-by: Peter Crosthwaite
---
changed since v5:
Make commit msg body standalone
Add reset-cbar configuration
hw/arm/xlnx-zynqmp.c | 30 ++
include/hw/arm/xlnx-zynqmp.h | 2 ++
2 files changed, 32 insert
Cleanup some variable names in preparation for migrating the state
struct and type cast macro to a public header. The acronym "GEM" on
its own is not specific enough to be used in a more global namespace
so preface with "cadence". Fix the capitalisation of "gem" in the
state type while touching the
Clean up some variable names in preparation for migrating the state struct
and type cast macro to a public header. The acronym "UART" on it's own is
not specific enough to be used in a more global namespace so preface with
"cadence". Fix the capitalisation of "uart" in the state type while touching
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
board.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs are added. The
pre-existing models for GEM and UART are not SoC friendly (no vis
With quad Cortex-A53 CPUs.
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Tested-by: Alistair Francis
Reviewed-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Add has_el3
changed since v4 (PMM review):
Squashed in PSCI stuffs.
Add (c) info to new header
Rename some A57 CP register variables in preparation for support for
Cortex A53. Use "a57_a53" to describe the shareable features. Some of
the CP15 registers (such as ACTLR) are specific to implementation, but
we currently just RAZ them so continue with that as the policy for both
A57 and A53 proce
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use macro for GIC_INTERNAL
hw/arm/xlnx-zynqmp.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw/arm/xlnx-zyn
Add the ARM cortex A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.
Si
Signed-off-by: Eduardo Habkost
---
target-i386/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 305ce50..fdbb4af 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4402,9 +4402,10 @@ st
On Fri, 24 Apr 2015, Daniel Stekloff wrote:
Windows seems to send two separate calls to NVMe controller configuration. The
first sends configuration info and the second the enable bit. I couldn't
enable the Windows 8.1 in-box NVMe driver with base Qemu. I made the
following change to store the co
Signed-off-by: Eduardo Habkost
---
hw/intc/apic.c| 2 +-
target-i386/cpu.c | 4 ++--
target-i386/cpu.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 2f19c19..175e601 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -298,7 +298,
On Thu, Apr 23, 2015 at 5:43 PM, Peter Crosthwaite
wrote:
> On Thu, Apr 23, 2015 at 11:15 AM, Peter Maydell
> wrote:
>> On 23 March 2015 at 11:05, Peter Crosthwaite
>> wrote:
>>> Using standard ARM bootloader.
>>
>> Commit msg, etc.
>>
>>> Signed-off-by: Peter Crosthwaite
>>> ---
>>> hw/arm/xl
On 04/24/2015 08:46 AM, Peter Maydell wrote:
> On 24 April 2015 at 12:26, Paolo Bonzini wrote:
>> On 24/04/2015 04:10, Wenjie Liu wrote:
>>> The thing I am trying to achieve is to get the data and guest physical
>>> address of every guest memory access, so I need to known which API can
>>> be used
From: Eric Blake
Pretending that QMP doesn't understand a command merely because
we are not in the right mode doesn't help first-time users figure
out what to do to correct things. Although the documentation for
QMP calls out capabilities negotiation, we should also make it
clear in our error me
The following changes since commit e5b3a24181ea0cebf1c5b20f44d016311b7048f0:
Update version for v2.3.0 release (2015-04-24 15:05:06 +0100)
are available in the git repository at:
git://repo.or.cz/qemu/qmp-unstable.git tags/for-upstream
for you to fetch changes up to 2d5a8346a484250934526a15
A VM supports only one balloon device, but due to several changes
in infrastructure the error message got messed up when trying
to add a second device. Fix it.
Before this fix
Command-line:
qemu-qmp: -device virtio-balloon-pci,id=balloon0: Another balloon device
already registered
qemu-qmp: -de
From: Eric Blake
Defaulting a parameter to True, then having all callers omit or
pass an explicit True for that parameter, is pointless. Looks
like it has been dead since introduction in commit 06d64c6, more
than 4 years ago.
Signed-off-by: Eric Blake
Signed-off-by: Luiz Capitulino
---
script
From: Paolo Bonzini
As far as the QMP parser is concerned, neither the 'O' nor the 'q' format
specifiers
put any constraint on the command. However, there are two differences:
1) from a documentation point of view 'O' says that this command takes
a dictionary. The dictionary will be converted
On Fri, Apr 24, 2015 at 10:41 AM, Jan Kiszka wrote:
> The subtle difference between "property not found" and "property not
> set" is already confusing enough.
>
> Signed-off-by: Jan Kiszka
Reviewed-by: Peter Crosthwaite
> ---
> backends/hostmem-file.c | 2 +-
> 1 file changed, 1 insertion(+),
Cc: Blue Swirl
Cc: Riku Voipio
Cc: "Michael S. Tsirkin"
Signed-off-by: Eduardo Habkost
---
bsd-user/main.c | 2 +-
hw/i386/pc.c | 3 +--
linux-user/main.c| 2 +-
target-i386/cpu.h| 2 +-
target-i386/kvm.c| 2 +-
target-i386/seg_helper.c | 2 +-
6 fi
Signed-off-by: Eduardo Habkost
---
hw/intc/apic.c | 4 ++--
target-i386/cpu.h| 2 +-
target-i386/helper.c | 7 +++
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 0f97b47..2f19c19 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 4 ++--
target-i386/cpu.h | 2 +-
target-i386/kvm.c | 20 ++--
target-i386/misc_helper.c | 3 ++-
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.h| 2 +-
target-i386/helper.c | 6 +++---
target-i386/kvm.c| 3 +--
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 4ee12ca..5f4dab1 100644
--- a/target-i386/cpu.h
+++ b/target-i3
Eduardo Habkost (5):
target-i386: Use X86CPU on cpu_x86_support_mca_broadcast()
target-i386: Use X86CPU on cpu_x86_version()
target-i386: Use X86CPU on cpu_get_pic_interrupt()
target-i386: Use X86CPU on cpu_report_tpr_access()
target-i386: Use X86CPU on cpu_x86_cpuid()
bsd-user/main.c
Signed-off-by: Eduardo Habkost
---
target-i386/helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 166a803..215b354 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -25,9 +25,9 @@
#include "monitor/mo
The subtle difference between "property not found" and "property not
set" is already confusing enough.
Signed-off-by: Jan Kiszka
---
backends/hostmem-file.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c
index 5179994..4b5536
On 24 April 2015 at 16:19, Greg Bellows wrote:
> Updated scr_write to always allow updates to the SCR.SMD bit on ARMv8
> regardless of whether virtualization (EL2) is enabled or not.
>
> Signed-off-by: Greg Bellows
> ---
Applied to target-arm.next, thanks.
-- PMM
On Thu, Apr 23, 2015 at 10:50 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> In preparation for migrating the state struct and type cast macro to a public
I have also made this commit message more standalone.
>> header. The acronym "GEM" on it's own is not s
On 04/24/15 16:50, Yao, Jiewen wrote:
> Hi Laszlo
>
> I think there is good resource for your reference - Intel Quark.
> https://downloadcenter.intel.com/download/23197
>
> You may download "Board_Support_Package_Sources_for_Intel_Quark_v1.1.0.7z",
> and find "Quark_EDKII_v1.1.0"
>
> IA32Family
On Mon, Mar 23, 2015 at 6:17 AM, Ryota Ozaki wrote:
> Hi,
>
> On Mon, Mar 23, 2015 at 8:05 PM, Peter Crosthwaite
> wrote:
>> Similar to a53, but with different L1 I cache policy, phys addr size and
> ^^^
> I guess a57 :)
>
Fixed. Thanks.
Regards,
Peter
On Thu, Apr 23, 2015 at 10:35 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> In preparation for support for Cortex a53. Use "axx" to describe the
>> shareable features. Some of the CP15 registers (such as ACTLR) are
>> specific to implementation, but we curren
On Fri, Apr 24, 2015 at 8:26 AM, Peter Maydell wrote:
> On 23 April 2015 at 22:38, Peter Maydell wrote:
>> On 23 April 2015 at 20:21, Peter Crosthwaite
>> wrote:
>>> On Thu, Apr 23, 2015 at 10:42 AM, Peter Maydell
>>> wrote:
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> -
On 04/24/2015 12:20 PM, Kashyap Chamarthy wrote:
On Fri, Apr 24, 2015 at 11:52:00AM -0400, John Snow wrote:
On 04/24/2015 04:32 AM, Kashyap Chamarthy wrote:
[. . .]
These:
block-dirty-bitmap-add
block-dirty-bitmap-clear
Aren't merged yet, so it might be a little confusing.
On Fri, Apr 24, 2015 at 11:52:00AM -0400, John Snow wrote:
>
> On 04/24/2015 04:32 AM, Kashyap Chamarthy wrote:
[. . .]
> These:
>
> > block-dirty-bitmap-add
> > block-dirty-bitmap-clear
> >
>
> Aren't merged yet, so it might be a little confusing.
Yeah, I expected someone to call tha
On 04/24/2015 04:32 AM, Kashyap Chamarthy wrote:
Although the canonical source of reference for QMP commands is
qapi-schema.json, for consistency's sake, update qmp-commands.hx to
state the list of supported transactionable operations, namely:
drive-backup
blockdev-backup
blockd
On 03.04.2015 16:05, Fam Zheng wrote:
Signed-off-by: Fam Zheng
---
tests/qemu-iotests/129 | 86 ++
tests/qemu-iotests/129.out | 5 +++
tests/qemu-iotests/group | 1 +
3 files changed, 92 insertions(+)
create mode 100644 tests/qemu-iotest
On 23 April 2015 at 22:38, Peter Maydell wrote:
> On 23 April 2015 at 20:21, Peter Crosthwaite
> wrote:
>> On Thu, Apr 23, 2015 at 10:42 AM, Peter Maydell
>> wrote:
>>> On 23 March 2015 at 11:05, Peter Crosthwaite
>>> wrote:
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@
Updated scr_write to always allow updates to the SCR.SMD bit on ARMv8
regardless of whether virtualization (EL2) is enabled or not.
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
Allows sysbus devices to be instantiated from command line by
using -device option. Machvirt creates a platform bus at init.
The dynamic sysbus devices are attached to this platform bus device.
The platform bus device registers a machine init done notifier
whose role will be to bind the dynamic sy
Re-indent in a15memmap after VIRT_PLATFORM_BUS introduction
Signed-off-by: Eric Auger
Reviewed-by: Alex Bennée
---
v11 -> v12:
- Add Alex R-b
---
hw/arm/virt.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index
This new C module will be used by ARM machine files to generate
platform bus node and their dynamic sysbus device tree nodes.
Dynamic sysbus device node addition is done in a machine init
done notifier. arm_register_platform_bus_fdt_creator does the
registration of this latter and is supposed to b
On 24.04.2015 17:01, Alberto Garcia wrote:
This patch tests that in a partial block-stream operation, no data is
ever copied from the base image.
Signed-off-by: Alberto Garcia
---
tests/qemu-iotests/030 | 18 ++
tests/qemu-iotests/030.out | 4 ++--
2 files changed, 20 i
This patch series enables machvirt to dynamically instantiate sysbus
devices from command line (using -device option).
All those sysbus devices are plugged onto a platform bus. This latter
device is instantiated in machvirt and takes care of the binding of
children sysbus devices on a machine init
Device tree nodes for the platform bus and its children dynamic sysbus
devices are added in a machine init done notifier. To load the dtb once,
after those latter nodes are built and before ROM freeze, the actual
arm_load_kernel existing code is moved into a notifier notify function,
arm_load_kerne
This patch makes the 'device' parameter of the 'block-stream' command
accept a node name as well as a device name.
In addition to that, operation blockers will be checked in all
intermediate nodes between the top and the base node.
Since qmp_block_stream() now uses the error from bdrv_lookup_bs()
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
Reviewed-by: Eric Blake
---
docs/live-block-ops.txt | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/docs/live-block-ops.txt b/docs/live-block-ops.txt
index a257087..a05d869 100644
--- a/do
This test case checks that it's not possible to perform two
block-stream operations if there are nodes involved in both.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
tests/qemu-iotests/030 | 27 +++
tests/qemu-iotests/030.out | 4 ++--
2 files changed, 2
Currently, block jobs can only be owned by root nodes. This patch
allows block jobs to be in any arbitrary node, by making the following
changes:
- Block jobs can now be identified by the node name of their
BlockDriverState in addition to the device name. Since both device
and node names live
This adds test_stream_intermediate(), similar to test_stream() but
streams to the intermediate image instead.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
tests/qemu-iotests/030 | 18 +-
tests/qemu-iotests/030.out | 4 ++--
2 files changed, 19 insertions(+), 3 d
This test case checks that it's possible to launch several stream
operations in parallel in the same snapshot chain, each one involving
a different set of nodes.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
tests/qemu-iotests/030 | 80
This patch tests that in a partial block-stream operation, no data is
ever copied from the base image.
Signed-off-by: Alberto Garcia
---
tests/qemu-iotests/030 | 18 ++
tests/qemu-iotests/030.out | 4 ++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/tests
The current way to obtain the list of existing block jobs is to
iterate over all root nodes and check which ones own a job.
Since we want to be able to support block jobs in other nodes as well,
this patch keeps a list of jobs that is updated every time one is
created or destroyed.
This also upda
This test is streaming to the top layer using the intermediate image
as the base. This is a mistake since block-stream never copies data
from the base image and its backing chain, so this is effectively a
no-op.
In addition to fixing the base parameter, this patch also writes some
data to the inte
We need to call stream_complete() in order to do all the necessary
clean-ups, even if there's an early failure. At the moment it's only
useful to make sure that s->backing_file_str is not leaked, but it
will become more important as we introduce support for streaming to
any intermediate node.
Sign
v6:
- fix the no-op test following Max's suggestions
v5: https://lists.gnu.org/archive/html/qemu-devel/2015-04/msg03006.html
- Fix a few typos
- Minor documentation updates
- Update test_stream_partial() to test no-ops
- New test case: test_stream_parallel()
- New test case: test_stream_overlappin
This makes sure that the image we are steaming into is open in
read-write mode during the operation.
Operation blockers are also set in all intermediate nodes, since they
will be removed from the chain afterwards.
Finally, this also unblocks the stream operation in backing files.
Signed-off-by:
On 18.03.2015 21:56, Max Reitz wrote:
This series adds support to qemu for changing the refcount_bits option
of an existing qcow2 file through the qemu-img amend command.
Originally (up until v7), this series was called
"qcow2: Support refcount orders != 4", but by now that support has
already b
Hi Laszlo
I think there is good resource for your reference - Intel Quark.
https://downloadcenter.intel.com/download/23197
You may download "Board_Support_Package_Sources_for_Intel_Quark_v1.1.0.7z", and
find "Quark_EDKII_v1.1.0"
IA32FamilyCpuBasePkg\PiSmmCpuDxeSmm - it is CPUSMM driver.
IA32Fam
On 19.03.2015 19:53, Max Reitz wrote:
BDRV_O_PROTOCOL is an internal qemu flag which a user should be able to
override by explicitly specifying a block driver. This series implements
this and adds two iotests (one for NBD, one for file) to test it.
v2 (rebase on current master):
- Patch 1: Conf
On Fri, Apr 17, 2015 at 07:49:48PM -0400, John Snow wrote:
> It's spring! The winter snow has thawed and so here is a new
> patch series to enter your life and warm your heart.
>
> This patchset enables the in-memory part of the incremental backup
> feature, without transactional support.
>
> Sup
On 24.04.2015 15:55, Alberto Garcia wrote:
On Fri 24 Apr 2015 03:19:54 PM CEST, Max Reitz wrote:
This patch updates test_stream_partial() to test that the
block-stream operation never copies data from the image specified as
base.
I think it would be better to add this as an own test case. But
On Fri 24 Apr 2015 03:19:54 PM CEST, Max Reitz wrote:
>> This patch updates test_stream_partial() to test that the
>> block-stream operation never copies data from the image specified as
>> base.
>
> I think it would be better to add this as an own test case. But I
> won't oppose adding it as a sp
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