Signed-off-by: Fam Zheng
---
tests/Makefile| 2 +
tests/test-poll.c | 272 ++
2 files changed, 274 insertions(+)
create mode 100644 tests/test-poll.c
diff --git a/tests/Makefile b/tests/Makefile
index 55aa745..d152bf5 100644
--- a/tests/
In qemu_poll_timerfd, we arm the timerfd with timeout_ns. The timerfd is
also watched by epollfd, so that when there is no other events,
epoll_wait will still return on time, even though we pass -1 (wait
infinitely).
Signed-off-by: Fam Zheng
---
poll-linux.c | 84
Signed-off-by: Fam Zheng
---
poll-glib.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/poll-glib.c b/poll-glib.c
index 64fde69..23d528d 100644
--- a/poll-glib.c
+++ b/poll-glib.c
@@ -14,6 +14,9 @@
#include "qemu-common.h"
#include "qemu/timer
qemu_poll_set_fds + qemu_poll does the same, and when epoll is
available, it is faster.
Signed-off-by: Fam Zheng
---
include/qemu/timer.h | 13 -
main-loop.c | 35 ++-
qemu-timer.c | 28
3 files changed, 30
The AIO handler list is only modified by aio_set_fd_handler, so we can
easily add del poll fd there. Initialize a QEMUPoll and keep track of
all the fds, so we don't need to rebuild a GPollFD array for g_poll in
aio_poll.
Signed-off-by: Fam Zheng
---
aio-posix.c | 52
This is abstract of underlying poll implementation. A glib
implementation is included.
Signed-off-by: Fam Zheng
---
Makefile.objs | 2 +-
include/qemu/poll.h | 40 +++
include/qemu/typedefs.h | 4 +-
poll-glib.c | 130 +++
This implements qemu_poll with ppoll + epoll. The only complex part is
qemu_poll_set_fds, which will sync up epollfd with epoll_ctl by
computing the symmetric difference of previous and new fds.
The ppoll is used to retain ns precision of timeout.
Signed-off-by: Fam Zheng
---
Makefile.objs |
v3: Rebase to master for 2.4.
Although epoll_pwait1 syscall is still being worked on [1], the QEMU part
(if any) will base on this, so let's merge it first.
That part is not included in this version because I'm still evaluating by
comparing epoll_pwait1 with epoll+timerfd as wi
From: Chen Fan
Due to local apic address is in view of CPU's address space,
so able to move apic mapping to each apic realizefn.
Signed-off-by: Chen Fan
Signed-off-by: Zhu Guihua
---
exec.c| 5 +
hw/i386/pc.c | 7 ---
hw/intc/apic_common.c | 14 -
From: Chen Fan
ICC bus was invented only to provide hotplug capability to
CPU and APIC because at the time being hotplug was available only for
BUS attached devices.
Now this patch is to drop ICC bus impl, and switch to bus-less
CPU+APIC hotplug, handling them in the same manner as pc-dimm.
and
ICC Bus was used for providing a hotpluggable bus for APIC and CPU,
but now we use HotplugHandler to make hotplug. So ICC Bus is
unnecessary.
This code has passed the new pc-cpu-test.
And I have tested with kvm along with kernel_irqchip=on/off,
it works fine.
v4:
-add wrapper to get root memory
Use DEVICE() casts to avoid accessing ICCDevice's qdev field
directly.
Signed-off-by: Zhu Guihua
---
hw/intc/apic.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 0f97b47..00ae0ec 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@
ICC bus impl has been droped, so all icc related files are not useful
any more; delete them.
Signed-off-by: Zhu Guihua
---
default-configs/i386-softmmu.mak | 1 -
default-configs/x86_64-softmmu.mak | 1 -
hw/cpu/Makefile.objs | 1 -
hw/cpu/icc_bus.c | 118
On Wed, 04/15 11:17, Konstantin Krotov wrote:
> Hello list!
>
> I performed tests with fio and obtained results:
>
> *** virtio-scsi with cache=none, io=threads, blok device is md-device from
> mdadm raid1, random r/w, 32 thread from guest (debian, kernel 3.16):
>
> fio fio1
> readtest: (g=0): r
> -Original Message-
> From: Stefan Berger [mailto:stef...@linux.vnet.ibm.com]
> Sent: Wednesday, April 15, 2015 10:50 PM
> To: Xu, Quan; stefano.stabell...@eu.citrix.com; ebl...@redhat.com
> Cc: wei.l...@citrix.com; qemu-devel@nongnu.org; xen-de...@lists.xen.org;
> aligu...@amazon.com; p
> -Original Message-
> From: Stefan Berger [mailto:stef...@linux.vnet.ibm.com]
> Sent: Wednesday, April 15, 2015 10:56 PM
> To: Xu, Quan; stefano.stabell...@eu.citrix.com; ebl...@redhat.com
> Cc: wei.l...@citrix.com; qemu-devel@nongnu.org; xen-de...@lists.xen.org;
> aligu...@amazon.com; p
> -Original Message-
> From: Daniel De Graaf [mailto:dgde...@tycho.nsa.gov]
> Sent: Wednesday, April 15, 2015 11:07 PM
> To: Stefan Berger; Xu, Quan
> Cc: stefano.stabell...@eu.citrix.com; ebl...@redhat.com; wei.l...@citrix.com;
> qemu-devel@nongnu.org; xen-de...@lists.xen.org; aligu...@a
Introduce a lock and a condition to notify anyone waiting for the completion
of the execution of a TPM command by the backend (thread). The backend
uses the condition to signal anyone waiting for command completion.
We need to place the condition in two locations: one is invoked by the
backend thre
Rather than integrating TPM functionality into QEMU directly
using the TPM emulation of libtpms, we now integrate an external
emulated TPM device. This device is expected to implement a Linux
CUSE interface (CUSE = character device in userspace).
QEMU talks to the CUSE TPM using much functionality
The following series of patches extends TPM support with an
external TPM that offers a Linux CUSE (character device in userspace)
interface. This TPM lets each VM access its own private vTPM.
The CUSE TPM supports suspend/resume and migration. Much
out-of-band functionality necessary to control the
Extend the TPM TIS code to support suspend/resume. In case a command
is being processed by the external TPM when suspending, wait for the command
to complete to catch the result. In case the bottom half did not run,
run the one function the bottom half is supposed to run. This then
makes the resume
TPM backends will suspend independently of the frontends. Also
here we need to be able to wait for the TPM command to have been
completely processed.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_passthrough.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/tpm/tpm_pas
For automated management of a TPM device, implement the TCG Physical Presence
Interface Specification that allows a root user on Linux (for example) to set
an opcode for a sequence of TPM operations that the BIOS is supposed to execute
upon reboot of the physical or virtual machine. A sequence of o
Add a TPM2 ACPI table if a TPM 2 is used in the backend.
Rename tpm_find() to tpm_get_version() and have this function
return the version of the TPM found, TPMVersion_Unspec if
no TPM is found. Use the version number to build version
specific ACPI tables.
Signed-off-by: Stefan Berger
---
hw/i38
Following the recent upgrade to version 1.3, extend the TPM TIS
interface with capabilities introduced for support of a TPM 2.
TPM TIS for TPM 2 introduced the following extensions beyond the
TPM TIS 1.3 (used for TPM 1.2):
- A new 32bit interface Id register was introduced.
- New flags for the s
In the TPM passthrough backend driver, modify the probing code so
that we can check whether a TPM 1.2 or TPM 2 is being used
and adapt the behavior of the TPM TIS accordingly.
Move the code that tested for a TPM 1.2 into tpm_utils.c
and extend it with test for probing for TPM 2. Have the
function
After the previous upgrade of the TPM TIS to version 1.3,
we now upgrade it to support a TPM 2 in the backend.
Stefan Berger (3):
Extend TPM TIS interface to support TPM 2
tpm: Probe for connected TPM 1.2 or TPM 2
TPM2 ACPI table support
backends/tpm.c | 14 +
hw/i386/ac
On 04/15/2015 10:44 AM, Stefan Berger wrote:
On 04/10/2015 02:59 AM, Quan Xu wrote:
This patch adds infrastructure for xen front drivers living in qemu,
so drivers don't need to implement common stuff on their own. It's
mostly xenbus management stuff: some functions to access XenStore,
setting
Confirm the rc3 is working :)
i will check other softmmu too in this last rc.
small OT because i dont know where ask...
One day will be possible have one emulated core for every host thread like now
do WinUae with qemu core?
Example: 64 power8 cpus emulate 64 x86 cpus in one virtual machine
On 04/15/2015 02:31 PM, Eric Blake wrote:
On 04/15/2015 12:13 PM, John Snow wrote:
On 04/15/2015 11:19 AM, Eric Blake wrote:
Pretending that QMP doesn't understand a command merely because
we are not in the right mode doesn't help first-time users figure
out what to do to correct things. A
On 04/15/2015 12:13 PM, John Snow wrote:
>
>
> On 04/15/2015 11:19 AM, Eric Blake wrote:
>> Pretending that QMP doesn't understand a command merely because
>> we are not in the right mode doesn't help first-time users figure
>> out what to do to correct things. Although the documentation for
>>
On 04/15/2015 11:19 AM, Eric Blake wrote:
Pretending that QMP doesn't understand a command merely because
we are not in the right mode doesn't help first-time users figure
out what to do to correct things. Although the documentation for
QMP calls out capabilities negotiation, we should also ma
Reviewed-by: Paulo Vital
On Wed, 2015-04-15 at 09:19 -0600, Eric Blake wrote:
> Pretending that QMP doesn't understand a command merely because
> we are not in the right mode doesn't help first-time users figure
> out what to do to correct things. Although the documentation for
> QMP calls out c
On 08.04.2015 16:43, Alberto Garcia wrote:
There's only one change in this series: there's now a list of block
jobs that is updated everytime a new one is created or destroyed.
This way we can iterate the list directly, rather than searching all
BlockDriverStates for the ones that own a block jo
On 08.04.2015 16:43, Alberto Garcia wrote:
Signed-off-by: Alberto Garcia
---
docs/live-block-ops.txt | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/docs/live-block-ops.txt b/docs/live-block-ops.txt
index a257087..5e969fd 100644
--- a/doc
On 08.04.2015 16:43, Alberto Garcia wrote:
This patch makes the 'device' paramater of the 'block-stream' command
allow a node name as well as a device name.
s/allow/accept/
In addition to that, operation blockers will be checked in all
intermediate nodes between the top and the base node.
Si
On 08.04.2015 16:43, Alberto Garcia wrote:
This makes sure that the image we are steaming into is open in
read-write mode during the operation.
Operation blockers are also set in all intermediate nodes, since they
will be removed from the chain afterwards.
Finally, this also unblocks the stream
From: Fabian Aggeler
GICs with grouping (GICv2 or GICv1 with Security Extensions) have a
different exception generation model which is more complicated than
without interrupt grouping. We add a new function to handle this model.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v
From: Fabian Aggeler
Prepare to split gic_update() in two functions, one for GICs with
interrupt grouping and one without grouping (existing).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/intc/arm_gic.c | 11 ---
hw/intc/gic_internal.h | 1 +
2 files changed,
From: Fabian Aggeler
GICs with Security Extensions restrict the non-secure view of the
interrupt priority and priority mask registers.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/intc/arm_gic.c | 66 +-
hw/intc/gic_inte
> On 15 Apr 2015, at 15:49, Leon Alrae wrote:
>
> ... If there aren't any objections for the proposed solution, then let's
> just cook up the patch.
the changes related to moving --semihosting-cmdline to the end of the line are
in:
git://git.code.sf.net/p/gnuarmeclipse/qemu gnuarmeclipse-qe
On Wed, Apr 15, 2015 at 09:19:23AM -0600, Eric Blake wrote:
> Pretending that QMP doesn't understand a command merely because
> we are not in the right mode doesn't help first-time users figure
> out what to do to correct things. Although the documentation for
> QMP calls out capabilities negotiat
From: Fabian Aggeler
Grouping (GICv2) and Security Extensions change the behaviour of reads
of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/intc/arm_gic.c | 29 -
hw/intc
From: Fabian Aggeler
Security Extensions for GICv1 and GICv2 use register banking
to provide transparent access to seperate Secure and Non-secure
copies of GIC configuration registers. This function will later
be replaced by code determining the security state of a read/write
access to a register
From: Fabian Aggeler
ICCICR/GICC_CTLR is banked in GICv1 implementations with Security
Extensions or in GICv2 in independent from Security Extensions.
This makes it possible to enable forwarding of interrupts from
the CPU interfaces to the connected processors for Group0 and Group1.
We also allo
From: Fabian Aggeler
ICDDCR/GICD_CTLR is banked in GICv1 implementations with Security
Extensions or in GICv2 in independent from Security Extensions.
This makes it possible to enable forwarding of interrupts from
Distributor to the CPU interfaces for Group0 and Group1.
EnableGroup0 (Bit [1]) in
From: Fabian Aggeler
Grouping (GICv2) and Security Extensions change the behavior of EOIR
writes. Completing Group0 interrupts is only allowed from Secure state
and completing Group1 interrupts from Secure state is only allowed if
AckCtl bit is set.
Signed-off-by: Fabian Aggeler
Signed-off-by:
From: Fabian Aggeler
The existing implementation does not support Security Extensions mentioned
in the GICv1 and GICv2 architecture specification. Security Extensions are
not available on all GICs. This property makes it possible to enable Security
Extensions.
It also makes GICD_TYPER/ICDICTR.S
From: Fabian Aggeler
Preparing for FIQ lines from GIC to CPUs, which is needed for GIC
Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/intc/arm_gic.c| 3 +++
include/hw/intc/arm_gic_common.h | 1 +
2 files changed, 4 insertions(+)
diff --
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Greg Bellows
---
hw/arm/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 565f573..f3326cf 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -386,6 +386,8 @@ static uint32_t cr
From: Fabian Aggeler
Interrupt Group Registers (previously called Interrupt Security
Registers) as defined in GICv1 with Security Extensions or GICv2 allow
to configure interrupts as Secure (Group0) or Non-secure (Group1).
In GICv2 these registers are implemented independent of the existence of
S
From: Fabian Aggeler
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/vexpress.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 3989bc5..c2602a2 100644
--- a/hw/arm
From: Fabian Aggeler
This register is banked in GICs with Security Extensions. Storing the
non-secure copy of BPR in the abpr, which is an alias to the non-secure
copy for secure access. ABPR itself is only accessible from secure state
if the GIC implements Security Extensions.
Signed-off-by: Fa
This patch series adds ARM GICv1 and GICv2 security extension support. As a
result GIC interrupt grouping and FIQ enablement have also been added. FIQ
enablement is limited to ARM the ARM vexpress and virt machines.
At the current moment, the security extension capability is not enabled as it
de
From: Fabian Aggeler
Grouping (GICv2) and Security Extensions change the behavior of IAR
reads. Acknowledging Group0 interrupts is only allowed from Secure
state and acknowledging Group1 interrupts from Secure state is only
allowed if AckCtl bit is set.
Signed-off-by: Fabian Aggeler
Signed-off-
From: Fabian Aggeler
For GICs with Security Extensions Non-secure reads have a restricted
view on the current running priority.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/intc/arm_gic.c | 17 -
hw/intc/gic_internal.h | 1 +
2 files changed, 17 inser
On 08.04.2015 16:43, Alberto Garcia wrote:
We need to call stream_complete() in order to do all the necessary
clean-ups, even if there's an early failure. At the moment it's only
useful to make sure that s->backing_file_str is not leaked,
Which is important enough on its own.
but it
will beco
On 08.04.2015 16:43, Alberto Garcia wrote:
Currently, block jobs can only be owned by root nodes. This patch
allows block jobs to be in any arbitrary node, by making the following
changes:
- Block jobs can now be identified by the node name of their
BlockDriverState in addition to the device
Pretending that QMP doesn't understand a command merely because
we are not in the right mode doesn't help first-time users figure
out what to do to correct things. Although the documentation for
QMP calls out capabilities negotiation, we should also make it
clear in our error messages what we were
On 04/12/2015 10:15 PM, Xu, Quan wrote:
-Original Message-
From: Stefan Berger [mailto:stef...@linux.vnet.ibm.com]
Sent: Monday, April 13, 2015 4:50 AM
To: Xu, Quan; stefano.stabell...@eu.citrix.com; ebl...@redhat.com
Cc: pbonz...@redhat.com; qemu-devel@nongnu.org; aligu...@amazon.com;
On 04/10/2015 02:59 AM, Quan Xu wrote:
This Patch provides the glue for the TPM_TIS(Qemu frontend) to Xen
stubdom vTPM domain that provides the actual TPM functionality. It
sends data and TPM commends with xen_vtpm_frontend. It is similar as
another two vTPM backens:
*vTPM passthrough backen S
On 04/10/2015 02:59 AM, Quan Xu wrote:
This patch adds infrastructure for xen front drivers living in qemu,
so drivers don't need to implement common stuff on their own. It's
mostly xenbus management stuff: some functions to access XenStore,
setting up XenStore watches, callbacks on device disco
On 08.04.2015 16:43, Alberto Garcia wrote:
The current way to obtain the list of existing block jobs is to
iterate over all root nodes and check which ones own a job.
Since we want to be able to support block jobs in other nodes as well,
this patch keeps a list of jobs that is updated everytime
Fix coding style in one instance.
Signed-off-by: Stefan Berger
---
hw/tpm/tpm_tis.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c
index 4b6d601..b8235d5 100644
--- a/hw/tpm/tpm_tis.c
+++ b/hw/tpm/tpm_tis.c
@@ -842,7 +842,7 @@ static v
On Mi, 2015-04-15 at 15:55 +0300, Denis Kirjanov wrote:
> On 4/15/15, Gerd Hoffmann wrote:
> > On Di, 2015-04-14 at 17:47 +0300, Denis Kirjanov wrote:
> >> On 4/14/15, Denis Kirjanov wrote:
> >> > On 4/14/15, Denis Kirjanov wrote:
> >> >> On 4/14/15, Gerd Hoffmann wrote:
> >> >>> Denis Kirjanov
On Wed, 2015-04-15 at 18:30 +0800, Chen Fan wrote:
> On 04/08/2015 11:36 PM, Alex Williamson wrote:
> > On Wed, 2015-04-08 at 16:59 +0800, Chen Fan wrote:
> >> On 04/01/2015 11:46 PM, Alex Williamson wrote:
> >>> On Wed, 2015-04-01 at 12:12 +0800, Chen Fan wrote:
> On 03/25/2015 10:41 AM, Alex
good to know, thanks dominique. I gave it a sniff test with FSX and a few
other benchmarks, but I need to hit it with some multithreaded
regressions. Any pointers to reproducible failure cases would be
beneficial.
On Wed, Apr 15, 2015 at 6:28 AM Dominique Martinet <
dominique.marti...@cea.fr> wr
On 15/04/2015 16:14, Li, Liang Z wrote:
> Yes, it's the right place. Put aside the bug fix, I think the
> memory_region_ref/unref pair
> should be move to xen_pt_region_update after the conditional as you point
> out.
> Do you think so?
It would make sense, but I was just guessing... I'm s
> On 13/04/2015 16:12, Liang Li wrote:
> > 2. Do the attach and detach operation with a time interval. eg. 10s.
> >
> > The error message will not disappear if retry, in this case, it's
> > a bug.
> >
> > In the 'xen_pt_region_add' and 'xen_pt_region_del', we should only
> > care about
On Tue, Apr 14, 2015 at 12:34:02PM +0100, Peter Maydell wrote:
> On 14 April 2015 at 12:27, Gerd Hoffmann wrote:
> > Hi,
> >
> > Damn, wanted to sent this out last week, then forgot, so it missed -rc3.
> > But it is a documentation-only change, so it should still be fine for
> > 2.3, right?
>
>
Hi,
> > d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
> > +d->wmask[MCH_HOST_BRIDGE_SMRAM] = 0xff;
>
> Is this right? I see a bunch of reserved bits etc there.
Restores the state we had before the guest flipped the lock bit.
Entriely possible that we should have a
On Wed, 15 Apr 2015 12:38:57 +0200
"Michael S. Tsirkin" wrote:
> On Tue, Mar 03, 2015 at 05:18:12PM +0100, Igor Mammedov wrote:
> > Changes since v13:
> > * fix comment style to /*... */ in testcase
> > * make BAR TARGET_PAGE_SIZE as required by spec
> > * make BAR prefetchable, spec also says
On Di, 2015-04-14 at 16:35 +0200, Paolo Bonzini wrote:
>
> On 14/04/2015 15:12, Gerd Hoffmann wrote:
> > Signed-off-by: Gerd Hoffmann
> > ---
> > hw/pci-host/q35.c | 17 -
> > 1 file changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q3
From: Shannon Zhao
DSDT consists of the usual common table header plus a definition
block in AML encoding which describes all devices in the platform.
After initializing DSDT with header information the namespace is
created which is followed by the device encodings. The devices are
described usi
From: Shannon Zhao
Introduce a preliminary framework in virt-acpi-build.c with the main
ACPI build functions. It exposes the generated ACPI contents to
guest over fw_cfg.
The required ACPI v5.1 tables for ARM are:
- RSDP: Initial table that points to XSDT
- RSDT: Points to FADT GTDT MADT tables
From: Shannon Zhao
Move generic acpi building helpers into dedictated file and this
can be shared with other machines.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/acpi/aml-build.c | 58 ++
hw/i386/acpi-build.c| 77
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/acpi/aml-build.c | 11 +++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 179acda..eb
From: Shannon Zhao
Add aml_memory32_fixed() for describing device mmio region in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/acpi/aml-build.c | 27 +++
include/hw/
From: Shannon Zhao
The ACPI related header file acpi-defs.h, includes definitions that
apply on other architectures as well. Move it in `include/hw/acpi/`
to sanely include it from other architectures.
Signed-off-by: Alvise Rigo
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/
From: Shannon Zhao
Add aml_interrupt() for describing device interrupt in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/acpi/aml-build.c | 28 +
include/hw/acpi/aml-
From: Shannon Zhao
This patch series generate seven ACPI tables for machine virt on ARM.
The set of generated tables are:
- RSDP
- RSDT
- MADT
- GTDT
- FADT
- DSDT
- MCFG (For PCIe host bridge)
These tables are created dynamically using the function of aml-build.c,
taking into account the needed
From: Shannon Zhao
Add PCIe controller in ACPI DSDT table, so the guest can detect
the PCIe.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/virt-acpi-build.c | 152 +++
1 file changed, 152 insertions(+)
diff --git a/hw/arm/virt-
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/acpi/aml-build.c | 18 ++
include/hw/acpi/aml-build.h | 5 +
2 files changed, 23 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index
From: Shannon Zhao
In the case of mach virt, it is used to set the Hardware Reduced bit
and enable PSCI SMP booting through HVC. So ignore FACS and FADT
points to DSDT.
Update the header definitions for FADT taking into account the new
additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h`
Sig
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/acpi/aml-build.c | 9 +
include/hw/acpi/aml-build.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index cd4ffe2..139099
From: Shannon Zhao
MADT describes GIC enabled ARM platforms. The GICC and GICD
subtables are used to define the GIC regions.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/arm/virt-acpi-build.c | 61
in
From: Shannon Zhao
Expose the needed device information to the table generation
insfrastructure and register a machine_init_done notify to
call virt_acpi_build().
Add CONFIG_ACPI to arm-softmmu.mak.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
default-configs/arm-softmmu.mak
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/acpi/aml-build.c | 7 +++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 139099f..179acda 1
From: Shannon Zhao
Add aml_or() term and expose build_append_int_noprefix
as it wiil be used by creating a buffer.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/acpi/aml-build.c | 12 +++-
include/hw/acpi/aml-build.h | 2 ++
2 files changed, 13 insertions(+),
From: Shannon Zhao
Add ToUUID macro, this is useful for generating PCIe ACPI table.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/acpi/aml-build.c | 40
include/hw/acpi/aml-build.h | 1 +
2 files changed, 41 insertions(+)
dif
From: Shannon Zhao
Add PCIe info struct, prepare for building PCIe table.
And generate MCFG table.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/virt-acpi-build.c | 21 +
include/hw/arm/virt-acpi-build.h | 9 +
2 files changed, 30 inse
From: Shannon Zhao
RSDP points to RSDT which in turn points to other tables.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
Reviewed-by: Alex Bennée
---
hw/arm/virt-acpi-build.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/h
From: Shannon Zhao
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86.
Here we still use RSDT as UEFI puts ACPI tables below 4G address space,
and UEFI ignore the RSDT or XSDT.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/acpi/aml-build.c | 2
From: Shannon Zhao
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer
related information in the system. The Arch Timer interrupts must
be provided for GTDT.
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/virt-acpi-build.c| 30 +
On 08.04.2015 11:29, Alberto Garcia wrote:
Since this event can occur in nodes that cannot have a device name
associated, include also a field with the node name.
Signed-off-by: Alberto Garcia
---
block/qcow2.c | 8 ++--
docs/qmp/qmp-events.txt | 21 +
qap
On 15.04.2015 12:43, Stefan Hajnoczi wrote:
The 'block-stream' QMP command is documented in block-core.json but not
qmp-commands.hx. Add a summary of the command to qmp-commands.hx
(similar to the documentation for 'block-commit').
Reported-by: Kashyap Chamarthy
Signed-off-by: Stefan Hajnoczi
On 04/15/2015 04:43 AM, Stefan Hajnoczi wrote:
> The 'block-stream' QMP command is documented in block-core.json but not
> qmp-commands.hx. Add a summary of the command to qmp-commands.hx
> (similar to the documentation for 'block-commit').
>
> Reported-by: Kashyap Chamarthy
> Signed-off-by: Ste
On 04/15/2015 05:59 AM, Eduardo Habkost wrote:
> Currently it is impossible to set an option in a config file to an empty
> string, because the parser matches only lines containing non-empty
> strings between double-quotes.
>
> As sscanf() "[" conversion specifier only matches non-empty strings, a
Chen, Tiejun wrote
> +/* Here we just expose minimal host bridge offset subset. */
> +static const IGDHostInfo igd_host_bridge_infos[] = {
> +{0x08, 2}, /* revision id */
> +{0x2c, 2}, /* sybsystem vendor id */
> +{0x2e, 2}, /* sybsystem id */
> +{0x50, 2}, /* SNB: processor gra
On Thu, Apr 09, 2015 at 06:12:38PM +0200, Andreas Färber wrote:
> Hello,
Hi!
Sorry for the late response, I'm travelling and have a rather full
agenda.
> Testing QEMU v2.3.0-rc2, I have run into QEMU's glusterfs support being
> broken on openSUSE Tumbleweed, resulting in its configure complainin
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