As advised by Eric, I have enabled sharing of the function between of the
function that syncs the dirty bitmap obtained via kvm ioctl. I have tried
to make the least changes to the functions by concentrating only on the
function definitions.
Signed-off-by: Sanidhya Kashyap
---
arch_init.c
No particular functional change. Corrected some mistakes.
Signed-off-by: Sanidhya Kashyap
---
hmp-commands.hx | 15 +++
hmp.c| 12
hmp.h| 1 +
qapi-schema.json | 10 ++
qmp-commands.hx | 23 +++
savevm.c | 13
Introduced both runstates: RUN_STATE_MIGRATE and RUN_STATE_DUMP_BITMAP to
both migration and bitmap dump process.
I want the bitmap dump process to get canceled so whenever the state changes
from RUN_STATE_BITMAP to something else. But, this does not happen when I stop
the guest via stop qmp inter
> -Original Message-
> From: Gerd Hoffmann [mailto:kra...@redhat.com]
> Sent: Wednesday, June 04, 2014 2:12 PM
> To: Gonglei (Arei)
> Cc: qemu-devel@nongnu.org; Luonengjun; Huangweidong (C); Huangpeng
> (Peter)
> Subject: Re: [PATCH v2 0/9] usb: usb host adapter hotplug
>
> Hi,
>
> > ch
I have added two new flags - RUN_STATE_MIGRATE and RUN_STATE_DUMP_BITMAP.
These both flags behave same as RUN_STATE_RUNNING flag. The purpose of
introducing these flags is to avoid running both migration and dump bitmap
process simultaneously.
I haven't added many transitions to the RUN_STATE_DUMP
No particular functional change. This file does not need to be included in
the Makefile as it will be only useful once the user has generated the bitmap
file via bitmap dump process.
Signed-off-by: Sanidhya Kashyap
---
scripts/extract-bitmap.py | 64 ++
Following are the changes made with respect to the previous version:
Chen's advice
1) Replaced DIRTY_MEMORY_LOG_BITMAP with DIRTY_MEMORY_MIGRATION and
completely removed the DIRTY_MEMORY_LOG_BITMAP flag.
Eric's advice
2) Replaced FILE pointer with file descriptor.
3) Replaced fopen/fclose with qem
Hi,
The following patches introduce the support of dirty bitmap logging and dumping
to a specified file. Still, some work is still left in the area of runstates
that
I will try to work on after discussing this patch series.
v1 --> v2:
* Added two new run states to avoid simultaneous execution of
On Tue, Jun 03, 2014 at 11:58:21PM +0900, Hitoshi Mitake wrote:
> On Tue, Jun 3, 2014 at 9:41 PM, Liu Yuan wrote:
> > On Tue, Jun 03, 2014 at 01:54:21PM +0900, Hitoshi Mitake wrote:
> >> sheepdog driver should decide a write request is COW or not based on
> >> inode object which is active when the
> -Original Message-
> From: Gerd Hoffmann [mailto:kra...@redhat.com]
> Sent: Wednesday, June 04, 2014 2:10 PM
> To: Gonglei (Arei)
> Cc: qemu-devel@nongnu.org; Luonengjun; Huangweidong (C); Huangpeng
> (Peter)
> Subject: Re: [PATCH v2 7/9] usb-ehci: add ehci-pci device exit function
>
> O
Hi,
> changes since v1:
> * add more completely resource cleanup for every usb host adapter.
Looks good overall. How did you test this?
cheers,
Gerd
On Di, 2014-06-03 at 18:54 +0800, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> clean up ehci resource when ehci pci device exit.
>
> Signed-off-by: Gonglei
> ---
> hw/usb/hcd-ehci-pci.c | 33 +
> 1 file changed, 33 insertions(+)
>
> diff --git a/hw/usb/hc
On Wed, 4 Jun 2014 00:37:44 +0100
Peter Maydell wrote:
> On 29 April 2014 15:17, Natanael Copa wrote:
> > In addition to the previoiusly sent "linux-user: avoid using glibc
> > internals in _syscall5 and in definition of target_sigevent struct",
> > those are needed for making qemu build with mu
On 06/04/2014 09:42 AM, Alexey Kardashevskiy wrote:
> On 06/04/2014 03:10 AM, Tom Musta wrote:
>> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>>> This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
>>>
>>> This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
>>> it is accessed
On 06/04/2014 02:42 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> Compared to PowerISA-compliant CPUs, 970 family has most of them plus
>> PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
>>
>> Since we are changing SPRs for Book3s/970 families, le
On 06/04/2014 02:32 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> +static void gen_spr_book3s_pmu_user(CPUPPCState *env)
>> +{
>> +spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, S
On 06/04/2014 02:25 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> @@ -7303,8 +7304,21 @@ static void init_proc_970 (CPUPPCState *env)
>> SPR_NOACCESS, SPR_NOACCESS,
>> &spr_read_hior, &spr_write_hior,
>> 0x);
The function init_blk_migration is better to be called before
set_dirty_tracking as the reasons below.
If we want to track dirty blocks via dirty_maps on a BlockDriverState
when doing live block-migration, its correspoding 'BlkMigDevState' should be
added to block_mig_state.bmds_list first for su
On 06/04/2014 04:05 AM, Tom Musta wrote:
> On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote:
>> This adds DABRX SPR.
>>
>> As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
>> have them (as it implements more powerful facility instead), this limits
>> DABR/DABRX registration
On 06/04/2014 03:58 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This adds TM (Transactional Memory) SPRs.
>>
>> This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
>> handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
>> Since this
On Tue, Jun 03, 2014 at 11:22:51AM +0100, Alex Bennée wrote:
>
> Edgar E. Iglesias writes:
>
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-arm/cpu.h| 2 +-
> > target-arm/helper.c | 6 ++
> > 2 files changed, 7 insertions(+), 1 deletion(-)
>
On Mon, Jun 02, 2014 at 11:12:11AM -0500, Greg Bellows wrote:
> On 30 May 2014 22:49, Edgar E. Iglesias wrote:
>
> > On Fri, May 30, 2014 at 11:50:23AM -0500, Greg Bellows wrote:
> > > On 30 May 2014 02:28, Edgar E. Iglesias
> > wrote:
> > >
> > > > From: "Edgar E. Iglesias"
> > > >
> > > > Sig
On 06/04/2014 03:08 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This makes user-privileged read/write fail if TAR facility is not enabled
>> in FSCR.
>>
>> Since this is the very first check for enabled in FSCR facility,
>> this also adds gen_fscr_facility_check() for
Both 'indirect_desc' and 'event_idx' are bus independent features,
and they should be enabled for mmio devices too.
On arm64 quad core VM(qemu-kvm), the patch can increase block I/O
performance a lot with latest linux tree:
- without the patch: 14K IOPS
- with the patch: 34K IOPS
On 06/04/2014 02:59 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This adds TIR (Thread Identification Register) SPR first defined in
>> PowerISA 2.05.
>>
>> Signed-off-by: Alexey Kardashevskiy
>> ---
>> Changes:
>> v4:
>> * disabled reading it from user space
>> ---
>
On 06/04/2014 02:57 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This extends init_proc_book3s_64 to support POWER7 and POWER8.
>>
>> Signed-off-by: Alexey Kardashevskiy
>> ---
>> Changes:
>> v4:
>> * added g_assert_not_reached() to default path to catch errors earlie
On 06/04/2014 02:54 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers
>> will be called from generalized init_proc_book3s_64().
>>
>> Signed-off-by: Alexey Kardashevskiy
>> ---
>> target-ppc/translate_
> From: Paolo Bonzini
> Sent: Tuesday, June 03, 2014 4:40 AM
>
> Il 03/06/2014 13:29, Stefano Stabellini ha scritto:
> >> It's really not your fault, there's not much you can do given the hardware
> >> architecture. But I don't think this code can be accepted upstream, sorry.
> >
> > Yeah, the co
On 06/04/2014 02:47 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This enabled PMU SPRs migration by hooking hypv privileged versions with
>> "KVM one reg" IDs.
>>
>> Signed-off-by: Alexey Kardashevskiy
>> ---
>> target-ppc/translate_init.c | 104
>> +
Allow "make install" to handle tool binaries that reside in
sub-directories.
Without this patch "make install" will fail if it needs to strip
a tool binary (e.g. debugging is not enabled) that is installed
from a subdirectory. An example is fsdev/virtfs-proxy-helper.
Signed-off-by: Sam Bobroff
-
On 06/04/2014 02:35 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> Since we started adding "POWER" prefix to 64bit PMU SPRs, let's finish
>> the transition and fix MMCRA and define a hypv version of it.
>>
>> Signed-off-by: Alexey Kardashevskiy
>
> I'm still not a fan
On 04/06/14 04:04, DEnis wrote:
> 2014.06.03 Problem remains current
>
> -- =
>
> You received this bug notification because you are a member of qemu-
> devel-ml, which is subscribed to QEMU.
> https://bugs.launchpad.net/bugs/1319493
>
> Title:
> strip: '/usr/local/bin/fsdev/virtfs-proxy-help
Hi,
Since Linux kernel 3.5, KVM has set eax to KVM_CPUID_FEATURES, for
leaf 0x4000, see this:
https://github.com/torvalds/linux/commit/57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190
But qemu still tries to set it to 0. It would be better to make qemu
and kvm consistent. This patch just fixes this
Quoting Eric Blake (2014-06-03 17:06:22)
> On 06/03/2014 03:58 PM, Michael Roth wrote:
>
> >> Bikeshedding on the proposed name: given that 'fs' is an abbreviation of
> >> 'filesystem', "fsfreeze-freeze-filesystems" sounds rather redundant. I
> >> would suggest guest-fsfreeze-list as a shorter na
The SPE emulation code wants to access the highest 32bits of a 64bit register
and uses the andi TCG instruction for that. Unfortunately it masked with the
wrong mask. Fix the mask to actually cover the upper 32 bits.
This fixes simple multiplication tests with SPE guests for me.
Signed-off-by: Al
Trying to override the implementations of g_malloc and g_free is
a really bad idea -- it means statically linked builds fail to
link (because of the multiple definitions provided by this file
and by glib), and non-statically linked builds segfault as soon
as they try to do anything more complicated
On 06/04/2014 02:51 AM, Greg Kurz wrote:
> On Tue, 3 Jun 2014 19:28:04 +1000
> Alexey Kardashevskiy wrote:
>
>> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
>> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>>
>> This defines AIL flags for LPCR special register.
>>
>> This
On 06/04/2014 03:10 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
>>
>> This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
>> it is accessed via its user-privileged mirror. A spr_read_ureg() is
>> al
The function popcountl() in hbitmap.c is effectively a reimplementation
of what host-utils.h provides as ctpopl(). Use ctpopl() directly; this fixes
a failure to compile on NetBSD (whose strings.h erroneously exposes a
system popcountl() which clashes with this one).
Signed-off-by: Peter Maydell
On 29 April 2014 15:17, Natanael Copa wrote:
> In addition to the previoiusly sent "linux-user: avoid using glibc
> internals in _syscall5 and in definition of target_sigevent struct",
> those are needed for making qemu build with musl libc on Alpine Linux.
>
> There is still 2 missing fcntl.h def
On 6/3/14 18:10 , "Eric Blake" wrote:
>On 06/03/2014 04:06 PM, Eric Blake wrote:
>> On 06/03/2014 03:58 PM, Michael Roth wrote:
>>
Bikeshedding on the proposed name: given that 'fs' is an abbreviation
of
'filesystem', "fsfreeze-freeze-filesystems" sounds rather redundant.
I
>>>
When we run 32bit guest CPUs (or 32bit guest code on 64bit CPUs) on
qemu-system-ppc64 the TLB lookup will use the full effective address
as pointer.
However, only the first 32bits are valid when MSR.CM = 0. Check for
that condition.
This makes QEMU boot an e500v2 guest with more than 1G of RAM fo
On 06/03/2014 04:06 PM, Eric Blake wrote:
> On 06/03/2014 03:58 PM, Michael Roth wrote:
>
>>> Bikeshedding on the proposed name: given that 'fs' is an abbreviation of
>>> 'filesystem', "fsfreeze-freeze-filesystems" sounds rather redundant. I
>>> would suggest guest-fsfreeze-list as a shorter name
On 06/03/2014 03:58 PM, Michael Roth wrote:
>> Bikeshedding on the proposed name: given that 'fs' is an abbreviation of
>> 'filesystem', "fsfreeze-freeze-filesystems" sounds rather redundant. I
>> would suggest guest-fsfreeze-list as a shorter name that conveys the
>> intent, without quite as muc
Quoting Eric Blake (2014-06-03 16:38:35)
> On 06/03/2014 03:21 PM, Michael Roth wrote:
> > Quoting Tomoki Sekiyama (2014-05-22 08:56:53)
> >> When an array of mount point paths is specified as 'mountpoints' argument
> >> of guest-fsfreeze-freeze, qemu-ga with this patch will only freeze the file
>
On 06/03/2014 03:21 PM, Michael Roth wrote:
> Quoting Tomoki Sekiyama (2014-05-22 08:56:53)
>> When an array of mount point paths is specified as 'mountpoints' argument
>> of guest-fsfreeze-freeze, qemu-ga with this patch will only freeze the file
>> systems mounted on specified paths in Linux.
>>
Quoting Tomoki Sekiyama (2014-05-22 08:56:53)
> When an array of mount point paths is specified as 'mountpoints' argument
> of guest-fsfreeze-freeze, qemu-ga with this patch will only freeze the file
> systems mounted on specified paths in Linux.
> This would be useful when the host wants to create
On Tue, Jun 03, 2014 at 10:29:45AM +0100, Leon Alrae wrote:
> On 02/06/14 20:16, Aurelien Jarno wrote:
> >> -case OPC_DADDI:
> >> +case OPC_DADDI: /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
> >> +if (ctx->insn_flags & ISA_MIPS32R6) {
> >> +/* OPC_BNVC, OPC_BNEZALC, OPC_BNEC *
The iwmmxt_msadb helper and its corresponding gen function are unused;
delete them. (This function appears to have never been used right back
to the initial implementation of iwMMXt; it is identical to iwmmxt_madduq,
and is presumably an accidental remnant from the initial development.)
Signed-off
On 3 June 2014 19:29, Peter Maydell wrote:
> The VMStateDescription structs for the GPIO and PPC devices were
> accidentally never wired up. Add missing state fields and register
> them via dc->vmsd.
>
> Signed-off-by: Peter Maydell
This patch has missing '&' syndrome too. I must have
compiled t
On 3 June 2014 19:30, Peter Maydell wrote:
> The pxa2xx-gpio device has a VMStateDescription, but it was accidentally
> never actually registered, and it wasn't quite correct. Remove the
> 'lines' field (this is a device property, not mutable state), add
> the missing 'gpsr' and 'prev_level' field
The pxa2xx-gpio device has a VMStateDescription, but it was accidentally
never actually registered, and it wasn't quite correct. Remove the
'lines' field (this is a device property, not mutable state), add
the missing 'gpsr' and 'prev_level' fields, and set dc->vmsd so it
actually gets used.
Signe
The VMStateDescription structs for the GPIO and PPC devices were
accidentally never wired up. Add missing state fields and register
them via dc->vmsd.
Signed-off-by: Peter Maydell
---
hw/arm/strongarm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/arm/strongarm.c b/hw/arm/strongar
2014.06.03 Problem remains current
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1319493
Title:
strip: '/usr/local/bin/fsdev/virtfs-proxy-helper': No such file make:
*** [install] Error 1
Statu
On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote:
> This adds DABRX SPR.
>
> As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
> have them (as it implements more powerful facility instead), this limits
> DABR/DABRX registration by POWER7 (inclusive).
>
> Signed-off-by: Alex
On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote:
> POWER8 supports Event-Based Branch Facility (EBB). It is controlled via
> set of SPRs access to which should generate an "Facility Unavailable"
> interrupt if the facilities are not enabled in FSCR for problem state.
>
> This adds EBB SPRs.
>
> S
The sign_extend() function is unused; delete it.
Signed-off-by: Peter Maydell
---
We have sextract() for this these days anyway.
---
target-microblaze/translate.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds TM (Transactional Memory) SPRs.
>
> This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
> handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
> Since this is not the only register like that and their n
Il 31/05/2014 20:43, Max Reitz ha scritto:
@@ -108,7 +120,9 @@ bool aio_pending(AioContext *ctx)
int revents;
revents = node->pfd.revents & node->pfd.events;
-if (revents & (G_IO_IN | G_IO_HUP | G_IO_ERR) && node->io_read) {
+if (revents & (G_IO_IN | G_IO_HUP |
Make the mux always go through qemu_chr_fe_write, so that we'll get
the mutex for the underlying chardev.
Signed-off-by: Paolo Bonzini
---
qemu-char.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/qemu-char.c b/qemu-char.c
index 3df5db7..2bda2fb 100644
--- a/
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This extends init_proc_book3s_64 to support POWER7 and POWER8.
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> Changes:
> v4:
> * added g_assert_not_reached() to default path to catch errors earlier
> ---
> target-ppc/translate_init.c | 100
> +
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This replaces VRSAVE registration and vscr_init() call with
> gen_spr_book3s_altivec() which is generic and does the same thing if
> insns_flags has PPC_ALTIVEC bit set (which POWER7/8 have set).
>
> Signed-off-by: Alexey Kardashevskiy
> ---
>
>
On 3 June 2014 17:15, Michal Privoznik wrote:
> With the latest gcc-4.9.0 I'm getting some compile errors:
>
> In file included from qemu.git/linux-user/syscall.c:113:0:
> qemu.git/linux-user/syscall.c: In function ‘copy_from_user_fdset’:
> qemu.git/linux-user/qemu.h:309:13: error: right-hand oper
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers
> will be called from generalized init_proc_book3s_64().
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> target-ppc/translate_init.c | 70
> ++---
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This makes use of generic gen_spr_book3s_lpar() which registers LPCR SPR.
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> target-ppc/translate_init.c | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target-ppc/trans
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This replaces gen_spr_7xx() call (which registers 32bit SPRs) with
> gen_spr_book3s_pmu() call.
>
> This removes SPR_7XX_PMC5/6 as they are for 32bit and gen_spr_book3s_pmu()
> already registers correct PMC5/6 SPRs.
>
> This removes explicit MMCR
On Tue, 3 Jun 2014 19:28:04 +1000
Alexey Kardashevskiy wrote:
> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>
> This defines AIL flags for LPCR special register.
>
> This changes @excp_prefix according to the mode, takes e
Drop the sd_acmd_type[] array: it is never used. (The equivalent
sd_cmd_type[] array for normal commands is used to identify
those commands whose argument includes the card address in the
top 16 bits; but for app commands the card address is passed
with the APP_CMD prefix, not with the argument to
* Peter Lieven (p...@kamp.de) wrote:
> if a saved vm has unknown flags in the memory data qemu
> currently simply ignores this flag and continues which
> yields in an unpredictable result.
>
> this patch catches all unknown flags and
> aborts the loading of the vm.
Yes, I think that's quite nice
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds TIR (Thread Identification Register) SPR first defined in
> PowerISA 2.05.
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> Changes:
> v4:
> * disabled reading it from user space
> ---
> target-ppc/cpu.h| 1 +
> target-ppc/t
On 29.05.2014 13:04, Peter Maydell wrote:
> No, we don't in general have any benchmarking of TCG
> codegen. I think if we did do benchmarking we'd be interested
> in performance benchmarking -- code expansion ratio doesn't
> seem like a very interesting thing to measure to me.
Hi,
I have a plan t
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
>
> This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
> it is accessed via its user-privileged mirror. A spr_read_ureg() is
> already there. Since the new helper is only used
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This makes user-privileged read/write fail if TAR facility is not enabled
> in FSCR.
>
> Since this is the very first check for enabled in FSCR facility,
> this also adds gen_fscr_facility_check() for using in spr_write_tar()/
> spr_read_tar().
>
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This moves TAR SPR to a helper. Later this helper will be
> called from generalized init_proc_book3s_64().
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> target-ppc/translate_init.c | 14 +-
> 1 file changed, 9 insertions(+), 5 dele
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This enabled PMU SPRs migration by hooking hypv privileged versions with
> "KVM one reg" IDs.
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> target-ppc/translate_init.c | 104
> ++--
> 1 file changed, 52
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This moves PIR/PURR/SPURR SPRs to helpers. Later these helpers will be
> called from generalized init_proc_book3s_64().
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> target-ppc/translate_init.c | 40 ++--
>
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> After merging 970s into one class, check_pow_970() is used for all of them.
> Since POWER5+ is no different in the matter of supported power modes,
> let's use the same check_pow() callback for POWER5+ too,
>
> Signed-off-by: Alexey Kardashevskiy
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> At the moment every POWER CPU family has its own init_proc_POWERX function.
> E500 already has common init function so we try to do the same thing.
>
> This introduces BOOK3S_CPU_TYPE enum with 2 values - 970 and POWER5+.
>
> This introduces gene
Event emission must be protected by a mutex because of access to
the shared rate-limiting state, and to guard against concurrent
monitor "hot-plug" by means of human-monitor-command.
Signed-off-by: Paolo Bonzini
---
monitor.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletio
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> Compared to PowerISA-compliant CPUs, 970 family has most of them plus
> PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
>
> Since we are changing SPRs for Book3s/970 families, let's add them too.
>
> Signed-off-by: Alexey K
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> Previously LPCR was registered for the 970 class which was wrong as
> it does not have LPCR. Instead, HID4 is used which this patch registers.
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> target-ppc/cpu.h| 1 +
> target-ppc/trans
This will let threads other than the I/O thread raise QMP events.
GIOChannel is thread-safe, and send and receive state is usually
well-separated. The only driver that requires some care is the
pty driver, where some of the state is shared by the read and write
sides. That state is protected wit
Signed-off-by: Paolo Bonzini
---
qemu-char.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/qemu-char.c b/qemu-char.c
index 2bda2fb..b478a3d 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -1055,6 +1055,22 @@ static void pty_chr_rearm_timer(Ch
Even though virtio-blk-dataplane mostly synchronizes with the block layer
by means of the AioContext, we still need to introduce mutexes for other
QEMU subsystems that the dataplane thread might encounter on its way.
Adding rerror/werror support, for example, means that the dataplane
thread will ha
This lets the block layer emit QMP events from outside the I/O thread.
Signed-off-by: Paolo Bonzini
---
monitor.c | 35 ---
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/monitor.c b/monitor.c
index 342e83b..ebc66fb 100644
--- a/monitor.c
+++ b/mon
The next patch will modify this function to initialize state that is
common to all backends.
Signed-off-by: Paolo Bonzini
---
backends/baum.c | 2 +-
backends/msmouse.c| 2 +-
include/sysemu/char.h | 9 +
qemu-char.c | 32 +++-
spice-qem
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> Compared to PowerISA-compliant CPUs, 970 family has most of them plus
> PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
>
> Since we are changing SPRs for Book3s/970 families, let's add them too.
>
> Signed-off-by: Alexey K
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> MMCR0, MMCR1, MMCRA, PMC1..6, SIAR, SDAR are defined for 970 and PowerISA
> CPUs. Since we are building common infrastructure for SPRs intialization
> to share it between 970 and POWER5+/7/..., let's add missing SPRs to
> the 970 family. Later rewo
Ensure proper env->tsc value for kvmclock_current_nsec calculation.
Reported-by: Marcin Gibuła
Signed-off-by: Marcelo Tosatti
diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c
index 6f4ed28a..bef2504 100644
--- a/hw/i386/kvm/clock.c
+++ b/hw/i386/kvm/clock.c
@@ -17,6 +17,7 @@
#include "q
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> Since we started adding "POWER" prefix to 64bit PMU SPRs, let's finish
> the transition and fix MMCRA and define a hypv version of it.
>
> Signed-off-by: Alexey Kardashevskiy
I'm still not a fan of "SPR_POWER_*" since these are now in the ISA (t
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> As defined in Linux kernel, PMC*, SIAR, MMCR0/1 have different numbers
> for 32 and 64 bit POWERPC. We are going to support 64bit versions too so
> let's rename 32bit ones to avoid confusion.
>
> This is a mechanical patch so it does not fix obvio
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> +static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> +{
> +spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x);
>
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> @@ -7303,8 +7304,21 @@ static void init_proc_970 (CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_hior, &spr_write_hior,
> 0x);
> +
> +spr_register(env, SPR_CTRL, "SPR_CT
With the latest gcc-4.9.0 I'm getting some compile errors:
In file included from qemu.git/linux-user/syscall.c:113:0:
qemu.git/linux-user/syscall.c: In function ‘copy_from_user_fdset’:
qemu.git/linux-user/qemu.h:309:13: error: right-hand operand of comma
expression has no effect [-Werror=unused-v
On 06/02/2014 04:10 PM, Tom Musta wrote:
On 6/2/2014 7:27 AM, Alexander Graf wrote:
You can either send just a new patch 3/6 and I replace the one in my queue or a
patch on top.
From: Doug Kwan
Date: Thu, 15 May 2014 15:54:55 -0500
Subject: [V4 PATCH (resend) 3/6] target-ppc: Add a new user m
On Tue, 3 Jun 2014 19:27:37 +1000
Alexey Kardashevskiy wrote:
> The differences between classes were:
> 1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
> 2. check_pow() callback, HID0 format is the same so should be the same
> 0x01C0 which means "deep nap", "doze" and "n
On 2 June 2014 17:21, Alex Bennée wrote:
> This is a pre-cursor to removing the cpsr_write function.
>
> diff --git a/linux-user/arm/nwfpe/fpa11.h b/linux-user/arm/nwfpe/fpa11.h
> index bb9ac65..0dbdf75 100644
> --- a/linux-user/arm/nwfpe/fpa11.h
> +++ b/linux-user/arm/nwfpe/fpa11.h
> @@ -108,7 +1
On 06/03/2014 05:40 PM, Greg Kurz wrote:
On Tue, 3 Jun 2014 19:27:37 +1000
Alexey Kardashevskiy wrote:
The differences between classes were:
1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
2. check_pow() callback, HID0 format is the same so should be the same
0x01C0 w
Il 03/06/2014 16:37, Kevin Wolf ha scritto:
> Am 03.06.2014 um 16:16 hat Paolo Bonzini geschrieben:
>> With virtio-blk dataplane, I/O errors might occur while QEMU is
>> not in the main I/O thread. However, it's invalid to call vm_stop
>> when we're neither in a VCPU thread nor in the main I/O thr
The Tuesday 03 Jun 2014 à 08:55:24 (-0600), Eric Blake wrote :
> On 05/31/2014 05:51 AM, Benoît Canet wrote:
> > Signed-off-by: Benoit Canet
> > ---
> > qapi-schema.json | 33 -
> > qapi/block-core.json | 33 +
> > 2 files change
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