On 06/04/2014 02:42 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> Compared to PowerISA-compliant CPUs, 970 family has most of them plus
>> PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
>>
>> Since we are changing SPRs for Book3s/970 families, let's add them too.
>>
>> Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru>
>> ---
>> target-ppc/cpu.h | 4 ++++
>> target-ppc/translate_init.c | 26 ++++++++++++++++++++++++++
>> 2 files changed, 30 insertions(+)
>>
>
> [ ... ]
>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index e4c9a4c..0fcf918 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7442,6 +7442,30 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
>> 0x00000000);
>> }
>>
>> +static void gen_spr_970_pmu_hypv(CPUPPCState *env)
>> +{
>> + spr_register(env, SPR_970_PMC7, "PMC7",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + 0x00000000);
>> + spr_register(env, SPR_970_PMC8, "PMC8",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + 0x00000000);
>> +}
>> +
>
> Sorry ... forgot my comments: Shouldn't this be named "gen_spr_970_pm_sup" ?
> These are supervisor SPRs, not hypervisor SPRs.
Will be fixed in v5.
>> +static void gen_spr_970_pmu_user(CPUPPCState *env)
>> +{
>> + spr_register(env, SPR_970_UPMC7, "UPMC7",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_970_UPMC8, "UPMC8",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> +}
>> +
>
> Are UPMC7/8 writeable from supervisor state? (the 970 UM is not crystal
> clear here).
No idea either. I suggest enabling writes there and get back to the topic
when/if we decide to model them correctly. Ok?
--
Alexey
