On 17 March 2014 22:17, Andreas Färber wrote:
> Am 17.03.2014 12:55, schrieb riku.voi...@linaro.org:
> > From: Riku Voipio
> >
> > some people get numerous unimplemented capget/capset warnings. Since qemu
> > linux-user is not secure to begin with, just skip the system call
> > warning for now.
Signed-off-by: Maria Kustova
---
Changes v1 -> v2:
* Removed trailing "\n" from the error string
---
block/curl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/curl.c b/block/curl.c
index 3494c6d..359637e 100644
--- a/block/curl.c
+++ b/block/curl.c
@@ -538,8 +538,7 @
Signed-off-by: Maria Kustova
---
qemu-io-cmds.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-io-cmds.c b/qemu-io-cmds.c
index f1de24c..5707bda 100644
--- a/qemu-io-cmds.c
+++ b/qemu-io-cmds.c
@@ -1087,7 +1087,7 @@ writev_help(void)
" writes a range of bytes from the g
It's not clear from the usage description that "--cmd" option accepts its
argument as a string, so any special symbols have to be quoted from the shell.
Updates in usage text:
- Specified parameter format for "--cmd" option.
- Added an instruction how to get help for "--cmd" option.
Signed-off-
These patches are the part of OPW application.
Two of them update help messages of qemu-io utility.
And last one replaces fprintf() with error_setg() in curl.c
Changes v1 -> v2:
* Removed trailing "\n" from the error string in error_setg() call
Maria Kustova (3):
qemu-io-cmds: Fixed typo in ex
Thanks, that is an excellent blog!
2014-03-18 12:04 GMT+08:00 Kashyap Chamarthy :
> On Tue, Mar 18, 2014 at 07:56:16AM +0800, Le Tan wrote:
>> Hi, I am diving into the source code of qemu. I see the word
>> "coroutine" appears in so many places. I can't figure out what it
>> means. So, please, can
2014-03-12 20:40 GMT+08:00 Eric Blake :
> On 03/11/2014 09:10 PM, Chunyan Liu wrote:
>
>
> >>> Could be if changing qemu_opt_get return value type, but just as said
> >>> before,
> >>> that will affect many codes.
> >>
> >> Also, changing an existing function that returns 'const char *' into
On Tue, Mar 18, 2014 at 10:31 AM, Chen Gang wrote:
> Clean up useless 'break' statement after 'return' statement.
>
> Signed-off-by: Chen Gang
Reviewed-by: Peter Crosthwaite
> ---
> target-arm/gdbstub64.c |2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/target-arm/gdbstub64.c b/ta
On Tue, Mar 18, 2014 at 07:56:16AM +0800, Le Tan wrote:
> Hi, I am diving into the source code of qemu. I see the word
> "coroutine" appears in so many places. I can't figure out what it
> means. So, please, can anyone help me, telling me the mechanism or
> semantic of "coroutine"? Thanks!
This mi
2014-03-18 3:35 GMT+08:00 Leandro Dorileo :
> Hi,
>
> On Mon, Mar 10, 2014 at 03:31:41PM +0800, Chunyan Liu wrote:
> > Add some qemu_opt functions to replace the same functionality of
> > QEMUOptionParameter handling.
> >
> > Signed-off-by: Dong Xu Wang
> > Signed-off-by: Chunyan Liu
> > ---
> >
If you start a Linux guest with more than 4GB of memory and try to look at a
memory address, you will get an error from gdb:
(gdb) p node_data[0]->node_id
Cannot access memory at address 0x88013fffd3a0
(gdb)
I debugged this down to x86_cpu_get_phys_page_debug(), it doesn't handle the
case whe
The new functionality of common.qemu implements the QEMU control
and communication functionality that was originally in test 085.
This removes that now-duplicate functionality, and uses the
common.qemu functions.
Signed-off-by: Jeff Cody
---
tests/qemu-iotests/085 | 73 +
The _rm_test_img() function in common.rc did not quote the image
file, which left droppings in the scratch directory (and performed
a potentially unsafe rm -f).
This adds the necessary quotes.
Signed-off-by: Jeff Cody
---
tests/qemu-iotests/common.rc | 4 ++--
1 file changed, 2 insertions(+), 2
Both tests 019 and 086 need proper quotations to work with pathnames
that contain spaces.
Signed-off-by: Jeff Cody
---
tests/qemu-iotests/019 | 2 +-
tests/qemu-iotests/086 | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/qemu-iotests/019 b/tests/qemu-iotests/01
This adds some common functionality to control QEMU for qemu-iotests.
Additionally, test 085 is updated to use this new functionality.
Some minor fixups along the way, to clear up spaced pathname issues,
for common.rc, test 019, and test 086.
Jeff Cody (4):
block: qemu-iotests - add common.q
This creates some common functions for bash language qemu-iotests
to control, and communicate with, a running QEMU process.
4 functions are introduced:
1. _launch_qemu()
This launches the QEMU process(es), and sets up the file
descriptors and fifos for communication. You can
On 03/18/2014 08:39 AM, Peter Maydell wrote:
> On 18 March 2014 00:31, Chen Gang wrote:
>> Clean up useless 'break' statement after 'return' statement.
>>
>> Signed-off-by: Chen Gang
>
> Reviewed-by: Peter Maydell
>
> thanks
> -- PMM
>
Thank you too.
--
Chen Gang
Open, share, and attitude
Hi qemu-devel,
I am a member of a development team based out of the Johns Hopkins University
Applied Physics Laboratory. Over the past year and a half, we've been working
with the OpenStack community on several security features for their Compute and
Block Storage services that leverage encrypt
On 18 March 2014 00:31, Chen Gang wrote:
> Clean up useless 'break' statement after 'return' statement.
>
> Signed-off-by: Chen Gang
Reviewed-by: Peter Maydell
thanks
-- PMM
Clean up useless 'break' statement after 'return' statement.
Signed-off-by: Chen Gang
---
target-arm/gdbstub64.c |2 --
1 file changed, 2 deletions(-)
diff --git a/target-arm/gdbstub64.c b/target-arm/gdbstub64.c
index e8a8295..8f3b8d1 100644
--- a/target-arm/gdbstub64.c
+++ b/target-arm/gdb
On 12/03/14 21:26, Olivier Danet wrote:
Hi Olivier,
Here is a patch for handling this corner case on SPARC32.
SPARC64 division already checks this in helper_sdivx(), some other
architectures
seem to do the same (for example, target-arm/helper.c: HELPER(sdiv))
==
On Mon, Feb 10, 2014 at 6:32 PM, Peter Maydell wrote:
> On 10 February 2014 23:02, Rob Herring wrote:
>> From: Rob Herring
>>
>> Non-PCI AHCI support is broken due to assertion failures when trying
>> to convert AHCIState to a PCIDevice pointer as AHCIState can have
>> different container struct
Implement the SADDLP, UADDLP, SADALP and UADALP instructions
in the SIMD 2-reg misc category.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-8-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper-a64.c| 61 ++
Signed-off-by: Hervé Poussineau
---
hw/pci-host/prep.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 8d0794e..fed6c26 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -223,12 +223,12 @@ static void raven_pci
This is something clang's -fsanitize=undefined spotted. The
code generated by qapi-commands.py in qmp-marshal.c for
qmp_marshal_* functions where there are some optional
arguments looks like this:
bool has_force = false;
bool force;
mi = qmp_input_visitor_new_strict(QOBJECT(args));
From: Alex Bennée
These are fairly simple exponent only estimation functions using helpers.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-14-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper-a64.c| 59 +
Hi, I am diving into the source code of qemu. I see the word
"coroutine" appears in so many places. I can't figure out what it
means. So, please, can anyone help me, telling me the mechanism or
semantic of "coroutine"? Thanks!
--Le Tan
Add the binfmt-misc magic needed to register QEMU for handling AArch64
ELF binaries.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-26-git-send-email-peter.mayd...@linaro.org
---
scripts/qemu-binfmt-conf.sh | 3 +++
1 file changed, 3 insertions(+)
diff
Implement the SHLL and SHLL2 instructions from the 2-reg-misc
category.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-9-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c | 32 +++-
1 file changed, 31 ins
Contrary to the comment describing this function's behavior, it does not
return 0 on success, but rather the offset of the newly allocated
cluster. This patch adjusts the comment accordingly to reflect the
actual behavior.
Signed-off-by: Max Reitz
---
block/qcow2-refcount.c | 2 +-
1 file change
From: Alex Bennée
I need these available outside of softfloat for some of the reciprocal
processing in aarch64 helper functions.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-20-git-send-email-peter.mayd...@linaro.org
---
af0f691db1e7ed1:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-3' into staging
(2014-03-17 15:51:57 +)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140317
for y
From: Alex Bennée
Implement the CLS, CLZ operations in the 2-reg-misc category.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-6-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper-a64.c| 5 +
target-arm/
If the CPU is a Cortex-A9 then we should set its reset-cbar property
so that the guest can read the correct PERIPHBASE/CBAR register value;
newer versions of the Linux kernel (as of commit bc41b8724 in 3.12)
will otherwise assume the CPU is a buggy single core A9 SoC. The
realview-pbx-a9 is the onl
From: Alex Bennée
rn == 31 always means SP (not XZR) whether an add_sub_ext
instruction is setting the flags or not; only rd has behaviour
dependent on whether we are setting flags.
Reported-by: Laurent Desnogues
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hen
Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-13-git-send-email-peter.mayd...@linaro.org
---
t
Cover basic aspects and API usage for QemuOpt. The current implementation
covers the API's planned to be changed by Chunyan Liu in his QEMUOptionParameter
replacement/cleanup job.
Other APIs should be covered in future improvements.
Signed-off-by: Leandro Dorileo
Changes:
v2:
+ fixed com
On Tue, Mar 18, 2014 at 5:29 AM, Don Slutz wrote:
> On 03/16/14 22:21, Peter Crosthwaite wrote:
>>
>> On Thu, Feb 27, 2014 at 12:48 PM, Don Slutz wrote:
>>>
>>> The commit 88c1ee73d3231c74ff90bcfc084a7589670ec244
>>> char/serial: Fix emptyness check
>>>
>>> Still causes extra NULL byte(s) to be s
On Thu, Feb 20, 2014 at 4:30 AM, Don Slutz wrote:
> The commit 88c1ee73d3231c74ff90bcfc084a7589670ec244
> char/serial: Fix emptyness check
>
> Still causes extra NULL byte(s) to be sent.
>
> So if the fifo is empty, do not send an extra NULL byte.
>
> Signed-off-by: Don Slutz
> ---
> hw/char/ser
Since 1.7, the default framebuffer settings for PowerPC are 800x600x32.
Signed-off-by: Mark Cave-Ayland
CC: qemu-...@nongnu.org
---
qemu-doc.texi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 6d684e2..e6e20eb 100644
--- a/qemu-doc.texi
On Thu, Feb 20, 2014 at 4:30 AM, Don Slutz wrote:
> The commit 88c1ee73d3231c74ff90bcfc084a7589670ec244
> char/serial: Fix emptyness check
>
> Still causes extra NULL byte(s) to be sent.
>
> So if the fifo is empty, do not send an extra NULL byte.
>
> Signed-off-by: Don Slutz
Reviewed-by: Peter
On Mon, Mar 17, 2014 at 07:35:43PM +, Peter Maydell wrote:
> [another resend for qemu-devel...]
>
> On 27 February 2014 07:16, Pranavkumar Sawargaonkar
> wrote:
> > On 27 February 2014 12:21, Pranavkumar Sawargaonkar
> > wrote:
> >> Latest linux kernel supports in-kernel emulation of PSCI v0
ble in the git repository at:
>
>
> git://github.com/borntraeger/qemu.git tags/kvm-s390-20140317
>
> for you to fetch changes up to 4f3ed190a673c0020c3ccebb4882ae4675cb5f4d:
>
> s390x/sclpconsole-lm: Fix and simplify irq setup (2014-03-17 22:01:19 +0100)
>
Applied, thanks.
-- PMM
Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD
2-reg-misc category.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-11-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c | 24 +++-
1 file changed, 2
From: Alex Bennée
This completes the set of integer narrowing saturating ops including:
SQXTN, SQXTN2
SQXTUN, SQXTUN2
UQXTN, UQXTN2
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-23-git-send-email-peter.mayd..
On 17 March 2014 18:20, Richard Henderson wrote:
> Following the patch series posting from 2 weeks ago. The set
> contains a couple of real bug fixes, not merely improvments,
> so it'd be nice to have this in 2.0.
>
>
> r~
>
>
> The following changes since commit 87f639629334c4592c3ba1011af0f691d
On 17/03/14 21:55, Artyom Tarasenko wrote:
Hi Andreas,
On Mon, Mar 17, 2014 at 8:59 PM, Andreas Färber wrote:
this patch seems still be missing in master. Is it causing any problems?
It does not apply without the preceding patches. Here's my cherry-pick
result:
[...]
I.e. we might change 1
On Sun, Mar 16, 2014 at 11:44 AM, Peter Maydell
wrote:
> On 16 March 2014 15:57, Peter Maydell wrote:
>> On 14 March 2014 18:22, Rob Herring wrote:
>>> From: Rob Herring
>>>
>>> When setting the fifo trigger level, the rx interrupt needs to be asserted
>>> if the current fifo level matches. Thi
From: Alex Bennée
Implement FSQRT in the two-reg-misc category.
GCC uses this instruction form.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-5-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c | 13 ++
Implement the floating-point-to-integer conversion instructions
FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc
categories.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-10-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c
Hi,
Le lun. 17 mars 2014 22:55:37 CET, Artyom Tarasenko a écrit :
[...]
BTW another unresolved issue that's been discussed is whether we should
change the default CPU for -M prep. I've been open to doing so for 2.0
but would like some pointer that such a machine did exist
That's fair. I don't h
On 03/17/14 23:04, Max Reitz wrote:
> Contrary to the comment describing this function's behavior, it does not
> return 0 on success, but rather the offset of the newly allocated
> cluster. This patch adjusts the comment accordingly to reflect the
> actual behavior.
>
> Signed-off-by: Max Reitz
>
Implement the saturating left shift instructions SQSHL, SQSHLU
and UQSHL for the scalar-shift-imm and shift-imm categories.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-18-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c | 132 ++
On Mon, 17 Mar 2014, Andreas Färber wrote:
In earlier times QEMU did not properly support multiple PCI bus domains.
Some code in
http://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci-host/uninorth.c;h=e72fe2a70b954bf5675ad0c8735fea6bad665be6;hb=HEAD
is #if 0'ed out that you should take a look at.
I'v
Implement SRI (shift right and insert).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-15-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c | 57 +++---
1 file changed, 49 insertions(+), 8 del
Set the reset-cbar property of the Exynos4210 SoC's Cortex-A9
CPUs, so that Linux doesn't misrecognize them as a broken
uniprocessor SoC.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
Message-id: 1394462692-8871-4-git-send-email-peter.mayd...@linaro.org
---
hw/arm/exynos4210.c | 1
Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm
categories; this completes the implementation of those two groups.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-19-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c
Now that the PMCR writefn makes timer accesses, its reginfo needs
the ARM_CP_IO flag, so that icount mode works correctly. (Fixes
the bug accidentally introduced in commit 7c2cb42b).
Reported-by: Laurent Desnogues
Signed-off-by: Peter Maydell
Message-id: 1394908291-16546-1-git-send-email-peter.m
Implement FCVTL, the only instruction in the 2-reg-misc group
which widens from size to 2*size elements.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-12-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c | 47 ++
Implement the PMULL instruction; this is the last unimplemented insn
in the three-reg-diff group.
Note that PMULL with size 3 is considered part of the AES part
of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
in the v8 ARM ARM), so it isn't necessary to burn an extra feature
The ARM A64 decoder's worst case number of TCG ops per instruction
is 266 (for insn 0x4c80, a post-indexed ST4 multiple-structures
store). Raise the MAX_OP_PER_INSTR define accordingly.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-17-git-send-email
On 03/17/14 23:04, Max Reitz wrote:
> If qcow2_alloc_clusters() fails, new_offset and ret will both be
> negative after the fail label, thus passing the first if condition and
> subsequently resulting in a call of qcow2_free_clusters() with an
> invalid (negative) offset parameter. Fix this by intr
From: Alex Bennée
Move the handle_2misc_narrow() function up the file so that it can
be called from disas_simd_scalar_two_reg_misc().
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-22-git-send-email-peter.mayd...@linaro.org
Set the reset-cbar property on CPUs used by the virt board,
if they have it. This isn't necessary for correct functioning
under Linux (since the A9 isn't a valid CPU for the virt board),
but it is the correct behaviour.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
Message-id: 1394
Implement the FCVTXN operation, which does a narrowing fp precision
conversion using the "round to odd" (von Neumann) mode. This can
conveniently be implemented as "do operation using round to zero;
then set the LSB of the mantissa to 1 if the Inexact flag was set".
Signed-off-by: Peter Maydell
R
From: Alex Bennée
Implement URECPE and FRECPE instructions in both scalar and vector forms.
The actual reciprocal estimate function is shared with the A32/T32 Neon
code. However in A64 we aren't using the Neon "standard FPSCR value"
so extra checks are necessary to handle non-squashed denormal in
Newer versions of the Linux kernel (as of commit bc41b8724 in 3.12)
now assume that if the CPU is a Cortex-A9 and the reset value of the
PERIPHBASE/CBAR register is zero then the CPU is a specific buggy
single core A9 SoC, and will not try to start other cores. Since we
now have a CPU property for
Implement the FRINT* round-to-integral operations from
the 2-reg-misc category.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 1394822294-14837-16-git-send-email-peter.mayd...@linaro.org
---
target-arm/translate-a64.c | 45 ++---
From: Alex Bennée
This adds the remaining [US]CVTF operations to the SIMD
shift-immediate, scalar-shift-immediate, two-reg-misc and
scalar-two-reg-misc groups of opcodes.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
Message-id: 1394822294-14837-4-git-
From: Alex Bennée
This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are
saturating and narrowing shift right operations. These are used in
things like libav. Note signed shifts can have an "unsigned" saturating
narrow operation which will floor negative values.
Signed-off-by: A
From: Alex Bennée
This adds support for [UF]RSQRTE instructions. It utilises the existing
NEON helpers with some changes. The changes include an explicit passing
of fpstatus (so the correct one is used between arm32 and aarch64),
denormilzation, more correct error handling and also proper scaling
On 17/03/14 19:11, Cornelia Huck wrote:
> Allow KVM_ENABLE_CAP to act on a vm as well as on a vcpu. This makes more
> sense when the caller wants to enable a vm-related capability.
>
> s390 will be the first user; wire it up.
>
> Reviewed-by: Thomas Huth
> Signed-off-by: Cornelia Huck
Reviewed-
If qcow2_alloc_clusters() fails, new_offset and ret will both be
negative after the fail label, thus passing the first if condition and
subsequently resulting in a call of qcow2_free_clusters() with an
invalid (negative) offset parameter. Fix this by introducing a new label
"fail_free_cluster" whic
This series fixes the fail path of the static function
realloc_refcount_block() in block/qcow2-refcount.c which is used for
repairing corrupted image files. While doing so, the whole return path
is cleaned up and the comment describing the return value in case of
success is fixed.
Max Reitz (2):
PCI memory region is 0x3f00 bytes starting at 0xc000.
However, keep compatibility with Open Hack'Ware expectations
by adding a hack for Open Hack'Ware display.
Signed-off-by: Hervé Poussineau
---
hw/pci-host/prep.c |9 ++---
hw/ppc/prep.c |9 +
2 files changed,
PCI I/O region is 0x3f80 bytes starting at 0x8000.
Do not use global QEMU I/O region, which is only 64KB.
Signed-off-by: Hervé Poussineau
---
hw/pci-host/prep.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/pre
Signed-off-by: Hervé Poussineau
---
hw/pci-host/prep.c | 40 +---
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index fed6c26..373af48 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -70,7
Regions added in next patches will also have the pci_ prefix.
Signed-off-by: Hervé Poussineau
---
hw/pci-host/prep.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 94fdffa..84d50ca 100644
--- a/hw/pci-host/prep.c
+++ b/
This has been tested on Linux 2.4/PPC with the lsi53c895a SCSI adapter.
Signed-off-by: Hervé Poussineau
---
hw/pci-host/prep.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 45615bd..8d0794e 100644
--- a/hw/pci-host/pr
Remove now duplicated code from prep board.
Signed-off-by: Hervé Poussineau
---
hw/pci-host/prep.c | 84 ++
hw/ppc/prep.c | 94 ++--
2 files changed, 87 insertions(+), 91 deletions(-)
diff --git
This patchset improves Raven PCI host emulation, found in some PPC platforms,
like the QEMU 'prep' one, and for example the IBM RS/6000 40p.
Some features added to raven emulation were already present in prep board
(non contiguous I/O, firmware loading), while some other are new (PCI bus
mastering
On 17/03/14 22:25, Peter Maydell wrote:
> On 17 March 2014 20:56, Christian Borntraeger wrote:
>> Turns out that valgrind is right. We simply forget the memory that
>> g_strconcat has allocated.
>> This fixes the small leak, but I have to cast away the constness of .name.
>> Any better ideas?
>
Hi Mark,
thank you for taking some time!
a)
Yes, the color issue is exactly the same for qemu 1.6.0 with darwinppc-602.cdr
from https://opensource.apple.com/static/iso/
command used:
qemu-system-ppc -snapshot -L -hda /Users/joe/darwinppc-602.cdr -g
1280x1024x32
I have tried some additional
On Mon, 2014-03-17 at 22:53 +0100, Christian Borntraeger wrote:
> since commit 261747f176f6 (vl: Use MachineClass instead of global
> QEMUMachine list) valgrind complains about the following:
>
> ==54082== 57 bytes in 3 blocks are definitely lost in loss record 365 of 729
> ==54082==at 0x4031A
A few minor tidy-ups, plus add reference to the new -vga tcx and cg3 options.
Signed-off-by: Mark Cave-Ayland
---
qemu-doc.texi |9 +
qemu-options.hx | 10 +-
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index ad31f2d..6d68
On 17/03/14 19:11, Cornelia Huck wrote:
> When registering a new irqfd, we call its ->poll method to collect any
> event that might have previously been pending so that we can trigger it.
> This is done under the kvm->irqfds.lock, which means the eventfd's ctx
> lock is taken under it.
>
> However
Hi Andreas,
On Mon, Mar 17, 2014 at 8:59 PM, Andreas Färber wrote:
>> this patch seems still be missing in master. Is it causing any problems?
>
> It does not apply without the preceding patches. Here's my cherry-pick
> result:
>[...]
> I.e. we might change 1 -> 4 in the SysBus API, but would tha
since commit 261747f176f6 (vl: Use MachineClass instead of global
QEMUMachine list) valgrind complains about the following:
==54082== 57 bytes in 3 blocks are definitely lost in loss record 365 of 729
==54082==at 0x4031AFE: malloc (vg_replace_malloc.c:292)
==54082==by 0x4145569: g_malloc (
Hi all,
Here are a couple of minor documentation updates - the first is for sun4m and
is primarily concerned with documenting the new CG3 framebuffer whilst touching
up a couple of minor errors. The second updates the documentation with respect
to the default PowerPC framebuffer settings which wa
Instead of checking and calling unavailable_host_feature() once for each
bit, simply call the function (now renamed to
report_unavailable_features()) once for each feature word.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* Rebase to latest qom-cpu (commit 90c5d39c)
---
target-i386/cpu
On Mon, 2014-03-17 at 22:29 +0100, Christian Borntraeger wrote:
> On 17/03/14 22:25, Peter Maydell wrote:
> > On 17 March 2014 20:56, Christian Borntraeger
> > wrote:
> >> Turns out that valgrind is right. We simply forget the memory that
> >> g_strconcat has allocated.
> >> This fixes the small
valgrind complains about a memory leak in irq setup of sclpconsole:
==42117== 8 bytes in 1 blocks are definitely lost in loss record 89 of 833
==42117==at 0x4031AFE: malloc (vg_replace_malloc.c:292)
==42117==by 0x8022F855: malloc_and_trace (vl.c:2715)
==42117==by 0x4145569: g_malloc (i
valgrind complains about a memory leak in irq setup of sclpconsole:
==42117== 8 bytes in 1 blocks are definitely lost in loss record 89of 833
==42117==at 0x4031AFE: malloc (vg_replace_malloc.c:292)
==42117==by 0x8022F855: malloc_and_trace (vl.c:2715)
==42117==by 0x4145569: g_malloc (in
The following changes since commit 087edb503afebf184f07078900efc26c73035e98:
Merge remote-tracking branch 'remotes/bonzini/fixes-for-2.0' into staging
(2014-03-17 13:05:48 +)
are available in the git repository at:
git://github.com/borntraeger/qemu.git tags/kvm-s390-2014031
Am 17.03.2014 22:29, schrieb Christian Borntraeger:
> On 17/03/14 22:25, Peter Maydell wrote:
>> On 17 March 2014 20:56, Christian Borntraeger wrote:
>>> Turns out that valgrind is right. We simply forget the memory that
>>> g_strconcat has allocated.
>>> This fixes the small leak, but I have to
On 17 March 2014 20:56, Christian Borntraeger wrote:
> Turns out that valgrind is right. We simply forget the memory that
> g_strconcat has allocated.
> This fixes the small leak, but I have to cast away the constness of .name.
> Any better ideas?
It's how cpu_register() in target-arm/cpu.c does
valgrind complains about the following:
==42117== 8 bytes in 1 blocks are definitely lost in loss record 88 of 833
==42117==at 0x4031AFE: malloc (vg_replace_malloc.c:292)
==42117==by 0x8022F855: malloc_and_trace (vl.c:2715)
==42117==by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0
commit 18674b26788a9e47f1157170234e32ece2044367
(elf-loader: add more return codes) enabled the elf loader to return
other errors than -1.
Lets also handle that case for our "BIOS" on s390.
Signed-off-by: Christian Borntraeger
CC: Alexey Kardashevskiy
CC: Alexander Graf
---
hw/s390x/ipl.c | 2
On 16.03.2014 00:16, Benoît Canet wrote:
The Saturday 15 Mar 2014 à 21:55:54 (+0100), Max Reitz wrote :
If qcow2_alloc_clusters() fails, new_offset and ret will both be
negative after the fail label, thus passing the first if condition and
subsequently resulting in a call of qcow2_free_clusters(
Marcel,
after
commit 261747f176f6 (vl: Use MachineClass instead of global QEMUMachine list)
valgrind complains about the following:
==54082== 57 bytes in 3 blocks are definitely lost in loss record 365 of 729
==54082==at 0x4031AFE: malloc (vg_replace_malloc.c:292)
==54082==by 0x4145569
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