Il 07/03/2014 04:07, Hu Tao ha scritto:
There is already an accepted version de580dafade551.
Paolo, I found that your numa tree is behind current master about 99
commits. I'd like to take over this series if you have no time on it.
Sure, I rebased it and pushed it again (not tested the rebase
Il 07/03/2014 01:40, Marcelo Tosatti ha scritto:
Failing initialization in case hugepage path has
hugepage smaller than specified.
Signed-off-by: Marcelo Tosatti
Why is this needed? Isn't it just operator error?
Perhaps libvirt could add an attribute to its XML element,
and could use it
On Wed, 02/26 17:35, Jeff Cody wrote:
> On Sun, Feb 23, 2014 at 09:54:46AM +0800, Fam Zheng wrote:
> > This is the common but non-trivial steps to assign or change the
> > backing_hd of BDS.
> >
> > Signed-off-by: Fam Zheng
> > ---
> > block.c | 46 +
On Thu, 02/27 13:12, Markus Armbruster wrote:
> Fam Zheng writes:
>
> > This drops BlockDriverState.in_use with op_blockers:
> >
> > - Call bdrv_op_block_all in place of bdrv_set_in_use(bs, 1).
> > - Call bdrv_op_unblock_all in place of bdrv_set_in_use(bs, 0).
> > - Check bdrv_op_is_blocked
Il 07/03/2014 07:09, Hu Tao ha scritto:
On Tue, Mar 04, 2014 at 03:00:44PM +0100, Paolo Bonzini wrote:
Split the internal interface in exec.c to a separate function, and
push the check on mem_path up to memory_region_init_ram.
Signed-off-by: Paolo Bonzini
---
exec.c | 105 +++
Il 07/03/2014 06:33, Hu Tao ha scritto:
On Tue, Mar 04, 2014 at 03:00:43PM +0100, Paolo Bonzini wrote:
This option provides the infrastructure for binding guest NUMA nodes
to host NUMA nodes. For example:
-object memory-ram,size=1024M,policy=membind,host-nodes=0,id=ram-node0 \
-numa node,nod
On Thu, 03/06 11:27, Paolo Bonzini wrote:
> We were always truncating the sense size to 96 bytes.
>
> Signed-off-by: Paolo Bonzini
> ---
> hw/scsi/virtio-scsi.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c
> index 6610
Il 07/03/2014 03:56, Hu Tao ha scritto:
-obj = object_new(type);
-if (qemu_opt_foreach(opts, object_set_property, obj, 1) < 0) {
-object_unref(obj);
-return -1;
+qdict_del(pdict, "qom-type");
+visit_type_str(opts_get_visitor(ov), &type, "qom-type", &err);
+if (
Il 07/03/2014 04:31, Serge Hallyn ha scritto:
Hi,
At https://bugs.launchpad.net/bugs/1284793 it was found that commit
a66e657e: "pci/pcie: convert PCIE hotplug to use hotplug-handler API"
seems to break vga passthrough. Reverting that commit (plus one more
to reintroduce a needed definition) fi
Il 07/03/2014 02:19, Lluís Vilanova ha scritto:
Lluís Vilanova writes:
Lluís Vilanova writes:
Pass all the relevant sub-directory make variables.
Ping.
Ping^2
Thanks,
Lluis
Signed-off-by: Lluís Vilanova
---
Makefile |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Il 07/03/2014 00:32, Alexander Graf ha scritto:
Older gcc versions (such as the one in SLES11) get confused when you declare
a typedef on the same struct twice.
To work around that limitation, let's extract the QEMUMachine typedef into a
separate header file that is guarded by preprocessor dupli
On Tue, Mar 04, 2014 at 03:00:50PM +0100, Paolo Bonzini wrote:
> This allows the superclass to set various policies on the memory
> region that the subclass creates.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Paolo Bonzini
> ---
> backends/hostmem-file.c | 9 -
> backends/hostme
Currently, the default msix vectors for virtio-net-pci is 3 which is
obvious not suitable for multiqueue guest, so we depends on the user
or management tools to pass a correct vectors parameter. In fact, we
can simplifying this by calculate the number of vectors on init.
Consider we have N queues,
On Tue, Mar 04, 2014 at 03:00:49PM +0100, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> backends/Makefile.objs | 1 +
> backends/hostmem-file.c | 108
>
> 2 files changed, 109 insertions(+)
> create mode 100644 backends/hostmem-f
On Fri, Mar 07, 2014 at 02:09:25PM +0800, Hu Tao wrote:
> On Tue, Mar 04, 2014 at 03:00:44PM +0100, Paolo Bonzini wrote:
> > Split the internal interface in exec.c to a separate function, and
> > push the check on mem_path up to memory_region_init_ram.
> >
> > Signed-off-by: Paolo Bonzini
> > ---
On Thu, Mar 06, 2014 at 02:23:15PM -0700, Eric Blake wrote:
> On 03/05/2014 07:36 PM, Amos Kong wrote:
> > vm_config_groups[] only contains part of the options which have
> > argument, and all options which have no argument aren't added
> > to vm_config_groups[]. Current query-command-line-options
On Tue, Mar 04, 2014 at 03:00:44PM +0100, Paolo Bonzini wrote:
> Split the internal interface in exec.c to a separate function, and
> push the check on mem_path up to memory_region_init_ram.
>
> Signed-off-by: Paolo Bonzini
> ---
> exec.c | 105
> +--
vm_config_groups[] only contains part of the options which have
parameters, and all options which have no parameter aren't added
to vm_config_groups[]. Current query-command-line-options only
checks options from vm_config_groups[], so some options will
be lost.
We have macro in qemu-options.hx to
Signed-off-by: Amos Kong
Reviewed-by: Eric Blake
---
util/qemu-config.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/qemu-config.c b/util/qemu-config.c
index f610101..d2facfd 100644
--- a/util/qemu-config.c
+++ b/util/qemu-config.c
@@ -39,7 +39,7 @@ QemuOptsLi
This patchset fixed some issues of query-command-line-options:
* some new options that haven't argument can't be queried. (eg: -enable-fips)
* some legacy options that have argument can't be queried. (eg: -vnc display)
More discussion:
http://marc.info/?l=qemu-devel&m=139081830416684&w=2
V2: r
On Tue, Mar 04, 2014 at 03:00:43PM +0100, Paolo Bonzini wrote:
> This option provides the infrastructure for binding guest NUMA nodes
> to host NUMA nodes. For example:
>
> -object memory-ram,size=1024M,policy=membind,host-nodes=0,id=ram-node0 \
> -numa node,nodeid=0,cpus=0,memdev=ram-node0 \
>
On Fri, 2014-03-07 at 12:16 +1100, Alexey Kardashevskiy wrote:
> On 03/07/2014 10:44 AM, Andreas Färber wrote:
> > Am 05.03.2014 18:30, schrieb Marcel Apfelbaum:
> >> In order to allow attaching machine options to a machine instance,
> >> current_machine is converted into MachineState.
> >> As a fi
On Fri, 2014-03-07 at 00:44 +0100, Andreas Färber wrote:
> Am 05.03.2014 18:30, schrieb Marcel Apfelbaum:
> > In order to allow attaching machine options to a machine instance,
> > current_machine is converted into MachineState.
> > As a first step of deprecating QEMUMachine, some of the functions
Ping
On Fri, Feb 28, 2014 at 9:15 AM, Alistair Francis
wrote:
> This patch implements the ARM PMCCNTR register including
> the disable and reset components of the PMCR register.
>
> Signed-off-by: Alistair Francis
> ---
> V9: Completely #ifndef out the PMCR and PMCCNTR registers. Also use
> CONF
This changes resource code definitions to ones used in the host kernel.
This fixes H_SET_MODE_RESOURCE_LE (switch between big endian and
little endian) to sync registers from KVM before changing LPCR value.
This adds a set_spr() helper to update an SPR in a CPU's context to avoid
possible races a
This fixes H_SET_MODE.
Changes:
v4:
* rebased on top of current ppc-next.
* changed PPC2_ISA207S flag value
Alexey Kardashevskiy (3):
target-ppc: introduce powerisa-207-server flag
spapr-hcall: fix little-endian resource handling in H_SET_MODE
spapr-hcall: add address-translation-mode-on-in
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr_hcall.c | 26 ++
target-ppc/cpu.h | 2 ++
2 files changed, 28 insertions(+)
diff --git a/hw/ppc/spa
This flag will be used to decide whether to emulate some bits of
H_SET_MODE hypercall because some are POWER8-only.
While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already
have it.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h| 2 ++
target-ppc/translate_
On 03/06/2014 05:40 PM, Marcelo Tosatti wrote:
>
> Failing initialization in case hugepage path has
> hugepage smaller than specified.
>
> Signed-off-by: Marcelo Tosatti
>
> diff --git a/exec.c b/exec.c
> index b69fd29..c95a0f3 100644
> --- a/exec.c
> +++ b/exec.c
> };
>
> +static QemuOpts
On 03/07/2014 03:32 AM, Peter Maydell wrote:
This is v4 of the AArch64 system emulation patches, and it's
an important milestone -- this is enough to boot a Linux kernel.
Does this boot an aarch64 kernel with tcg on x86 host?
--
Thanks,
Xuebing Wang
On 02/14/2014 08:30 PM, Alexey Kardashevskiy wrote:
> On 02/11/2014 11:16 PM, Alexey Kardashevskiy wrote:
>> On 02/11/2014 11:12 PM, Alexander Graf wrote:
>>> On 02/11/2014 08:44 AM, Alexey Kardashevskiy wrote:
On 01/22/2014 04:43 PM, Alexey Kardashevskiy wrote:
> This fixes H_SET_MODE.
>>
On Tue, Mar 04, 2014 at 03:00:42PM +0100, Paolo Bonzini wrote:
> From: Igor Mammedov
>
> Provides framework for splitting host RAM allocation/
> policies into a separate backend that could be used
> by devices.
>
> Initially only legacy RAM backend is provided, which
> uses memory_region_init_ra
Hi,
At https://bugs.launchpad.net/bugs/1284793 it was found that commit
a66e657e: "pci/pcie: convert PCIE hotplug to use hotplug-handler API"
seems to break vga passthrough. Reverting that commit (plus one more
to reintroduce a needed definition) fixed it. Do you have any
idea what would have br
On Tue, Mar 04, 2014 at 03:00:41PM +0100, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> hw/i386/pc.c| 4 +---
> include/hw/boards.h | 4
> include/sysemu/sysemu.h | 1 +
> numa.c | 11 +++
> 4 files changed, 17 insertions(+), 3 deleti
Reviewed-by: Hu Tao
On Tue, Mar 04, 2014 at 03:00:40PM +0100, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> hw/i386/pc.c | 11 +--
> hw/i386/pc_piix.c| 8 +++-
> hw/i386/pc_q35.c | 4 +---
> include/hw/i386/pc.h | 7 +++
> 4 files changed, 12 ins
On Tue, Mar 04, 2014 at 03:00:39PM +0100, Paolo Bonzini wrote:
> Use QERR_INVALID_PARAMETER_VALUE for consistency, and avoid an assertion
> failure if the class name is incorrect.
>
> Signed-off-by: Paolo Bonzini
> ---
> qmp.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> d
On Tue, Mar 04, 2014 at 03:00:37PM +0100, Paolo Bonzini wrote:
> Follow the lines of the HMP implementation, using OptsVisitor
> to parse the options. This gives access to OptsVisitor's
> rich parsing of integer lists.
>
> Signed-off-by: Paolo Bonzini
> ---
> vl.c | 87
> ++
From: Alexey Kardashevskiy
PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of
316.
This fixes the definition of LPCR SPR.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 2 +-
target-ppc/translate_init.c | 2 +-
2 file
From: Tom Musta
This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are refactored to use this macro.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Al
From: Tom Musta
This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 46 +++
From: Tom Musta
This patch refactors the stxsdx instruction. Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 27 +++
Am 05.03.2014 18:30, schrieb Marcel Apfelbaum:
> In order to allow attaching machine options to a machine instance,
> current_machine is converted into MachineState.
> As a first step of deprecating QEMUMachine, some of the functions
> were modified to return MachineCLass.
>
> Signed-off-by: Marce
From: Tom Musta
This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 4 +++-
target-ppc/translate_init.c | 9 ++---
2 f
When we have 2 separate qdev devices that both create a qbus of the
same type without specifying a bus name or device name, we end up
with two buses of the same name, such as ide.0 on the Mac machines:
dev: macio-ide, id ""
bus: ide.0
type IDE
dev: macio-ide, id ""
bus: ide.0
From: Tom Musta
The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.
Also, t
From: Alexey Kardashevskiy
When the guests adds buffers to receive queue, the network device
should flush its queue of pending packets. This is done with
qemu_flush_queued_packets.
This adds a call to qemu_flush_queued_packets() which wakes up the main
loop and let QEMU update the network device
From: Tom Musta
This patch adds the Vector Minimum and Maximum Doubleword instructions
that are introduced in Power ISA Version 2.07.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/helper.h | 4
target-ppc/int_helper.c | 2 ++
target-ppc/translate.c | 8 ++
From: Tom Musta
This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 50 +
From: Tom Musta
This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 47
On Tue, Mar 04, 2014 at 03:00:35PM +0100, Paolo Bonzini wrote:
> Reviewed-by: Laszlo Ersek
> Signed-off-by: Paolo Bonzini
> ---
> include/qemu/config-file.h | 2 ++
> util/qemu-config.c | 14 ++
> vl.c | 11 +--
> 3 files changed, 17 insertions(
F_[GS]ETOWN is replaced by F_[GS]ETOWN_EX inside the glibc fcntl wrapper.
Signed-off-by: Andreas Schwab
---
linux-user/syscall.c | 10 ++
linux-user/syscall_defs.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 2f573b8..51
From: Tom Musta
This patch adds the Unpack Signed Word instructions introduced in
Power ISA Version 2.07:
- Vector Unpack High Signed Word (vupkusw)
- Vector Unpack Low Signed Word (vupklsw)
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/helper.h | 2 ++
target
From: Alexey Kardashevskiy
Recent changes introduced cannot_instantiate_with_device_add_yet
and removed capability of adding yet another PCI host bridge via
command line for SPAPR platform (POWERPC64 server).
This brings the capability back and puts SPAPR PHB into "bridge"
category.
This is not
From: "Aneesh Kumar K.V"
Correctly update the htab_mask using the return value of
KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1
on GET_SREGS for HV. We check for external htab and if
found true, we don't need to update sdr1
Signed-off-by: Aneesh Kumar K.V
[ fixed pte group offset compu
From: Tom Musta
This patch adds the Vector Count Leading Zeroes instructions introduced
in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/helper.h | 5 +
target-ppc/int_helper.c | 29 ++
From: Cédric Le Goater
The latest glibc provides a memrchr routine using an extended opcode
of the 'dcbt' instruction :
000a7cc0 :
a7cc0: 11 00 4c 3c addis r2,r12,17
a7cc4: b8 f8 42 38 addir2,r2,-1864
a7cc8: 14 2a e3 7c add r7,r3,r5
a7c
From: Alexey Kardashevskiy
Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with
970 user manuals/P5-bookIV/PowerISA204 which define the number as:
priviledged
# spr5-9 spr0-4 name mtspr mfspr len cat
136 00100 01000 CTRL -no32 S
152 0010
On 4 March 2014 13:41, Peter Maydell wrote:
> On 4 March 2014 11:32, Alex Bennée wrote:
> > Is the effect of this to report system uname or minimum whichever is
higher?
>
> That's what this patch does. The old configure stuff which
> this patchset removed made it report "always that version",
> I
From: Tom Musta
This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 35
From: "Aneesh Kumar K.V"
We will use this in later patches to make sure we use the right load
functions when copying hpte entries.
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Alexander Graf
---
hw/ppc/spapr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/pp
From: Tom Musta
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 31 +++
target-ppc/helpe
From: Tom Musta
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 4 +++-
ta
From: Peter Maydell
64 bit constants need the "ULL" suffix, not just "UL", because
on 32 bit platforms 'long' is not large enough and this will
cause a compiler warning.
Signed-off-by: Peter Maydell
Reviewed-by: Stefan Weil
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 4 ++--
1
From: Alexey Kardashevskiy
When ppc_store_slb() is called from kvm_arch_get_registers(), it stores
a SLB in CPUPPCState::slb[slot]. However it drops the slot number from
ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not
have correct "index" field anymore. This broke migrati
From: Tom Musta
This patch adds two Altivec unsigned doublword modulo instructions that
are introduced in Power ISA Version V2.07:
- vaddudm : Vector Add Unsigned Doubleword Modulo
- vsubudm : Vector Subtrace Unsigned Doubleword Modulo
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
From: Tom Musta
This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:
- Vector Multiply Even Unsigned Word (vmuleuw)
- Vector Multiply Even Signed Word (vmulesw)
- Vector Multiply Odd Unsigned Word (vmulouw)
- Vector Multiply Odd Signed Wo
From: Tom Musta
This patch adds the VSX floating point divide instructions defined
by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 49 ++
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org]
> On Behalf Of Stefan Hajnoczi
> Sent: Friday, February 14, 2014 7:58 AM
> To: Cedric Bosdonnat
> Cc: Jan Kiszka; qemu-devel; kvm; libvir-l...@redhat.com; Kevin Wolf; Peter
> Maydell; Peter Crosthwaite
From: Tom Musta
This patch adds the non-signalling scalar conversion instructions:
- VSX Scalar Convert Single Precision to Double Precision
Non-Signalling (xscvspdpn)
- VSX Scalar Convert Double Precision to Single Precision
Non-Signalling (xscvdpspn)
Signed-off-by: Tom Musta
Revi
From: Alexey Kardashevskiy
The 970GX definition was added in 2007 and it made sense then but this
version has never been released to the markets and it does not exist in
the real world so there is no point in emulating it.
This removes 970GX.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by:
From: Tom Musta
This patch adds the Book I (user space) Load Quadword (lq) instruction.
This instruction was introduced into Book I in Power ISA V2.07. Previous
versions of the architecture supported this as a privileged instruction.
Previous versions of the architecture also did not support Lit
From: Tom Musta
This patch adds the Vector Compare Doubleword instructions introduced
by Power ISA Version 2.07:
- Vector Compare Equal to Unsigned Doubleword (vcmpequd)
- Vector Compare Greater Than Signed Doubleword (vcmpgtsd)
- Vector Compare Greater Than Unsigned Doubleword (vcmpgtud)
On 03/06/2014 03:25 PM, Max Reitz wrote:
> The hdev_create() implementation in block/raw-posix.c is used by the
> "host_device", "host_cdrom" and "host_floppy" protocol block drivers
> together. Thus, it any of the associated prefixes may occur and exactly
s/it //
> one should be stripped, if it
Hi Blue / Aurelien / Anthony / Peter,
This is my current patch queue for ppc. Please pull.
This pull request includes:
- VSX emulation support
- book3s pr/hv selection
- some bug fixes
- qdev stable numbering
- eTSEC emulation
Alex
The following changes since commit f55ea6297cc022
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
[agraf: fix up stray quotes and newlines in strings]
Signed-off-by: Alexander Graf
---
hw/ppc/virtex_ml507.c | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/virtex_ml507.c b
From: Tom Musta
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.
Signed-off-by: Tom Musta
Reviewed-
On 02/21/2014 07:24 PM, Alexander Graf wrote:
>
> On 21.02.2014, at 07:09, Alexey Kardashevskiy wrote:
>
>> On 02/10/2014 05:52 PM, Alexey Kardashevskiy wrote:
>>> The changelog is:
version: update to 20140204
virtio-9p: disable unused structure
Make "boot net:dhcp" boot from IPv4
From: Alexey Kardashevskiy
PR KVM lacks support of many SPRs in set/get one register API but it does
really break PR KVM. So convert them to switchable traces for now.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
target-ppc/kvm.c | 7 +++
trace-events | 2 ++
From: Tom Musta
This patch adds the VSX floating point test for software divide
instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,
and xvtdivsp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 67 +
From: Alexey Kardashevskiy
The Figure 17 "SPR encodings" of the PowerISA 2.07 describes CTRL SPR as:
priviledged
# spr5-9 spr0-4 name mtspr mfspr len cat
136 00100 01000 CTRL -no32 S
152 00100 11000 CTRL yes-32 S
According to this chart, the hyp
From: Tom Musta
This patch updates the ppc_avr_t data structure to include elements for
signed 64-bit integers and (conditionally) unsigned 128 bit integers.
These elements will be in instructions models later on in this patch series.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
From: Alexey Kardashevskiy
SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5
bookIV nor PowerISA 2.04, the numbers assigned to them are not defined
either so remove them.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c |
From: Tom Musta
This patch adds the Vector Population Count instructions introduced in Power
ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/helper.h | 4
target-ppc/int_helper.c | 14 ++
From: Tom Musta
The existing implementation of xxpermdi is defective if the target
VSR is also a source VSR. This patch fixes the defect in this case
but also preserves the simpler, two TCG operation implementation
when the target is not once of the two sources.
Signed-off-by: Tom Musta
Signed
From: Tom Musta
This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 28
1 file changed, 28 inse
Lluís Vilanova writes:
> Lluís Vilanova writes:
>> Pass all the relevant sub-directory make variables.
> Ping.
Ping^2
> Thanks,
> Lluis
>> Signed-off-by: Lluís Vilanova
>> ---
>> Makefile |2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>> diff --git a/Makefile b/Makefile
>> in
From: Tom Musta
This patch addes the Unsigned Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 31 +++
On 03/07/2014 10:44 AM, Andreas Färber wrote:
> Am 05.03.2014 18:30, schrieb Marcel Apfelbaum:
>> In order to allow attaching machine options to a machine instance,
>> current_machine is converted into MachineState.
>> As a first step of deprecating QEMUMachine, some of the functions
>> were modifi
From: Tom Musta
This patch adds a flag for the floating point conversion instructions
introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 5 -
target-ppc/translate_init.c | 6 +++---
2 file
From: Tom Musta
This VMUL_DO macro provides support for the various vmule* and vmulo*
instructions. These instructions multiply vector elements, producing
products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit
elements and produces a 16 bit unsigned element.
The existing macr
于 2014/3/7 3:58, Luiz Capitulino 写道:
On Thu, 06 Mar 2014 11:14:01 -0700
Eric Blake wrote:
On 01/06/2014 04:18 PM, Luiz Capitulino wrote:
On Fri, 3 Jan 2014 07:10:29 +0800
Wenchao Xia wrote:
This series add support for tag/keyword 'event' in qapi-schema.
A new file was created to store som
于 2014/3/6 21:03, Luiz Capitulino 写道:
On Thu, 06 Mar 2014 19:54:33 +0800
Wenchao Xia wrote:
于 2014/3/6 16:25, Markus Armbruster 写道:
Wenchao Xia writes:
By default, any union will automatically generate a enum type as
"[UnionName]Kind" in C code, and it is duplicated when the discriminator
From: Tom Musta
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.
The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alex
By default, any union will automatically generate a enum type as
"[UnionName]Kind" in C code, and it is duplicated when the discriminator
is specified as a pre-defined enum type in schema. After this patch,
the pre-defined enum type will be really used as the switch case
condition in generated C co
From: Alexey Kardashevskiy
This makes use of new error codes which load_elf() can return and
prints more informative error message.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
hw/ppc/spapr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw
From: Tom Musta
This patch adds the vector doublword rotate and shift instructions
introduced in Power ISA Version 2.07:
- Vector Rotate Left Doubleword instruction (vrld)
- Vector Shift Left Doubleword (vsld)
- Vector Shift Right Doubleword (vsrd)
- Vector Shift Right Algegbraic Doublew
From: Tom Musta
This patch adds the Branch Conditional to Address Register (bctar)
instruction.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc
From: Alexey Kardashevskiy
PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category so
remove it from POWER7/8 class as it is "S" (server) category.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 46 ---
From: Tom Musta
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/fpu_helper.c | 56 -
ta
From: Alexey Kardashevskiy
The existing load_elf() just returns -1 if it fails to load ELF. However
it could be smarter than this and tell more about the failure such as
wrong endianness or incompatible platform.
This adds additional return codes for wrong architecture, wrong
endianness and if t
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