Hi Blue / Aurelien / Anthony / Peter,
This is my current patch queue for ppc. Please pull.
This pull request includes:
- VSX emulation support
- book3s pr/hv selection
- some bug fixes
- qdev stable numbering
- eTSEC emulation
Alex
The following changes since commit f55ea6297cc0224fe4934b90ff5343b620b14669:
block/gluster: Add missing argument to qemu_gluster_init() call (2014-03-04
20:20:57 +0000)
are available in the git repository at:
git://github.com/agraf/qemu.git tags/signed-ppc-for-upstream
for you to fetch changes up to 0f20ba62c35e6a779ba4ea00616192ef2abb6896:
target-ppc: spapr: e500: fix to use cpu_dt_id (2014-03-05 03:07:04 +0100)
----------------------------------------------------------------
Patch queue for ppc - 2014-03-05
This pull request includes:
- VSX emulation support
- book3s pr/hv selection
- some bug fixes
- qdev stable numbering
- eTSEC emulation
----------------------------------------------------------------
Alexander Graf (3):
KVM: Split QEMUMachine typedef into separate header
qdev: Keep global allocation counter per bus
PPC: sPAPR: Only use getpagesize() when we run with kvm
Alexey Kardashevskiy (19):
target-ppc: fix compile error when PPC_DUMP_CPU is enabled
target-ppc: fix LPCR SPR number
target-ppc: remove powerpc 970gx
target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers
target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8
target-ppc: remove unsupported SPRs from 970 and P5+
target-ppc: fix Authority Mask Register init value
PPC: KVM: fix "set one register"
spapr-pci: enable adding PHB via -device
target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL
PPC: KVM: store SLB slot number
PPC: KVM: suppress warnings about not supported SPRs
spapr: support only ELF kernel images
moxie: fix load_elf() usage
elf-loader: add more return codes
spapr: print more detailed error message on failed load_elf()
spapr-vlan: flush queue whenever can_receive can go from false to true
target-ppc: add PowerPCCPU::cpu_dt_id
target-ppc: spapr: e500: fix to use cpu_dt_id
Aneesh Kumar K.V (6):
kvm: Add a new machine option kvm-type
target-ppc: Update external_htab even when HTAB is managed by kernel
target-ppc: Fix htab_mask calculation
target-ppc: Fix page table lookup with kvm enabled
target-ppc: Change the hpte store API
target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel
htab
Anton Blanchard (1):
target-ppc: dump DAR and DSISR
Cédric Le Goater (2):
mmu-hash64: fix Virtual Page Class Key Protection
target-ppc: add extended opcodes for dcbt/dcbtst
Edgar E. Iglesias (1):
virtex_ml507: Add support for loading initrd images
Fabien Chouteau (1):
Add Enhanced Three-Speed Ethernet Controller (eTSEC)
Greg Kurz (1):
PPC: KVM: add support for LPCR
Laurent Dufour (1):
target-ppc: Introduce hypervisor call H_GET_TCE
Nathan Whitehorn (1):
spapr_vscsi: Fix REPORT_LUNS handling
Peter Maydell (1):
target-ppc/translate.c: Use ULL suffix for 64 bit constants
Tom Musta (93):
target-ppc: Add set_fprf Argument to fload_invalid_op_excp()
target-ppc: General Support for VSX Helpers
target-ppc: Add VSX ISA2.06 xadd/xsub Instructions
target-ppc: Add VSX ISA2.06 xmul Instructions
target-ppc: Add VSX ISA2.06 xdiv Instructions
target-ppc: Add VSX ISA2.06 xre Instructions
target-ppc: Add VSX ISA2.06 xsqrt Instructions
target-ppc: Add VSX ISA2.06 xrsqrte Instructions
target-ppc: Add VSX ISA2.06 xtdiv Instructions
target-ppc: Add VSX ISA2.06 xtsqrt Instructions
target-ppc: Add VSX ISA2.06 Multiply Add Instructions
target-ppc: Add VSX xscmp*dp Instructions
target-ppc: Add VSX xmax/xmin Instructions
target-ppc: Add VSX Vector Compare Instructions
target-ppc: Add VSX Floating Point to Floating Point Conversion
Instructions
target-ppc: Add VSX ISA2.06 Integer Conversion Instructions
target-ppc: Add VSX Rounding Instructions
target-ppc: VSX Stage 4: Add VSX 2.07 Flag
target-ppc: VSX Stage 4: Refactor lxsdx
target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx
target-ppc: VSX Stage 4: Refactor stxsdx
target-ppc: VSX Stage 4: Add stxsiwx and stxsspx
target-ppc: VSX Stage 4: Add xsaddsp and xssubsp
target-ppc: VSX Stage 4: Add xsmulsp
target-ppc: VSX Stage 4: Add xsdivsp
target-ppc: VSX Stage 4: Add xsresp
target-ppc: VSX Stage 4: Add xssqrtsp
target-ppc: VSX Stage 4: add xsrsqrtesp
target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds
target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp
target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc
target-ppc: Move To/From VSR Instructions
target-ppc: Floating Merge Word Instructions
target-ppc: Scalar Round to Single Precision
target-ppc: Scalar Non-Signalling Conversions
target-ppc: Add ISA2.06 bpermd Instruction
target-ppc: Add Flag for ISA2.06 Divide Extended Instructions
target-ppc: Add ISA2.06 divdeu[o] Instructions
target-ppc: Add ISA2.06 divde[o] Instructions
target-ppc: Add ISA 2.06 divweu[o] Instructions
target-ppc: Add ISA 2.06 divwe[o] Instructions
target-ppc: Add Flag for ISA2.06 Atomic Instructions
target-ppc: Add ISA2.06 lbarx, lharx Instructions
target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
target-ppc: Add Flag for ISA V2.06 Floating Point Conversion
target-ppc: Add ISA2.06 Float to Integer Instructions
target-ppc: Add ISA 2.06 fcfid[u][s] Instructions
target-ppc: Fix and enable fri[mnpz]
target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions
target-ppc: Add ISA 2.06 ftdiv Instruction
target-ppc: Add ISA 2.06 ftsqrt
target-ppc: Enable frsqrtes on Power7 and Power8
target-ppc: Add ISA2.06 lfiwzx Instruction
target-ppc: Fix xxpermdi When T==A or T==B
target-ppc: Add Flag for bctar
target-ppc: Add Target Address SPR (TAR) to Power8
target-ppc: Add bctar Instruction
target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions
target-ppc: Add is_user_mode Utility Routine
target-ppc: Load Quadword
target-ppc: Store Quadword
target-ppc: Add Load Quadword and Reserve
target-ppc: Add Store Quadword Conditional
target-ppc: Altivec 2.07: Add Instruction Flag
target-ppc: Altivec 2.07: Update AVR Structure
target-ppc: Altivec 2.07: Add GEN_VXFORM3
target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions
target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions
target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions
target-ppc: Altivec 2.07: Vector Logical Instructions
target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo
target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers
target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions
target-ppc: Altivec 2.07: vmuluw Instruction
target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes
target-ppc: Altivec 2.07: Vector Population Count Instructions
target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions
target-ppc: Altivec 2.07: Pack Doubleword Instructions
target-ppc: Altivec 2.07: Unpack Signed Word Instructions
target-ppc: Altivec 2.07: Vector Merge Instructions
target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and
Shifts
target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions
target-ppc: Altivec 2.07: Quadword Addition and Subtracation
target-ppc: Altivec 2.07: vbpermq Instruction
target-ppc: Altivec 2.07: Doubleword Compares
target-ppc: Altivec 2.07: Vector Gather Bits by Bytes
target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum
target-ppc: Altivec 2.07: Binary Coded Decimal Instructions
target-ppc: Altivec 2.07: AES Instructions
target-ppc: Altivec 2.07: Vector SHA Sigma Instructions
target-ppc: Altivec 2.07: Vector Permute and Exclusive OR
target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL
target-ppc: Use Additional Temporary in stqcx Case
default-configs/ppc-softmmu.mak | 1 +
hw/core/loader.c | 30 +-
hw/core/qdev.c | 20 +-
hw/i386/pc_piix.c | 8 +-
hw/intc/openpic_kvm.c | 2 +-
hw/intc/xics.c | 15 +-
hw/intc/xics_kvm.c | 10 +-
hw/moxie/moxiesim.c | 2 +-
hw/net/Makefile.objs | 3 +
hw/net/fsl_etsec/etsec.c | 465 +++++++++++++
hw/net/fsl_etsec/etsec.h | 174 +++++
hw/net/fsl_etsec/miim.c | 146 ++++
hw/net/fsl_etsec/registers.c | 295 ++++++++
hw/net/fsl_etsec/registers.h | 320 +++++++++
hw/net/fsl_etsec/rings.c | 650 ++++++++++++++++++
hw/net/spapr_llan.c | 2 +
hw/ppc/e500.c | 7 +-
hw/ppc/ppc.c | 22 +
hw/ppc/spapr.c | 56 +-
hw/ppc/spapr_hcall.c | 87 ++-
hw/ppc/spapr_iommu.c | 37 +
hw/ppc/spapr_pci.c | 15 +-
hw/ppc/spapr_rtas.c | 14 +-
hw/ppc/virtex_ml507.c | 34 +-
hw/s390x/ipl.c | 4 +-
hw/scsi/spapr_vscsi.c | 60 ++
include/hw/boards.h | 6 +-
include/hw/elf_ops.h | 19 +-
include/hw/loader.h | 6 +
include/hw/qdev-core.h | 2 +
include/hw/xen/xen.h | 3 +-
include/qemu/host-utils.h | 28 +
include/sysemu/kvm.h | 3 +-
include/sysemu/qemumachine.h | 16 +
include/sysemu/qtest.h | 3 +-
kvm-all.c | 17 +-
kvm-stub.c | 3 +-
linux-user/main.c | 18 +-
qtest.c | 2 +-
target-ppc/STATUS | 9 -
target-ppc/cpu-models.c | 2 -
target-ppc/cpu-models.h | 1 -
target-ppc/cpu-qom.h | 2 +
target-ppc/cpu.h | 55 +-
target-ppc/fpu_helper.c | 1294 +++++++++++++++++++++++++++++++----
target-ppc/helper.h | 207 ++++++
target-ppc/int_helper.c | 1411 +++++++++++++++++++++++++++++++++++++--
target-ppc/kvm.c | 117 +++-
target-ppc/kvm_ppc.h | 35 +-
target-ppc/machine.c | 11 +-
target-ppc/misc_helper.c | 4 +-
target-ppc/mmu-hash64.c | 117 +++-
target-ppc/mmu-hash64.h | 47 +-
target-ppc/mmu_helper.c | 3 +-
target-ppc/translate.c | 1268 +++++++++++++++++++++++++++++++----
target-ppc/translate_init.c | 274 ++------
trace-events | 3 +
util/host-utils.c | 75 +++
vl.c | 14 +-
xen-all.c | 2 +-
xen-stub.c | 2 +-
61 files changed, 6818 insertions(+), 740 deletions(-)
create mode 100644 hw/net/fsl_etsec/etsec.c
create mode 100644 hw/net/fsl_etsec/etsec.h
create mode 100644 hw/net/fsl_etsec/miim.c
create mode 100644 hw/net/fsl_etsec/registers.c
create mode 100644 hw/net/fsl_etsec/registers.h
create mode 100644 hw/net/fsl_etsec/rings.c
create mode 100644 include/sysemu/qemumachine.h
