On 12/20/2013 06:33 PM, Peter Maydell wrote:
> This sounds like it could work, though there are some wrinkles for
> registers with readfns/writefns -- do we have extra s vs ns read/write
> functions, or just one set of functions which has to look in env->ns to
> figure out whether to use the S or
On 12/22/2013 05:08 AM, Peter Crosthwaite wrote:
> On Sat, Dec 21, 2013 at 12:33 AM, Peter Maydell
> wrote:
>> On 20 December 2013 14:12, Fedorov Sergey wrote:
>>> I've briefly looked at the v8 ARM ARM. As I can see there is no banked
>>> system control registers in AArch64. Seems the concept is
On Mon, Dec 23, 2013 at 02:32:46PM +0800, Wenchao Xia wrote:
> Hi, Amos
>
> >(resend without big attachment)
> >
> >Hello Eric, other
> >
> >We had "command, enumeration, type, unionobj" in Eric suggested DataObject
> >union, it's helpful for us to provide meaningful metadata in the output.
> >but
Hi,
Andreas Färber a écrit :
Hi,
Am 05.11.2013 00:09, schrieb Hervé Poussineau:
Raven datasheet explains where firmware lives in system memory, so do
it there instead of in board code. Other boards using the same PCI
host will not have to copy the firmware loading code.
This part we had disc
Hi,
Andreas Färber a écrit :
Hi,
Am 05.11.2013 00:09, schrieb Hervé Poussineau:
Raven datasheet explains where firmware lives in system memory, so do
it there instead of in board code. Other boards using the same PCI
host will not have to copy the firmware loading code.
This part we had disc
Hi, Amos
(resend without big attachment)
Hello Eric, other
We had "command, enumeration, type, unionobj" in Eric suggested DataObject
union, it's helpful for us to provide meaningful metadata in the output.
but there still exists some problem.
We should describe some arbitrary data struct, I
于 2013/12/23 10:57, Wenchao Xia 写道:
于 2013/12/20 22:20, Stefan Hajnoczi 写道:
On Thu, Dec 05, 2013 at 08:02:50PM +0800, Wenchao Xia wrote:
+restore_refcount:
+if (qcow2_update_snapshot_refcount(bs, s->l1_table_offset,
s->l1_size, -1)
+< 0 && errp) {
+/* Nothing can be done now
Hi All,
I am relatively new to QEMU. I am using the latest version from git and I
am trying to add the necessary code to QEMU to perform a dynamic
instruction trace of guest code. My basic approach is to add a op call to
a function I have created with the parameters PC and opcode into the
disassm
On Sun, Dec 22, 2013 at 11:21:00PM +0100, Laszlo Ersek wrote:
> > 2. Use "IRQNoFlags() { 5 }" with the SMC (or any other
> >number that isn't already allocated.
>
> I don't think there's anything left free:
>...
>
> I guess the "by the book" solution would be to really stop the FDC fr
Very welcome! Thanks for the awesome software. It's allowed me to put my
SparcServer 5 out to pasture as a demonstration machine. Really, really hoping
that it supports the tcx with OBP at some point soon ... that'd be very cool.
I filed a separate bug report on that before realizing that it
-peter
On Dec 19, 2013, at 11:27 AM, Mark Cave-Ayland
wrote:
> On 19/12/13 12:59, Artyom Tarasenko wrote:
>
>> Hi Mark,
>>
>> this patch breaks booting with OBP:
>>
>> Probing /iommu@0,1000/sbus@0,10001000 at 5,0 espdma esp sd st
>> SUNW,bpp ledma le
>> Probing /iommu@0,1000/sbus@0
于 2013/12/20 22:20, Stefan Hajnoczi 写道:
On Thu, Dec 05, 2013 at 08:02:50PM +0800, Wenchao Xia wrote:
+restore_refcount:
+if (qcow2_update_snapshot_refcount(bs, s->l1_table_offset, s->l1_size, -1)
+< 0 && errp) {
+/* Nothing can be done now, need image check later */
+
The Figure 17 "SPR encodings" of the PowerISA 2.07 describes CTRL SPR as:
priviledged
# spr5-9 spr0-4 name mtspr mfspr len cat
136 00100 01000 CTRL -no32 S
152 00100 11000 CTRL yes-32 S
According to this chart, the hypervisor's CTRL (#152) does no
Hi QEMU/Libvirt list,
When I worked on query-command-line-options, I first used some marcos [1] to
generate two config & option tables. This will cover all the options,
but it returns a string, it's difficult for libvirt to parse and use
it.
Finally I got a suggestion to read info from new inter
On Fri, Dec 20, 2013 at 11:30:21AM +0100, Stefan Hajnoczi wrote:
> On Thu, Dec 19, 2013 at 10:27:35AM +0800, Hu Tao wrote:
> > This series implements full image preallocation to create a non-sparse image
> > file at creation time, both for raw and qcow2 format. The purpose is to
> > avoid
> > perf
On Fri, Dec 20, 2013 at 11:14:05AM +0100, Stefan Hajnoczi wrote:
> On Thu, Dec 19, 2013 at 10:27:38AM +0800, Hu Tao wrote:
> > +static int raw_preallocate2(int fd, int64_t offset, int64_t length)
> > +{
> > +int ret = -1;
> > +
> > +ret = fallocate(fd, 0, offset, length);
> > +
> > +/*
Hi,
Am 05.11.2013 00:09, schrieb Hervé Poussineau:
> Raven datasheet explains where firmware lives in system memory, so do
> it there instead of in board code. Other boards using the same PCI
> host will not have to copy the firmware loading code.
This part we had discussed and no one objected to
Am 05.11.2013 00:09, schrieb Hervé Poussineau:
> Hervé Poussineau (10):
> prep: kill get_system_io() usage
> raven: use constant PCI_NUM_PINS instead of 4
Thanks and sorry for the delay, I've applied these to prep-up:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/prep-up
(An interm
Implement an initial minimal set of EL0-visible system registers:
* NZCV
* FPCR
* FPSR
* CTR_EL0
* DCZID_EL0
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/cpu.h | 3 ++-
target-arm/helper.c| 61 ++
This patch support the basic load and store pair instructions and
includes the generic helper functions:
* do_gpr_st()
* do_fp_st()
* do_gpr_ld()
* do_fp_ld()
* read_cpu_reg_sp()
* gen_check_sp_alignment()
The last function gen_check_sp_alignment() is a NULL op currently but
put in pl
From: Alex Bennée
Implement the non-carry forms of addition and subtraction
(immediate, extended register and shifted register).
This includes the code to calculate NZCV if the instruction
calls for setting the flags.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard
Update the generic cpreg support code to also handle AArch64:
AArch64-visible registers coexist in the same hash table with
AArch32-visible ones, with a bit in the hash key distinguishing
them.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 74 +++---
tar
From: Claudio Fontana
this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 73 +-
1 file changed, 60 insertions(+),
The common pattern for system registers in a 64-bit capable ARM
CPU is that when in AArch32 the cp15 register is a view of the
bottom 32 bits of the 64-bit AArch64 system register; writes in
AArch32 leave the top half unchanged. The most natural way to
model this is to have the state field in the C
From: Alex Bennée
This adds support for the load/store forms using a register offset.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 144 -
1 file changed, 143 insertions(+),
From: Alexander Graf
Add decoding for the exception generating instructions, and implement
SVC (syscalls) and BRK (software breakpoint).
Signed-off-by: Alexander Graf
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 51 +
The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.
This is problematic for the A64 decoder, which doesn't pass the
environment pointer around everywhere the way the 32 bit decoder
does. Adjust the parameters these functi
In preparation for adding support for A64 load/store exclusive instructions,
widen the fields in the CPU state struct that deal with address and data values
for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
exclusive accesses will be generally separate there are some odd t
From: Michael Matz
This implement exclusive loads/stores for aarch64 along the lines of
arm32 and ppc implementations. The exclusive load remembers the address
and loaded value. The exclusive store throws an an exception which uses
those values to check for equality in a proper exclusive region.
From: Alexander Graf
This patch adds emulation for the "Data-processing (3 source)"
family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
UMADDL, UMSUBL, UMULH.
Signed-off-by: Alexander Graf
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
--
From: Alex Bennée
This patch adds emulation for the mov wide instructions
(MOVN, MOVZ, MOVK).
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 51 --
1 file changed, 49 insertio
From: Alex Bennée
Now the AArch64 targets are in mainline we can include them in our
Travis test matrix.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
---
.travis.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.travis.yml b/.travis.yml
index 90f1676..c7ff4da 100644
--- a/.t
From: Alex Bennée
This adds support for the forms of ld/st with a 12 bit
unsigned immediate offset.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 89 +-
1 file changed, 88 in
The AArch64 equivalent of the traditional AArch32
cp15 coprocessor registers is the set of instructions
MRS/MSR/SYS/SYSL, which cover between them both true
system registers and the "operations with side effects"
such as cache maintenance which in AArch32 are mixed
in with other cp15 registers. Imp
Add a top level decoder skeleton for FP instructions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 170 -
1 file changed, 169 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/targe
From: Claudio Fontana
The AArch64 linux-user support was written before but merged after
commit 4ce6243dc621 which cleaned up the handling of the clone()
syscall argument order, so we failed to notice that AArch64 also needs
TARGET_CLONE_BACKWARDS to be defined. Add this define so that clone
and
From: Alex Bennée
This adds support for the pre/post-index ld/st forms with immediate
offsets as well as the un-scaled immediate form (which are all
variations on the same 9-bit immediate instruction form).
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Implement FMOV, ie non-converting moves between general purpose
registers and floating point registers. This is a subtype of
the floating point <-> integer instruction class.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 86
Hi; this is the second version of a64-third-fourth-set, which
implements support for more or less all A64 instructions except
* FP [we support simple FP register load/store and
transfer to/from the general purpose registers]
* Neon
* system instructions (either ones only available to system
define_one_arm_cp_reg_with_opaque() has a set of nested loops which
insert a cpreg entry into the hashtable for each of the possible
opc/crn/crm values allowed by wildcard specifications. We're about
to add an extra loop to this nesting, so pull the core of the loop
(which adds a single entry to th
From: Will Newton
Use the helpers provided for getting the correct FPSR and FPCR
values for the signal context.
Signed-off-by: Will Newton
Signed-off-by: Peter Maydell
---
linux-user/signal.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/linux-user/signal.c b/
From: Claudio Fontana
This patch adds support for C3.5.3 Add/subtract (with carry):
instructions ADC, ADCS, SBC, SBCS.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 105 -
From: Alexander Graf
Adds support for Load Register (literal), both normal
and SIMD/FP forms.
Signed-off-by: Alexander Graf
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 47
Add a config for aarch64-linux-user, thereby enabling it as
a valid target.
Signed-off-by: Peter Maydell
Signed-off-by: Alexander Graf
Reviewed-by: Richard Henderson
---
default-configs/aarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 default-configs/aarch64-
On 12/22/13 18:14, Gabriel L. Somlo wrote:
> On Sun, Dec 22, 2013 at 04:58:58PM +0100, Laszlo Ersek wrote:
>> After this patch, ISA interrupt 6 is used by both "SMC" and "FDC0". The
>> latter depends on the FDEN object, but FDEN is currently constant 1.
>>
>> Probably not a problem in practice (ie.
On Sun, Dec 22, 2013 at 06:16:44PM +0100, Alexander Graf wrote:
>
> On 22.12.2013, at 17:37, Aurelien Jarno wrote:
>
> > On Fri, Dec 20, 2013 at 11:01:50AM +0100, Alexander Graf wrote:
> >> The recent VSX patches broken compilation of QEMU when configurated
> >> with --enable-debug, as it was tr
Hi,
Occasionally if I connect to monitor on unix socket and quickly
disconnect qemu process goes to 100% cpu usage until I connect to the
socket agian and actually read whatever there's, usually the qemu
welcome banner is printed twice, after the output is recieved qemu goes
back to not abusi
On Fri, Dec 20, 2013 at 03:00:12PM -0800, Richard Henderson wrote:
> As present on Atom and Haswell processors.
>
> Signed-off-by: Richard Henderson
> ---
> disas/i386.c | 8 ++--
> tcg/i386/tcg-target.c | 127
> ++
> 2 files changed, 9
Hi,
Looks like netdev bridge have no support for vhost=on switch. Would be
ince if that could be added.
-- Piotr.
On 22 December 2013 19:42, Stefan Weil wrote:
> cgcc reported a duplicate initialisation. Mainstone includes a matrix
> keyboard where two different positions map to 'space'.
>
> QEMU uses the reversed mapping and does not map 'space' to two different
> matrix positions.
>
> Some other keys are ei
On 20 December 2013 22:16, Peter Maydell wrote:
> More generally I think the way that AArch64 uses op1 to group
> the registers by exception-level-access-rights is going to make it
> a bit tricky to do the mapping; we either need to
> (1) have .opc1 be the AA32 opc1 and infer AA64 op1 from
> the p
cgcc reported a duplicate initialisation. Mainstone includes a matrix
keyboard where two different positions map to 'space'.
QEMU uses the reversed mapping and does not map 'space' to two different
matrix positions.
Some other keys are either missing or might be mapped wrongly (cf. Linux
kernel c
Hi,
I have the need to communicate efficiently between Windows 7 host and linux
guest. I tried first to use an IP socket communication using TAP driver on
Windows. Unfortunately, we reach a maximum of 4 Mbits/s where I would need
faster communication (more than 10 Mb/s). I don’t know yet if the
On 22 December 2013 19:01, Stefan Weil wrote:
>
> v2: Address Peter Maydell's suggestions:
> * Use first alternative, so there is no change of behaviour
No, I said that the compiler picked the last of the two, (5,3)
> [0x39] = {5,2}, /* space */
> -[0x39] = {5,3}, /* space */
> -
cgcc reported a duplicate initialisation. Mainstone includes a matrix
keyboard where two different positions map to 'space'.
QEMU uses the reversed mapping and does not map 'space' to two different
matrix positions.
Some other keys are either missing or might be mapped wrongly (cf. Linux
kernel c
On Sat, Dec 07, 2013 at 10:44:52AM +1300, Richard Henderson wrote:
> Don't duplicate the array length computation in the memset
> when plain sizeof can produce the correct results.
>
> Signed-off-by: Richard Henderson
> ---
> cputlb.c| 2 +-
> translate-all.c | 5 ++---
> 2 files changed
On Sat, Dec 07, 2013 at 10:44:51AM +1300, Richard Henderson wrote:
> The size of tlb_table is 4k on a 64-bit host. For overwriting
> memory at this size, cacheline tricks can help.
>
> Signed-off-by: Richard Henderson
> ---
> cputlb.c | 19 ++-
> 1 file changed, 2 insertions(+),
On Thu, Dec 19, 2013 at 10:00:18PM +, Peter Maydell wrote:
> We implement a number of float-to-integer conversions using conversion
> to an integer type with a wider range and then a check against the
> narrower range we are actually converting to. If we find the result to
> be out of range we
On 22.12.2013, at 17:37, Aurelien Jarno wrote:
> On Fri, Dec 20, 2013 at 11:01:50AM +0100, Alexander Graf wrote:
>> The recent VSX patches broken compilation of QEMU when configurated
>> with --enable-debug, as it was treating "target long" TCG variables
>> as "i64" which is not true for 32bit t
On Sun, Dec 22, 2013 at 04:58:58PM +0100, Laszlo Ersek wrote:
> After this patch, ISA interrupt 6 is used by both "SMC" and "FDC0". The
> latter depends on the FDEN object, but FDEN is currently constant 1.
>
> Probably not a problem in practice (ie. most users won't try to specify
> both a floppy
On 12/22/2013 03:32 AM, Aurelien Jarno wrote:
> find_first_bit has started to be used heavily in TCG code. The current
> implementation based on find_next_bit is not optimal and can't be
> optimized be the compiler if the bit array has a fixed size, which is
> the case most of the time.
>
> This n
On 12/21/2013 08:43 AM, Aurelien Jarno wrote:
> +/* If bit_MOVBE is defined in cpuid.h (added in GCC version 4.6), we are
> + going to attempt to determine at runtime whether movbe is available. */
> +#if defined(CONFIG_CPUID_H) && defined(bit_MOVBE)
> +static bool have_movbe;
> +#else
> +# defi
On 12/21/2013 08:43 AM, Aurelien Jarno wrote:
> +#define P_EXT2 0x200 /* 0x0f 0x38 opcode prefix */
I'm not keen on the name. It's not like the different extensions are numbered.
r~
On 12/21/2013 08:43 AM, Aurelien Jarno wrote:
> P_REXW is defined has a constant at the beginning of i386/tcg-target.c,
> but the corresponding bit is later used in a harcoded way, which defeat
> the purpose of a constant.
>
> Fix that by using a conditional expression operator instead of a shift.
On 12/21/2013 08:43 AM, Aurelien Jarno wrote:
> Signed-off-by: Aurelien Jarno
> ---
> disas/i386.c |8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/21/2013 08:43 AM, Aurelien Jarno wrote:
> TCG_TARGET_HAS_movcond_i32 is always defined to 1 in tcg-target.h, so
> remove the corresponding #ifdef #endif sequence, left from a previous
> refactoring.
>
> Signed-off-by: Aurelien Jarno
> ---
> tcg/i386/tcg-target.c |2 --
> 1 file changed
On 12/21/2013 01:08 PM, Peter Maydell wrote:
> If the input to float*_scalbn() is denormal then it represents
> a number 0.[mantissabits] * 2^(1-exponentbias) (and the actual
> exponent field is all zeroes). This means that when we convert
> it to our unpacked encoding the unpacked exponent must be
On 12/22/2013 04:24 AM, Aurelien Jarno wrote:
> On Sat, Dec 21, 2013 at 03:08:21PM +0100, Paolo Bonzini wrote:
>> Il 21/12/2013 00:00, Richard Henderson ha scritto:
>>> +if (real_bswap && have_movbe) {
>>> +tcg_out_modrm_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
>>> +
On Fri, Dec 20, 2013 at 11:01:50AM +0100, Alexander Graf wrote:
> The recent VSX patches broken compilation of QEMU when configurated
> with --enable-debug, as it was treating "target long" TCG variables
> as "i64" which is not true for 32bit targets.
>
> This patch fixes all the places that the c
On Sat, Dec 21, 2013 at 09:08:19PM +, Peter Maydell wrote:
> If the input to float*_scalbn() is denormal then it represents
> a number 0.[mantissabits] * 2^(1-exponentbias) (and the actual
> exponent field is all zeroes). This means that when we convert
> it to our unpacked encoding the unpacke
On 12/22/13 16:34, Gabriel L. Somlo wrote:
> AppleSMC (-device isa-applesmc) is required to boot OS X guests.
> OS X expects a SMC node to be present in the ACPI DSDT. This patch
> adds a SMC node to the DSDT, and dynamically patches the return value
> of SMC._STA to either 0x0B if the chip is pres
On 22 December 2013 14:11, Stefan Weil wrote:
> cgcc reported a duplicate initialisation. Mainstone includes a matrix
> keyboard where two different positions map to 'space'.
>
> QEMU uses the reversed mapping and cannot map 'space' to two different
> matrix positions.
>
> Signed-off-by: Stefan We
Signed-off-by: Hervé Poussineau
---
hw/dma/rc4030.c| 118 +---
hw/mips/mips_jazz.c| 37 +--
include/hw/mips/mips.h |4 +-
3 files changed, 115 insertions(+), 44 deletions(-)
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
Signed-off-by: Hervé Poussineau
---
hw/dma/rc4030.c | 112 ---
1 file changed, 16 insertions(+), 96 deletions(-)
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
index 97214de..432a4e4 100644
--- a/hw/dma/rc4030.c
+++ b/hw/dma/rc4030.c
@@ -120,
Remove also unneeded debug logs.
Signed-off-by: Hervé Poussineau
---
hw/dma/rc4030.c | 81 +++
trace-events|6 +
2 files changed, 22 insertions(+), 65 deletions(-)
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
index 09d235e..198
Now that rc4030 internally uses an AddressSpace for DMA handling, make it
public.
This is especially usefull for dp8393x netcard, which now uses well known QEMU
types and methods.
Signed-off-by: Hervé Poussineau
---
hw/dma/rc4030.c| 14 --
hw/mips/mips_jazz.c|8 +++
Remove now useless device models from other MIPS configurations
We're now compiling 18 files less than before.
Signed-off-by: Hervé Poussineau
---
default-configs/mips-softmmu.mak |5 -
default-configs/mips64-softmmu.mak |5 -
default-configs/mips64el-softmmu.mak |1 +
Register name is known, but its format is not known.
Signed-off-by: Hervé Poussineau
---
hw/dma/rc4030.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
index 432a4e4..09d235e 100644
--- a/hw/dma/rc4030.c
+++ b/hw/dma/rc403
Hi,
This patchset improves rc4030 chipset emulation to current QEMU
standards, ie QOM, tracing facilities, AddressSpace usage.
No behaviour change in emulation is expected.
Hervé
Hervé Poussineau (7):
mips jazz: compile only in 64 bit little endian
rc4030: create custom DMA address space
r
Keep it up to date by catching writes to DMA translation table.
Signed-off-by: Hervé Poussineau
---
hw/dma/rc4030.c | 153 ---
1 file changed, 113 insertions(+), 40 deletions(-)
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
index af26632..9b
AppleSMC (-device isa-applesmc) is required to boot OS X guests.
OS X expects a SMC node to be present in the ACPI DSDT. This patch
adds a SMC node to the DSDT, and dynamically patches the return value
of SMC._STA to either 0x0B if the chip is present, or otherwise to 0x00,
before booting the guest
On Fri, Dec 20, 2013 at 10:38:30PM +0100, Igor Mammedov wrote:
> > +Device (SMC) {
> > +Name(_HID, EisaId("APP0001"))
> > +/* _STA will be patched to 0x0B if AppleSMC is present */
> > +ACPI_EXTRACT_NAME_WORD_CONST CONCAT_SYM(SMC_PFX, smc_sta)
> typically dynamic variabl
On 22 December 2013 14:22, Stefan Weil wrote:
> The mapping is a hardware feature, so it is relatively constant.
This is true but not particularly relevant to whether we should be
marking the structs and parameters as 'const' or not. Still,
the change is good, so
Reviewed-by: Peter Maydell
tha
On 22 December 2013 14:32, Stefan Weil wrote:
> The row and column values use only a very limited range (-1 ... 7),
> so a byte value is sufficient.
>
> Signed-off-by: Stefan Weil
It's not like we have a ton of pxa2xx keymaps eating up
space, but yeah, this is an OK change.
Reviewed-by: Peter M
On 12/23/2013 01:46 AM, Alexey Kardashevskiy wrote:
> On 12/22/2013 09:56 PM, Michael S. Tsirkin wrote:
>> On Sun, Dec 22, 2013 at 02:01:23AM +1100, Alexey Kardashevskiy wrote:
>>> Hi!
>>>
>>> I am having a problem with virtio-net + vhost on POWER7 machine - it does
>>> not survive reboot of the gu
On Mon, 16 Dec 2013 21:53:07 +0200
"Michael S. Tsirkin" wrote:
> On Fri, Dec 13, 2013 at 05:22:14PM +0100, Igor Mammedov wrote:
> > .. and report range used by it to OSPM via _CRS.
> > PRST is needed in SSDT since its base will depend on
> > chipset and will be dynamically set by QEMU.
> > Also m
cgcc complains that -ENOSYS is not a good value for 'bool'.
A dummy virtio will never have pending queue entries, so let us return
false.
Signed-off-by: Stefan Weil
---
Could we also use g_assert_not_reached or hw_error in those dummy functions?
Regards
Stefan
hw/net/vhost_net.c |2 +-
1
On 12/22/2013 10:41 PM, Zhi Yong Wu wrote:
> On Sat, Dec 21, 2013 at 11:01 PM, Alexey Kardashevskiy wrote:
>> Hi!
> HI, Alexey
>
>>
>> I am having a problem with virtio-net + vhost on POWER7 machine - it does
>> not survive reboot of the guest.
> Can you let me login to your environment for debug
On 12/22/2013 09:56 PM, Michael S. Tsirkin wrote:
> On Sun, Dec 22, 2013 at 02:01:23AM +1100, Alexey Kardashevskiy wrote:
>> Hi!
>>
>> I am having a problem with virtio-net + vhost on POWER7 machine - it does
>> not survive reboot of the guest.
>>
>> Steps to reproduce:
>> 1. boot the guest
>> 2. c
The row and column values use only a very limited range (-1 ... 7),
so a byte value is sufficient.
Signed-off-by: Stefan Weil
---
include/hw/arm/pxa.h |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
index d146c58..7ca330a 100
On Sun, Dec 22, 2013 at 02:57:27PM +0100, Paolo Bonzini wrote:
> Linux prefers WRITE SAME to UNMAP if the limits are zero, and WRITE
> SAME does not discard anything unless the device can guarantee that
> the resulting block is zero.
>
> Setting the maximum unmap block and descriptor counts to non
The mapping is a hardware feature, so it is relatively constant.
Signed-off-by: Stefan Weil
---
hw/arm/mainstone.c |2 +-
hw/arm/z2.c |2 +-
hw/input/pxa2xx_keypad.c |6 +++---
include/hw/arm/pxa.h |4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
cgcc reported a duplicate initialisation. Mainstone includes a matrix
keyboard where two different positions map to 'space'.
QEMU uses the reversed mapping and cannot map 'space' to two different
matrix positions.
Signed-off-by: Stefan Weil
---
Of course we could also randomly select one of the
> Am 22.12.2013 um 12:31 schrieb "Michael S. Tsirkin" :
>
>> On Fri, Dec 20, 2013 at 11:31:17AM +0100, Alexander Graf wrote:
>>
>>> On 20.12.2013, at 10:42, Bharat Bhushan wrote:
>>>
>>> This patch adds pci pin to irq_num routing callback.
>>> This callback is called from pci_device_route_int
Linux prefers WRITE SAME to UNMAP if the limits are zero, and WRITE
SAME does not discard anything unless the device can guarantee that
the resulting block is zero.
Setting the maximum unmap block and descriptor counts to non-zero
makes Linux choose UNMAP and fixes thin provisioning on glusterfs.
From: Peter Lieven
this fixes a potential segfault and performance regression.
If the coroutine is reentered directly in the iscsi_co_generic_cb
iscsi_process_{read,write} are interrupted and reentered any
time later. One the one hand this could happen after an iscsi_close
where the iscsi contex
Anthony,
The following changes since commit e157b8fdd412d48eacfbb8c67d3d58780154faa3:
Merge remote-tracking branch 'bonzini/virtio' into staging (2013-12-13
11:10:33 -0800)
are available in the git repository at:
git://github.com/bonzini/qemu.git scsi-next
for you to fetch changes up to
Linux prefers WRITE SAME to UNMAP if the limits are zero, and WRITE
SAME does not discard anything unless the device can guarantee that
the resulting block is zero.
Setting the maximum unmap block and descriptor counts to non-zero
makes Linux choose UNMAP and fixes thin provisioning on glusterfs.
Il 21/12/2013 11:42, Markus Armbruster ha scritto:
> Suggest to add: ", killing migration."
Not good. But perhaps we can give a reason for this 2.0 thing.
It is certainly nice to schedule incompatible changes for obscure
machine types every 2 years.
> Which boards are affected? Should be liste
Il 22/12/2013 13:24, Aurelien Jarno ha scritto:
> On Sat, Dec 21, 2013 at 03:08:21PM +0100, Paolo Bonzini wrote:
>> Il 21/12/2013 00:00, Richard Henderson ha scritto:
>>> +if (real_bswap && have_movbe) {
>>> +tcg_out_modrm_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
>>> +
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