[Qemu-devel] [PATCH] kvm: fix traces to use %x instead of %d

KVM request types are normally defined using hex constants but QEMU traces print decimal values instead what is not very convinient. This changes the request type format from %d to %x. Signed-off-by: Alexey Kardashevskiy --- trace-events | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(

[Qemu-devel] [PATCH 1/4] tcg/optimize: fix know-zero bits optimization

Known-zero bits optimization is a great idea that helps to generate more optimized code. However the current implementation is basically useless as the computed mask is not saved. Fix this to make it really working. Cc: Richard Henderson Cc: Paolo Bonzini Signed-off-by: Aurelien Jarno --- tcg

[Qemu-devel] [PATCH 4/4] tcg/optimize: add known-zero bits compute for load ops

Cc: Richard Henderson Cc: Paolo Bonzini Signed-off-by: Aurelien Jarno --- tcg/optimize.c | 13 + 1 file changed, 13 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index b1f736b..044f456 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -787,6 +787,19 @@ static TCGAr

[Qemu-devel] [PATCH 3/4] tcg/optimize: improve known-zero bits for 32-bit ops

The shl_i32 op might set some bits of the unused 32 high bits of the mask. Fix that by clearing the unused 32 high bits for all 32-bit ops except load/store which operate on tl values. Cc: Richard Henderson Cc: Paolo Bonzini Signed-off-by: Aurelien Jarno --- tcg/optimize.c |6 ++ 1 fil

[Qemu-devel] [PATCH 2/4] tcg/optimize: fix known-zero bits for right shift ops

32-bit versions of sar and shr ops should not propagate known-zero bits from the unused 32 high bits. For sar it could even lead to wrong code being generated. Cc: Richard Henderson Cc: Paolo Bonzini Signed-off-by: Aurelien Jarno --- tcg/optimize.c | 21 + 1 file changed,

[Qemu-devel] [PATCH 0/4] tcg/optimize: fixes and improvements

This patchset first fixes known-zero bits optimization so that it is actually used, and does some further optimizations for 32-bit ops and unsigned loads. Aurelien Jarno (4): tcg/optimize: fix know-zero bits optimization tcg/optimize: fix known-zero bits for right shift ops tcg/optimize: imp

Re: [Qemu-devel] [PULL 00/29] Three tcg patch sets

On Mon, Sep 02, 2013 at 09:28:45AM -0700, Richard Henderson wrote: > > Aurelien has now reviewed three tcg related patch sets. This is a pull > request for all of them, fixing a trivial patch conflict in the process. > Done, thanks. -- Aurelien Jarno GPG: 1024D/F1BCD

Re: [Qemu-devel] [PULL 00/18] ppc patch queue 2013-09-02

On Mon, Sep 02, 2013 at 10:11:15AM +0200, Alexander Graf wrote: > Hi Blue / Aurelien / Anthony, > > This is my current patch queue for ppc. Please pull. > Done, thanks. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [Qemu-stable][PATCH] rdma: fix multiple VMs parallel migration

On 09/03/2013 12:20 PM, Frank Yang wrote: Yes, it depends on low-level implementation. During my earlier test, What do you mean by the 'it depends on low-level implementation'? Do you test it with IB or Ethernet? using one CQ to send and receive may cause packet loss with heavy load: the des

Re: [Qemu-devel] [Qemu-stable][PATCH] rdma: fix multiple VMs parallel migration

Hi Frank, I failed to apply this patch. Please make sure to use git-send-email, otherwise it's a little hard to review. :) On 08/30/2013 08:39 PM, Frank Yang wrote: When several VMs migrate with RDMA at the same time, the increased pressure cause packet loss probabilistically and make source an

Re: [Qemu-devel] [Qemu-stable][PATCH] rdma: fix multiple VMs parallel migration

Yes, it depends on low-level implementation. During my earlier test, using one CQ to send and receive may cause packet loss with heavy load: the destination thinks it send READY message successfully but the source still waits for it. This situation always happens when the destination polls receive

Re: [Qemu-devel] [libvirt] [PATCH 3/5] qemu: add usb-bot support from disks points of view

On 09/02/2013 08:57 PM, Daniel P. Berrange wrote: On Mon, Sep 02, 2013 at 05:38:42PM +0800, Guannan Ren wrote: usb-bot only supports 16 luns(0~15) and they must be contiguous, (using lun 0 and 2 without 1 doesn't work). In this case qemu doesn't throw an error, we can not find the lun 2 in guest

Re: [Qemu-devel] [PATCH V3 3/3] qemu-iotests: add tests for runtime fd passing via SCM rights

于 2013-9-2 22:51, Stefan Hajnoczi 写道: On Mon, Sep 02, 2013 at 05:18:13PM +0800, Wenchao Xia wrote: @@ -125,5 +125,39 @@ class TestFdSets(iotests.QMPTestCase): 'No file descriptor supplied via SCM_RIGHTS') self.vm.shutdown() +#Add fd at runtime, there are two ways: mo

Re: [Qemu-devel] [RFC] Streamlining endian handling in TCG

On Wed, Aug 28, 2013 at 08:26:43AM -0700, Richard Henderson wrote: > On 08/28/2013 07:34 AM, Peter Maydell wrote: > > On 28 August 2013 15:31, Richard Henderson wrote: > >> On 08/28/2013 01:15 AM, Peter Maydell wrote: > >>> [*] not impossible, we already do something on the ppc > >>> that's simila

Re: [Qemu-devel] [PATCH 3/3] prep: improve Raven PCI host emulation

On 2 September 2013 22:18, Hervé Poussineau wrote: > Yes, aliases should probably work, but it won't be handy to create lots of > them. Moreover, this function needs to be expanded later to handle an > additional endianness switch, which will change both addresses and values... FWIW, I think the

Re: [Qemu-devel] [PATCH 3/3] prep: improve Raven PCI host emulation

Peter Maydell a écrit : On 23 August 2013 19:52, Hervé Poussineau wrote: - let it load a firmware (raw or elf image) - add a GPIO to let it handle the non-contiguous I/O address space - provide a bus master address space Also move isa_mem_base from PCI host to machine board. Simplify pre

Re: [Qemu-devel] [PATCH 3/3] prep: improve Raven PCI host emulation

On 23 August 2013 19:52, Hervé Poussineau wrote: > - let it load a firmware (raw or elf image) > - add a GPIO to let it handle the non-contiguous I/O address space > - provide a bus master address space > Also move isa_mem_base from PCI host to machine board. > Simplify prep board code by relyi

Re: [Qemu-devel] [PATCH 3/3] prep: improve Raven PCI host emulation

On 2 September 2013 21:26, Hervé Poussineau wrote: > Richard Henderson a écrit : > >> On 08/23/2013 11:52 AM, Hervé Poussineau wrote: >>> >>> +uint8_t buf[4]; >>> +uint64_t val; >>> + >>> +if (s->contiguous_map == 0) { >>> +/* 64 KB contiguous space for IOs */ >>> +addr

Re: [Qemu-devel] [PATCH 3/3] prep: improve Raven PCI host emulation

Richard Henderson a écrit : On 08/23/2013 11:52 AM, Hervé Poussineau wrote: +uint8_t buf[4]; +uint64_t val; + +if (s->contiguous_map == 0) { +/* 64 KB contiguous space for IOs */ +addr &= 0x; +} else { +/* 8 MB non-contiguous space for IOs */ +

[Qemu-devel] [PATCH v3 10/29] tcg-aarch64: Handle constant operands to add, sub, and compare

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 101 --- 1 file changed, 79 insertions(+), 22 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 64c8d19..dbb1c45 100644 --- a/tcg/aarch64/tcg-target.c +++

[Qemu-devel] [PATCH v3 22/29] tcg-aarch64: Use adrp in tcg_out_movi

Loading an qemu pointer as an immediate happens often. E.g. - exit_tb $0x7fa8140013 + exit_tb $0x7f81ee0013 ... - : d2800260mov x0, #0x13 - : f2b50280movkx0, #0xa814, lsl #16 - : f2c00fe0movkx0, #0x7f, lsl #32 + : 90ff1000adrpx0, 0x7f81ee +

[Qemu-devel] [PATCH v3 09/29] tcg-aarch64: Implement mov with tcg_fmt_* functions

Avoid the magic numbers in the current implementation. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 23 ++- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index bd6f823..64c8d19 100644 ---

[Qemu-devel] [PATCHv7] add qemu-img convert -n option (skip target volume creation)

From: Alexandre Derumier Add a -n option to skip volume creation on qemu-img convert. This is useful for targets such as rbd / ceph, where the target volume may already exist; we cannot always rely on qemu-img convert to create the image, as dependent on the output format, there may be parameters

[Qemu-devel] [PATCH v3 18/29] tcg-aarch64: Support div, rem

For remainder, generic code will produce mul+sub, whereas we can implement with msub. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 50 +++- tcg/aarch64/tcg-target.h | 8 2 files changed, 45 insertions(+), 13 deletions(-) d

[Qemu-devel] [PATCH v3 25/29] tcg-aarch64: Use symbolic names for branches

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 48 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 42edf9e..385d97a 100644 --- a/tcg/aarch64/tcg-target.c +++

[Qemu-devel] [PATCH v3 02/29] tcg-aarch64: Change all ext variables to bool

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 44 ++-- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 5b067fe..bde4c72 100644 --- a/tcg/aarch64/tcg-target.c +++ b/t

[Qemu-devel] [PATCH v3 07/29] tcg-aarch64: Introduce tcg_fmt_* functions

Now that we've converted opcode fields to pre-shifted insns, we can merge the implementation of arithmetic and shift insns. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 78 +++- 1 file changed, 38 insertions(+), 40 deletions(-) diff

[Qemu-devel] [PATCH v3 12/29] tcg-aarch64: Support andc, orc, eqv, not

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 65 ++-- tcg/aarch64/tcg-target.h | 16 ++-- 2 files changed, 65 insertions(+), 16 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 9324185..eb08

Re: [Qemu-devel] [PATCHv6] add qemu-img convert -n option (skip target volume creation)

On 2 Sep 2013, at 16:28, Stefan Hajnoczi wrote: > If bdrv_getlength() failed and bdrv_get_geometry() produced a 0 result, > then this error message will be confusing to users. > > It would be better to use bdrv_getlength() directly: > > int64_t length = bdrv_getlength(out_bs); > if (length < 0)

[Qemu-devel] [PATCH v3 28/29] tcg-aarch64: Introduce tcg_out_ldst_pair

Combines 4 other inline functions and tidies the prologue. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 84 1 file changed, 27 insertions(+), 57 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c inde

[Qemu-devel] [PATCH v3 26/29] tcg-aarch64: Implement tcg_register_jit

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 93 1 file changed, 70 insertions(+), 23 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 385d97a..be51d97 100644 --- a/tcg/aarch64/tcg-target.c +++

[Qemu-devel] [PATCH v3 20/29] tcg-aarch64: Improve tcg_out_movi

Handle small positive and negative numbers early. Check for logical immediates. Check if using MOVN for the first set helps. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 61 +--- 1 file changed, 53 insertions(+), 8 deletions(-) di

[Qemu-devel] [PATCH v3 19/29] tcg-aarch64: Introduce tcg_fmt_Rd_uimm_s

Cleaning up the implementation of tcg_out_movi at the same time. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 48 ++-- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.

[Qemu-devel] [PATCH v3 23/29] tcg-aarch64: Pass return address to load/store helpers directly.

Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 18 -- tcg/aarch64/tcg-target.c | 44 ++-- 2 files changed, 26 insertions(+), 36 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 7510246..9a3e

[Qemu-devel] [PATCH v3 29/29] tcg-aarch64: Remove redundant CPU_TLB_ENTRY_BITS check

Removed from other targets in 56bbc2f967ce185fa1c5c39e1aeb5b68b26242e9. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 3a68821..1bf609c 100644 --- a/tcg/aarch64/tcg-t

[Qemu-devel] [PATCH v3 15/29] tcg-aarch64: Support deposit

Also tidy the implementation of ubfm, sbfm, extr in order to share code. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 47 ++- tcg/aarch64/tcg-target.h | 4 ++-- 2 files changed, 36 insertions(+), 15 deletions(-) diff --git a/tcg/aa

[Qemu-devel] [PATCH v3 17/29] tcg-aarch64: Support muluh, mulsh

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 12 tcg/aarch64/tcg-target.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 0587765..5ab0596 100644 --- a/tcg/aarch64/tcg-target.c +++

[Qemu-devel] [PATCH v3 27/29] tcg-aarch64: Reuse FP and LR in translated code

We don't need the FP within translated code, and the LR is otherwise unused. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 36 +++- tcg/aarch64/tcg-target.h | 32 +--- 2 files changed, 32 insertions(+), 36 deletions(-)

[Qemu-devel] [PATCH v3 14/29] tcg-aarch64: Support movcond

Also tidy the implementation of setcond in order to share code. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 33 + tcg/aarch64/tcg-target.h | 4 ++-- 2 files changed, 27 insertions(+), 10 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tc

[Qemu-devel] [PATCH v3 11/29] tcg-aarch64: Handle constant operands to and, or, xor

Handle a simplified set of logical immediates for the moment. The way gcc and binutils do it, with 52k worth of tables, and a binary search depth of log2(5334) = 13, seems slow for the most common cases. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 148 +++

[Qemu-devel] [PATCH v3 16/29] tcg-aarch64: Support add2, sub2

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 78 tcg/aarch64/tcg-target.h | 8 ++--- 2 files changed, 82 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 0dc3fee..0587765 1006

[Qemu-devel] [PATCH v3 24/29] tcg-aarch64: Use tcg_out_call for qemu_ld/st

In some cases, a direct branch will be in range. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 1d0db02..42edf9e 100644 --- a/tcg/aarch64/tcg-targe

[Qemu-devel] [PATCH v3 13/29] tcg-aarch64: Handle zero as first argument to sub

In order to properly handle neg, as generated by TCG generic code. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 28 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index eb080ed..ea

[Qemu-devel] [PATCH v3 08/29] tcg-aarch64: Introduce tcg_fmt_Rdn_aimm

This merges the implementation of tcg_out_addi and tcg_out_subi. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 75 +--- 1 file changed, 27 insertions(+), 48 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.

[Qemu-devel] [PATCH v3 21/29] tcg-aarch64: Avoid add with zero in tlb load

Some guest env are small enough to reach the tlb with only a 12-bit addition. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 22 +- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 54f5ce

[Qemu-devel] [PATCH v3 03/29] tcg-aarch64: Don't handle mov/movi in tcg_out_op

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index bde4c72..79a447d 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @

[Qemu-devel] [PATCH v3 04/29] tcg-aarch64: Hoist common argument loads in tcg_out_op

This reduces the code size of the function significantly. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 95 +--- 1 file changed, 50 insertions(+), 45 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index

[Qemu-devel] [PATCH v3 06/29] tcg-aarch64: Merge enum aarch64_srr_opc with AArch64Insn

And since we're no longer talking about opcodes, merge the 0x1ac02000 data2 primary opcode with the shift subcode to create the full insn. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 49 1 file changed, 24 insertions(+), 25 del

[Qemu-devel] [PATCH v3 05/29] tcg-aarch64: Change enum aarch64_arith_opc to AArch64Insn

And since we're no longer talking about opcodes, change the values to be shifted into the opcode field, avoiding a shift at runtime. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 43 +++ 1 file changed, 23 insertions(+), 20 deletions(-)

[Qemu-devel] [PATCH v3 00/29] tcg-aarch64 improvements

I'm not sure if I posted v2 or not, but my branch is named -3, therefore this is v3. ;-) The jumbo "fixme" patch from v1 has been split up. This has been updated for the changes in the tlb helpers over the past few weeks. For the benefit of trivial conflict resolution, it's relative to a tree th

[Qemu-devel] [PATCH v3 01/29] tcg-aarch64: Set ext based on TCG_OPF_64BIT

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 28 +++- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 55ff700..5b067fe 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-ta

[Qemu-devel] [PATCH v3 00/29] tcg-aarch64 improvements

I'm not sure if I posted v2 or not, but my branch is named -3, therefore this is v3. ;-) The jumbo "fixme" patch from v1 has been split up. This has been updated for the changes in the tlb helpers over the past few weeks. For the benefit of trivial conflict resolution, it's relative to a tree th

[Qemu-devel] [PULL 03/29] tcg-ppc64: Implement muluh, mulsh

Using these instead of mulu2 and muls2 lets us avoid having to argument overlap analysis in the backend. Normal register allocation will DTRT. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 32 +++- tcg/ppc64/tcg-target.h |

[Qemu-devel] [PULL 14/29] tcg: Change relocation offsets to intptr_t

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 2 +- tcg/arm/tcg-target.c | 8 tcg/hppa/tcg-target.c| 6 +++--- tcg/i386/tcg-target.c| 2 +- tcg/ia64/tcg-target.c| 14 +++--- tcg/mips/tcg-target.c| 16 -

[Qemu-devel] [PULL 13/29] tcg: Change memory offsets to intptr_t

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/tcg.c | 16 +--- tcg/tcg.h | 8 +++- 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 240e6f4..251d390 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -389,7 +389,7 @@ TCGv_

Re: [Qemu-devel] [PATCH v3 0/2] Fix unassigned memory and I/O access handling

On 2 September 2013 17:43, Jan Kiszka wrote: > Repost of what missed the 1.6 release. > > Jan Kiszka (2): > memory: Provide separate handling of unassigned io ports accesses > Revert "memory: Return -1 again on reads from unsigned regions" Reviewed-by: Peter Maydell This fixes booting of in

[Qemu-devel] [PULL 23/29] exec: Reorganize the GETRA/GETPC macros

Always define GETRA; use __builtin_extract_return_addr, rather than having a special case for s390. Split GETPC_ADJ out of GETPC; use 2 universally, rather than having a special case for arm. Rename GETPC_LDST to GETRA_LDST to indicate that it does not contain the GETPC_ADJ value. Likewise with

Re: [Qemu-devel] [PATCH V3] target-i386: forward CPUID cache leaves when -cpu host is used

> > > > Signed-off-by: Benoit Canet > > Reviewed-by: Eduardo Habkost Thanks. Do you have an idea on how QEMU could reflect the real host clock frequency to the guest when the host cpu scaling governor kicks in ? Giving a false value to cloud customers is mildly annoying. Best regards Benoît

Re: [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets

On 2 September 2013 17:44, Peter Maydell wrote: > On 1 July 2013 18:35, Peter Maydell wrote: >> From: Alexander Graf >> >> Add the necessary code to configure to handle AArch64 as a target >> CPU (we already have some code for supporting it as host). Note >> that this doesn't enable the AArch64

[Qemu-devel] [PULL 16/29] tcg: Change tcg_gen_exit_tb argument to uintptr_t

And update all users. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 4 ++-- target-alpha/translate.c | 8 target-arm/translate.c| 2 +- target-cris/translate.c | 2 +- target-i386/translate.c | 2 +- target-lm3

[Qemu-devel] Academic Project

Hello, We are looking for projects to work on based on QEMU. These maybe research projects that developers had in their mind, but couldn't find the time to implement or GSoC projects that didn't get selected or haven't been worked on. *Details* Number of People : 4 Duration(actual) : February 20

Re: [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets

On 1 July 2013 18:35, Peter Maydell wrote: > From: Alexander Graf > > Add the necessary code to configure to handle AArch64 as a target > CPU (we already have some code for supporting it as host). Note > that this doesn't enable the AArch64 targets yet. > + aarch64) > +TARGET_BASE_ARCH=arm >

[Qemu-devel] [PATCH v3 0/2] Fix unassigned memory and I/O access handling

Repost of what missed the 1.6 release. Jan Kiszka (2): memory: Provide separate handling of unassigned io ports accesses Revert "memory: Return -1 again on reads from unsigned regions" exec.c| 3 ++- include/exec/ioport.h | 4 ioport.c | 16 +++

[Qemu-devel] [PATCH v3 2/2] Revert "memory: Return -1 again on reads from unsigned regions"

This reverts commit 9b8c69243585a32d14b9bb9fcd52c37b0b5a1b71. The commit was wrong: We only return -1 on invalid accesses, not on valid but unbacked ones. This broke various corner cases. Signed-off-by: Jan Kiszka --- memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/

[Qemu-devel] [PATCH v3 1/2] memory: Provide separate handling of unassigned io ports accesses

Accesses to unassigned io ports shall return -1 on read and be ignored on write. Ensure these properties via dedicated ops, decoupling us from the memory core's handling of unassigned accesses. Signed-off-by: Jan Kiszka --- exec.c| 3 ++- include/exec/ioport.h | 4 ioport.

[Qemu-devel] [PULL 29/29] tcg-i386: Make use of zero-extended memory helper routines

For 8 and 16-bit unsigned loads, rely on the zero-extension from the helper and use a smaller 32-bit move insn. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/tcg/i386/tcg

[Qemu-devel] [PULL 28/29] tcg: Introduce zero and sign-extended versions of load helpers

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- include/exec/softmmu_template.h | 58 - tcg/i386/tcg-target.c | 6 ++--- tcg/tcg.h | 21 ++- 3 files changed, 64 insertions(+), 21 deletions(-) d

[Qemu-devel] [PULL 27/29] exec: Split softmmu_defs.h

The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- inc

[Qemu-devel] [PULL 21/29] tcg-i386: Adjust tcg_out_tlb_load for x32

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 41 +++-- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 247c9d2..cde134f 100644 --- a/tcg/i386/tcg-ta

[Qemu-devel] [PULL 25/29] exec: Rename USUFFIX to LSUFFIX

In a following patch, there will be confusion between multiple "unsigned" suffixes; rename this one so as to imply "load". Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- include/exec/softmmu_template.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --

[Qemu-devel] [PULL 20/29] tcg-i386: Use intptr_t appropriately

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 41 +++-- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 70e80f9..247c9d2 100644 --- a/tcg/i386/tcg-ta

[Qemu-devel] [PULL 22/29] configure: Allow x32 as a host

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- configure | 27 ++- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/configure b/configure index 0a55c20..af6b048 100755 --- a/configure +++ b/configure @@ -362,7 +362,11 @@ if test ! -z "$cpu"

[Qemu-devel] [PULL 19/29] tcg: Fix jit debug for x32

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/tcg.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 99f3b2c..fd7fb6b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -49,10 +49,10 @@ #include "tcg-op.h" -#if TCG_TARG

[Qemu-devel] [PULL 24/29] tcg-i386: Don't perform GETPC adjustment in TCG code

Since we now perform it inside the helper, no need to do it here. This also lets us perform a tail-call from the store slow path to the helper. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 33 ++--- 1 file changed, 14 inser

[Qemu-devel] [PULL 18/29] tcg: Use appropriate types in tcg_reg_alloc_call

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 7ba9208..99f3b2c 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2070,7 +2070,9 @@ static int tcg_reg_alloc_call(TCGContext *s,

[Qemu-devel] [PULL 17/29] tcg: Change tcg_out_ld/st offset to intptr_t

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 4 ++-- tcg/arm/tcg-target.c | 4 ++-- tcg/hppa/tcg-target.c| 4 ++-- tcg/i386/tcg-target.c| 4 ++-- tcg/ia64/tcg-target.c| 4 ++-- tcg/mips/tcg-target.c| 4 ++-- tcg/ppc/tcg-target.c

[Qemu-devel] [PULL 12/29] tcg: Change frame pointer offsets to intptr_t

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/tcg.c | 5 ++--- tcg/tcg.h | 9 - 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 65cffca..240e6f4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -306,8 +306,7 @@ void tcg_prologue_

[Qemu-devel] [PULL 26/29] target: Include softmmu_exec.h where forgotten

Several targets forgot to include softmmu_exec.h, which would break them with a header cleanup to follow. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target-lm32/op_helper.c | 2 ++ target-moxie/helper.c| 1 + target-ppc/mmu_helper.c | 2 ++ target-unicore

[Qemu-devel] [PULL 09/29] tcg: Allow TCG_TARGET_REG_BITS to be specified independantly

There are several hosts for which it would be useful to use the available 64-bit registers in a 32-bit pointer environment. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/hppa/tcg-target.c | 4 tcg/hppa/tcg-target.h | 4 tcg/i386/tcg-target.h | 10 ++

[Qemu-devel] [PULL 10/29] tcg: Define TCG_TYPE_PTR properly

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/tcg.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 8a5e55b..7a6f2e5 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -178,9 +178,12 @@ typedef enum TCGType { TCG_TYPE_RE

[Qemu-devel] [PULL 15/29] tcg: Use uintptr_t in TCGHelperInfo

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/tcg.c | 6 +++--- tcg/tcg.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 75df845..714b0c7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -634,7 +634,7 @@ void tcg_register_helper

[Qemu-devel] [PULL 11/29] tcg: Define TCG_ptr properly

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/tcg.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 7a6f2e5..bb215a7 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -645,11 +645,11 @@ do {\ void tcg_add_target_add_op_defs(

[Qemu-devel] [PULL 07/29] tcg: Change tcg_qemu_tb_exec return to uintptr_t

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- cpu-exec.c | 2 +- tcg/ppc/tcg-target.h | 2 +- tcg/tcg.h| 3 +-- tcg/tci/tcg-target.h | 2 +- tci.c| 4 ++-- 5 files changed, 6 insertions(+), 7 deletions(-) diff --git a/cpu-exec.c b/cpu-exe

[Qemu-devel] [PULL 06/29] tcg: Change flush_icache_range arguments to uintptr_t

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 3 +-- tcg/arm/tcg-target.h | 9 - tcg/hppa/tcg-target.h| 3 +-- tcg/i386/tcg-target.h| 3 +-- tcg/ia64/tcg-target.h| 3 +-- tcg/mips/tcg-target.h| 3 +-- tcg/s390/tcg-ta

[Qemu-devel] [PULL 08/29] tcg: Fix next_tb type in cpu_exec

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- cpu-exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu-exec.c b/cpu-exec.c index 14af2ed..5a43995 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -209,7 +209,7 @@ int cpu_exec(CPUArchState *env) int ret

[Qemu-devel] [PULL 04/29] tcg: Constant fold div, rem

Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/optimize.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index e8dedf3..b29bf25 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -304,6 +304,25 @@ static TCGArg

[Qemu-devel] [PULL 05/29] qtest: Fix FMT_timeval vs time_t

Since FMT_timeval unconditionally uses %ld for both tv_sec and tv_usec, and already casts tv_usec to long, also cast tv_sec to long. Cc: Andreas Färber Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- qtest.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff -

[Qemu-devel] [PULL 02/29] tcg-mips: Implement mulsh, muluh

With the optimization in tcg_liveness_analysis, we can avoid the MFLO when it is unused. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 10 ++ tcg/mips/tcg-target.h | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/tcg/m

[Qemu-devel] [PULL 01/29] tcg: Add muluh and mulsh opcodes

Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 4 tcg/arm/tcg-target.h | 2 ++ tcg/hppa/tcg-target.h| 2 ++ tcg/i386/tcg-target.h| 4 +

[Qemu-devel] [PULL 00/29] Three tcg patch sets

Aurelien has now reviewed three tcg related patch sets. This is a pull request for all of them, fixing a trivial patch conflict in the process. r~ The following changes since commit 4ff78e0dbcd5c795962567fdc1b31e9e03c55b07: Merge remote-tracking branch 'luiz/queue/qmp' into staging (2013-0

Re: [Qemu-devel] [PATCH V3] target-i386: forward CPUID cache leaves when -cpu host is used

On Mon, Sep 02, 2013 at 05:06:37PM +0200, Benoît Canet wrote: > Some users running cpu intensive tasks checking the cache CPUID leaves at > startup and making decisions based on the result reported that the guest was > not reflecting the host CPUID leaves when -cpu host is used. > > This patch fix

Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses

On Mon, Sep 02, 2013 at 05:05:10PM +0100, Peter Maydell wrote: > On 2 September 2013 17:00, Michael S. Tsirkin wrote: > > On Mon, Sep 02, 2013 at 04:53:50PM +0100, Peter Maydell wrote: > >> at the moment what happens is that the pci controller > >> creates the PCI memory and io memory regions (or

Re: [Qemu-devel] [RFC] TCG unit testing

On Fri, Aug 23, 2013 at 12:47:43PM -0700, Richard Henderson wrote: > I've been thinking for a while about how to reliably test TCG backends, and > maybe how to do regression testing on them. Having to begin the test from a > guest binary, especially considering the vast cross-compilation problem,

Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses

On 2 September 2013 17:00, Michael S. Tsirkin wrote: > On Mon, Sep 02, 2013 at 04:53:50PM +0100, Peter Maydell wrote: >> at the moment what happens is that the pci controller >> creates the PCI memory and io memory regions (or cheats >> by reusing the system memory space[*]), >> [*] I'm pretty su

Re: [Qemu-devel] [PATCH V11 1/5] throttle: Add a new throttling API implementing continuous leaky bucket.

> However, I think this is not what the code is doing right now, isn't it? Hi Paolo, I changed the code so it trigger only if the request size is bigger than op_size. Best regards Benoît

Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses

On Mon, 2013-09-02 at 16:53 +0100, Peter Maydell wrote: > On 2 September 2013 16:42, Marcel Apfelbaum wrote: > > On Mon, 2013-09-02 at 15:39 +0100, Peter Maydell wrote: > >> This is happening at the wrong layer -- you want this memory > >> region to be created and managed in the PCI core code so t

Re: [Qemu-devel] [PATCH v2 for 1.6 1/2] memory: Provide separate handling of unassigned io ports accesses

On 2013-09-02 17:58, Andreas Färber wrote: > Am 02.09.2013 17:56, schrieb Jan Kiszka: >> On 2013-09-02 15:52, Peter Maydell wrote: >>> On 12 August 2013 16:39, Andreas Färber wrote: Am 12.08.2013 17:29, schrieb Jan Kiszka: > Accesses to unassigned io ports shall return -1 on read and be i

Re: [Qemu-devel] [PATCH v2 for 1.6 1/2] memory: Provide separate handling of unassigned io ports accesses

Am 02.09.2013 17:56, schrieb Jan Kiszka: > On 2013-09-02 15:52, Peter Maydell wrote: >> On 12 August 2013 16:39, Andreas Färber wrote: >>> Am 12.08.2013 17:29, schrieb Jan Kiszka: Accesses to unassigned io ports shall return -1 on read and be ignored on write. Ensure these properties via

Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses

On 2 September 2013 16:53, Peter Maydell wrote: > On 2 September 2013 16:42, Marcel Apfelbaum wrote: >> Question, why are not pci_address_space and pci_hole present >> in a core layer? >> >> I followed the existing code; from what you are saying >> I understand that also the existing memory regio

Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses

On Mon, Sep 02, 2013 at 04:53:50PM +0100, Peter Maydell wrote: > On 2 September 2013 16:42, Marcel Apfelbaum wrote: > > On Mon, 2013-09-02 at 15:39 +0100, Peter Maydell wrote: > >> This is happening at the wrong layer -- you want this memory > >> region to be created and managed in the PCI core co

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