Right.
I don't see any problem with your patch.
On Sat, Jul 6, 2013 at 3:15 PM, Peter Lieven wrote:
> ok, to sum up you see no potential problem with my patch to optimize write
> zeroes by
> unmap iff lbprz==1 and lbpme == 1 ?
ACK
>
> the alternative would be to use writesame16 and sent a z
On Sun, Jul 7, 2013 at 12:19 AM, Andreas Färber wrote:
> Am 29.06.2013 22:01, schrieb Andreas Färber:
>> Since all targets now assign a softmmu-only field, we can drop helpers
>> cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd().
>>
>> Prepares for changing cpu_memory_rw_debu
ok, to sum up you see no potential problem with my patch to optimize write
zeroes by
unmap iff lbprz==1 and lbpme == 1 ?
the alternative would be to use writesame16 and sent a zero block. this would
allow
an optimization also if lbprz == 0. in this case i would not set the unmap bit.
peter
Am
OpenRISC uses the asm-generic versions of target_stat and
target_stat64, but it was incorrectly using the x86/ARM/etc version
due to a misplaced defined(TARGET_OPENRISC). The previously unused
OpenRISC section of the ifdef ladder also defined an incorrect
target_stat and omitted the target_stat64
Am 29.06.2013 22:01, schrieb Andreas Färber:
> Since all targets now assign a softmmu-only field, we can drop helpers
> cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd().
>
> Prepares for changing cpu_memory_rw_debug() argument to CPUState.
>
> Signed-off-by: Andreas Färber
On Sat, Jul 6, 2013 at 11:12 PM, Andreas Färber wrote:
> Am 06.07.2013 20:39, schrieb Max Filippov:
>> On Sat, Jul 6, 2013 at 10:01 PM, Max Filippov wrote:
>>> On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber wrote:
Am 29.06.2013 22:01, schrieb Andreas Färber:
> Register a CPU type per co
Am 06.07.2013 20:01, schrieb Max Filippov:
> On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber wrote:
>> Max,
>>
>> Am 29.06.2013 22:01, schrieb Andreas Färber:
>>> Register a CPU type per core registered. Save the XtensaConfig in
>>> XtensaCPUClass instead of CPUXtensaState.
>>>
>>> Prepares for sto
On Sat, Jul 6, 2013 at 10:45 PM, Andreas Färber wrote:
> Hi Max,
>
> Am 06.07.2013 20:01, schrieb Max Filippov:
>> On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber wrote:
>>> Am 29.06.2013 22:01, schrieb Andreas Färber:
Register a CPU type per core registered. Save the XtensaConfig in
Xte
From: Andreas Färber
Signed-off-by: Andreas Färber
Signed-off-by: Max Filippov
---
configure | 5 +++--
tests/tcg/xtensa/Makefile | 20 +++-
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/configure b/configure
index 0e0adde..7b60efd 100755
---
Am 01.07.2013 20:07, schrieb Richard Henderson:
> On 06/29/2013 01:01 PM, Andreas Färber wrote:
>> Replace GET_REG*() macros by gdb_get_reg*() inline functions for
>> clarity and drop breaks after return.
>>
>> Allows to move target-specific code to new target-*/gdbstub.c files.
>>
>> Signed-off-by
Am 06.07.2013 20:39, schrieb Max Filippov:
> On Sat, Jul 6, 2013 at 10:01 PM, Max Filippov wrote:
>> On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber wrote:
>>> Am 29.06.2013 22:01, schrieb Andreas Färber:
Register a CPU type per core registered. Save the XtensaConfig in
XtensaCPUClass in
Hi Max,
Am 06.07.2013 20:01, schrieb Max Filippov:
> On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber wrote:
>> Am 29.06.2013 22:01, schrieb Andreas Färber:
>>> Register a CPU type per core registered. Save the XtensaConfig in
>>> XtensaCPUClass instead of CPUXtensaState.
>>>
>>> Prepares for stori
Signed-off-by: Andreas Färber
---
configure | 5 +++--
tests/tcg/xtensa/Makefile | 8
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/configure b/configure
index 0e0adde..7b60efd 100755
--- a/configure
+++ b/configure
@@ -4469,13 +4469,14 @@ if [ "$dtc_inte
On Sat, Jul 6, 2013 at 10:01 PM, Max Filippov wrote:
> On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber wrote:
>> Max,
>>
>> Am 29.06.2013 22:01, schrieb Andreas Färber:
>>> Register a CPU type per core registered. Save the XtensaConfig in
>>> XtensaCPUClass instead of CPUXtensaState.
>>>
>>> Prepa
I'd like to test some changes I'm making which affect the
qemu linux-m68k target, but I can't find a working set of binaries
to test them with. Everything I've found online (including the
ones in the linux-user test tarball on the qemu wiki) just dies
pretty quickly with an illegal instruction (pos
Add timed bottom halves. A timed bottom half is a bottom half that
will not execute until a given time has passed (qemu_bh_schedule_at)
or a given interval has passed (qemu_bh_schedule_in). Any qemu
clock can be used, and times are specified in nanoseconds.
Timed bottom halves can be used where ti
On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber wrote:
> Max,
>
> Am 29.06.2013 22:01, schrieb Andreas Färber:
>> Register a CPU type per core registered. Save the XtensaConfig in
>> XtensaCPUClass instead of CPUXtensaState.
>>
>> Prepares for storing per-class GDB register count.
>>
>> Signed-off-
SPARC is one of the CPUs which has a funny syscall ABI for the
pipe syscall; add it to the set of special cases in do_pipe().
Signed-off-by: Peter Maydell
---
bash is much more useful with this patch -- without it, it will
close() stdin instead of one end of its pipe to a child process,
so after
--On 6 July 2013 17:24:57 +0100 Alex Bligh wrote:
Add timed bottom halves. A timed bottom half is a bottom half that
will not execute until a given time has passed (qemu_bh_schedule_at)
or a given interval has passed (qemu_bh_schedule_in). Any qemu
clock can be used, and times are specified in
Add timed bottom halves. A timed bottom half is a bottom half that
will not execute until a given time has passed (qemu_bh_schedule_at)
or a given interval has passed (qemu_bh_schedule_in). Any qemu
clock can be used, and times are specified in nanoseconds.
Timed bottom halves can be used where ti
Am 01.07.2013 00:13, schrieb Peter Maydell:
> On 30 June 2013 22:00, Andreas Färber wrote:
>> From: Andreas Färber
>>
>> Prepares for conversion to QOM realize.
>>
>> Signed-off-by: Andreas Färber
>> ---
>> hw/cpu/a9mpcore.c | 25 -
>> 1 file changed, 16 insertions(+), 9
From: David Gibson
This patch adds the necessary VMStateDescription information to support
savevm/loadvm for the spapr_tty (PAPR logical serial) device.
Signed-off-by: David Gibson
Signed-off-by: Alexey Kardashevskiy
---
hw/char/spapr_vty.c | 16
1 file changed, 16 insertions
The specific of sPAPR platform is that the guest allocates MSI/MSIX
vectors via RTAS hypercalls and only operates with global IRQ numbers.
In the real hardware, PHB is expected to convert MSIMessage to an IRQ
number. So it is up to the host kernel to setup correct MSIMessage in
a real device and a
From: Prerna Saxena
In absence of a -CPU parameter in the qemu command line, the nodes of
KVM-enabled guest device tree look like this :
/proc/device-tree/cpus/HOST@0/...
/proc/device-tree/cpus/HOST@4/...
This patch replaces this obscure 'HOST' label with a more descriptive label.
This is gathe
From: Prerna Saxena
This patch adds CPU PVR definition for POWER8,
and enables QEMU to launch guests on POWER8 hardware.
Signed-off-by: Prerna Saxena
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Paul Mackerras
Reviewed-by: Andreas Farber
---
Changes:
2013/07/04:
* version 0.1 fixed to 1
From: David Gibson
This adds the necessary support for saving the state of the PAPR virtual
PCI host bridge (or host bridges).
Signed-off-by: David Gibson
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr_pci.c | 49 +
include/hw/pci-hos
From: David Gibson
At present, the savevm / migration support for the pseries machine will not
work when KVM is enabled. That's because KVM manages the guest's hash page
table in the host kernel, so qemu has no visibility of it. This patch
fixes this by using new kernel interfaces to extract an
From: David Gibson
Recent PowerKVM allows the kernel to intercept some RTAS calls from the
guest directly. This is used to implement the more efficient in-kernel
XICS for example. qemu is still responsible for assigning the RTAS token
numbers however, and needs to tell the kernel which RTAS fun
From: David Gibson
This adds the necessary pieces to implement savevm / migration for the
pseries machine. The most complex part here is migrating the hash
table - for the paravirtualized pseries machine the guest's hash page
table is not stored within guest memory, but externally and the guest
From: David Gibson
This patch adds the necessary support for saving the state of the PAPR VIO
virtual SCSI device. This also saves and restores active SCSI requests.
[aik: implemented vscsi_req save/restore]
Signed-off-by: Alexey Kardashevskiy
Cc: David Gibson
Signed-off-by: Alexey Kardashevs
From: David Gibson
This patch adds the necessary VMStateDescription information to support
savevm/loadvm for the spapr_llan (PAPR logical lan) device.
Signed-off-by: David Gibson
Signed-off-by: Alexey Kardashevskiy
---
hw/net/spapr_llan.c | 24 ++--
1 file changed, 22 inse
From: David Gibson
The vmstate infrastructure includes a VMS_MULTIPY flag, and associated
VMSTATE_VBUFFER_MULTIPLY helper macro. These can be used to save a
variably sized buffer where the size in bytes of the buffer isn't directly
accessible as a structure field, but an element count from which
The patch reimplements handling of indirect requests in order to
simplify upcoming live migration support.
- all pointers (except SCSIRequest*) were replaces with integer
indexes and offsets;
- DMA'ed srp_direct_buf kept untouched (ie. BE format);
- vscsi_fetch_desc() is added, now it is the only p
From: David Gibson
This patch adds the necessary VMStateDescription information to save the
state of PAPR TCE tables (that is, the PAPR specified IOMMU).
Signed-off-by: David Gibson
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr_iommu.c | 25 +
1 file changed, 25
From: David Gibson
Recent (host) kernels support emulating the PAPR defined "XICS" interrupt
controller system within KVM. This patch allows qemu to initialize and
configure the in-kernel XICS, and keep its state in sync with qemu's XICS
state as necessary.
This should give considerable perform
From: David Gibson
This patch adds the necessary VMStateDescription information to support
savevm/loadvm for the XICS interrupt controller used on the pseries
machine.
Signed-off-by: David Gibson
[aik: added ics_resend() on post_load]
Signed-off-by: Alexey Kardashevskiy
---
hw/intc/xics.c |
From: David Gibson
This patch adds helpers to allow PAPR VIO devices to save state common
to all VIO devices during savevm.
Signed-off-by: David Gibson
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr_vio.c | 20
include/hw/ppc/spapr_vio.h | 5 +
2 files
Currently XICS interrupt controller is not a QEMU device. As we are going
to support in-kernel emulated XICS which is a part of KVM, it make
sense not to extend the existing XICS and have multiple KVM stub functions
but to create yet another device and share pieces between fully emulated
XICS and i
From: David Gibson
The savevm code for the powerpc cpu emulation is currently based around
the old register_savevm() rather than register_vmstate() method. It's also
rather broken, missing some important state on some CPU models.
This patch completely rewrites the savevm for target-ppc, using t
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Andreas Färber
---
default-configs/ppc64-softmmu.mak | 1 +
hw/intc/Makefile.objs | 1 +
hw/{ppc => intc}/xics.c | 0
hw/ppc/Makefile.objs | 2 +-
4 files changed, 3 insertions(+), 1 deletion(-)
rename hw/{ppc =
New patch ("target-ppc: Enhance the CPU node labels for
the guest device tree for pseries") and "savevm for VIO TTY" is
separated from "savevm for VIO LAN".
The series was also rebased on top of current master from qemu.org.
Besides that, no more changes.
Alexey Kardashevskiy (4):
pseries: m
Am 01.07.2013 11:33, schrieb Peter Crosthwaite:
> Hi Andreas,
>
> On Mon, Jul 1, 2013 at 7:00 AM, Andreas Färber wrote:
>> From: Andreas Färber
>>
>> Split the SysBusDevice initfn into instance_init and realizefn.
>>
>> Signed-off-by: Andreas Färber
>> ---
>> hw/timer/arm_mptimer.c | 25 ++
Am 01.07.2013 11:29, schrieb Peter Crosthwaite:
> On Mon, Jul 1, 2013 at 7:00 AM, Andreas Färber wrote:
>> From: Andreas Färber
>>
>> Introduce type constant and cast macro and rename
>> ARMMPTimerState::busdev to enforce its use.
>>
>> Signed-off-by: Andreas Färber
>> ---
>> hw/timer/arm_mptim
Am 06.07.2013 14:44, schrieb Peter Maydell:
> On 6 July 2013 13:40, Andreas Färber wrote:
>> softmmu would do it after the future QMP qom-set phase. The mess there
>> is reset handler registration order: We cannot have most CPUs register a
>> reset handler themselves yet because some machines (inc
Max,
Am 29.06.2013 22:01, schrieb Andreas Färber:
> Register a CPU type per core registered. Save the XtensaConfig in
> XtensaCPUClass instead of CPUXtensaState.
>
> Prepares for storing per-class GDB register count.
>
> Signed-off-by: Andreas Färber
Ping! Can you ack? (It did not seem to brea
** No longer affects: qemu-kvm (Ubuntu Lucid)
** No longer affects: qemu-kvm (Ubuntu Maverick)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/584143
Title:
qemu fails to set hdd serial number
Stat
On 6 July 2013 13:40, Andreas Färber wrote:
> softmmu would do it after the future QMP qom-set phase. The mess there
> is reset handler registration order: We cannot have most CPUs register a
> reset handler themselves yet because some machines (including most ARM
> ones) register reset handlers t
Am 06.07.2013 12:31, schrieb Peter Maydell:
> On 6 July 2013 01:36, Alexander Graf wrote:
>> When we create a new thread, there is no reason to reset it. I'm fairly sure
>> the code has mostly been left in there because nobody understood why it was
>> there in the first place.
>
> We had a big di
The page_unprotect() function is running everything locked. Before every
potential exit path of the function mmap_unlock() gets called to make sure
we don't leak the lock.
However, the function calls tb_invalidate_phys_page() which again can
exit a signal through longjmp, leaving our mmap_unlock()
The epoll emulation uses data structures without packing them, so the
compiler might choose to add padding inside.
This patch makes the most offending one (target_epoll_event) a packed
structure to make sure we don't pad it by accident. ARM would pad it,
so declare the padding mandatory for ARM ta
When forwarding a segmentation fault into the guest process, we were passing
the host's address directly into the guest process's signal descriptor.
That obviously confused the guest process, since it didn't know what to make
of the (usually 32-bit truncated) address. Passing in h2g(address) makes
From: Peter Maydell
In the ARM implementation of cpu_signal_handler(), set is_write
correctly using the FSR value which the kernel passes us in the
error_code field of uc_mcontext. Since the WnR bit of the FSR was
only introduced in ARMv6, this means that v5 cores will continue
to behave as befor
We can easily set the TLS on i386. Add code to do so.
Signed-off-by: Alexander Graf
---
linux-user/i386/target_cpu.h | 12 ++--
linux-user/syscall.c |2 +-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/linux-user/i386/target_cpu.h b/linux-user/i386/target_
Most kernels these days have protection code in place to forbid user space
to access low memory. The barrier varies between architectures though.
For this purpose we have the guest base option that allows us to offset
guest visible memory from host memory, so that the guest process thinks
it can a
When a new thread gets created, we need to reset non arch specific state to
get the new CPU into clean state.
However this reset should happen before the arch specific CPU contents get
copied over. Otherwise we end up having clean reset state in our newly created
thread.
Signed-off-by: Alexander
Howdy,
It's been a while since I've tried to run wine in QEMU's i386
linux-user target, so I figured I'd give it a go again.
Obviously I've hit a bunch of obstacles, some of which were old,
some of which we only introduced recently.
However, with this patch set I am able to successfully run
Civi
The i386 target is now able to properly handle NPTL. Enable it.
Signed-off-by: Alexander Graf
---
configure |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/configure b/configure
index 0e0adde..61f2770 100755
--- a/configure
+++ b/configure
@@ -4156,6 +4156,7 @@ TARGET_AB
The cmsg handling in the linux-user code is very hard to read as it tries
to follow glibc's unreadable code closely. Let's clean it up, converting
all helpers into static inline functions, so that QEMU developers have a
chance to understand what's going on.
While at it, this also allows us to make
On 06.07.2013, at 12:48, Peter Maydell wrote:
> On 6 July 2013 01:36, Alexander Graf wrote:
>> The i386 target is now able to properly handle NPTL. Enable it.
>
> This will conflict with the on-list series which reverses
> the default for target_nptl in this bit of configure
> (though the corre
On 6 July 2013 01:36, Alexander Graf wrote:
> The i386 target is now able to properly handle NPTL. Enable it.
This will conflict with the on-list series which reverses
the default for target_nptl in this bit of configure
(though the correction is obviously trivial).
thanks
-- PMM
On 06.07.2013, at 12:45, Peter Maydell wrote:
> On 6 July 2013 01:36, Alexander Graf wrote:
>> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
>> index 8b06a19..fbc3cac 100644
>> --- a/linux-user/syscall_defs.h
>> +++ b/linux-user/syscall_defs.h
>> @@ -2434,8 +2434,11 @@ typed
On 06.07.2013, at 12:42, Peter Maydell wrote:
> On 6 July 2013 01:36, Alexander Graf wrote:
>> While looking for cmsg entries, we want to compare guest pointers to see
>> whether we're at the end of the passed in array.
>>
>> However, what we really do is we compare our in-use host pointer with
On 6 July 2013 01:36, Alexander Graf wrote:
> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
> index 8b06a19..fbc3cac 100644
> --- a/linux-user/syscall_defs.h
> +++ b/linux-user/syscall_defs.h
> @@ -2434,8 +2434,11 @@ typedef union target_epoll_data {
>
> struct target_epoll_e
On 6 July 2013 01:36, Alexander Graf wrote:
> While looking for cmsg entries, we want to compare guest pointers to see
> whether we're at the end of the passed in array.
>
> However, what we really do is we compare our in-use host pointer with the
> to-be-the-end guest pointer. This comparison is
On 6 July 2013 01:36, Alexander Graf wrote:
> When we create a new thread, there is no reason to reset it. I'm fairly sure
> the code has mostly been left in there because nobody understood why it was
> there in the first place.
We had a big discussion on this on IRC. This code is here
because of
On 6 July 2013 01:36, Alexander Graf wrote:
> When forwarding a segmentation fault into the guest process, we were passing
> the host's address directly into the guest process's signal descriptor.
>
> That obviously confused the guest process, since it didn't know what to make
> of the (usually 32
On 06.07.2013, at 12:24, Peter Maydell wrote:
> On 6 July 2013 01:36, Alexander Graf wrote:
>> When we get a segmentation fault we check whether the fault was a write. If
>> it was a write, it might be a fault because we tried to modify a code region.
>>
>> This logic does not work on ARM hosts
On 04.06.2013, at 15:31, Peter Maydell wrote:
> In the ARM implementation of cpu_signal_handler(), set is_write
> correctly using the FSR value which the kernel passes us in the
> error_code field of uc_mcontext. Since the WnR bit of the FSR was
> only introduced in ARMv6, this means that v5 core
On 6 July 2013 01:36, Alexander Graf wrote:
> When we get a segmentation fault we check whether the fault was a write. If
> it was a write, it might be a fault because we tried to modify a code region.
>
> This logic does not work on ARM hosts, because they don't evaluate whether a
> segementation
Hi,
Is it possible from qemu userspace to identify what type of file access
( DIRECT or SYNC or ASYNC )the guest is performing on its files also along
with their file-names if possible.
I tried to trace bdrv events but I am not able to correctly identify.
Regards
Sen
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