Hi Kuo-Jung
I think you may have accidentally dropped your subject line and
promoted your long commit message to subject line. Looks better in
previous versions.
On Mon, Mar 25, 2013 at 10:09 PM, Kuo-Jung Su wrote:
>
> From: Kuo-Jung Su
>
> Only I2S and SPI protocol have been implemented in thi
The value of "do_interrupt" member of CPUClass shoule be set to a
target-specific function, or it will lead to a segfault like below:
$ moxie-softmmu/qemu-system-moxie -M moxiesim
Segmentation fault
Cc: Anthony Green
Cc: Blue Swirl
Cc: Andreas Färber
Signed-off-by: Dunrong Huang
---
target-m
On 31 March 2013 00:32, Michael W. Bombardieri wrote:
> This morning I tried building Qemu 1.4.0 on my
> Lenovo ThinkPad T61 running OpenBSD/i386 5.1.
> The thread code didn't build due to a missing
> library function. Looking at the code, #if
> statements for NetBSD should also be followed
> for
Hi,
This morning I tried building Qemu 1.4.0 on my
Lenovo ThinkPad T61 running OpenBSD/i386 5.1.
The thread code didn't build due to a missing
library function. Looking at the code, #if
statements for NetBSD should also be followed
for OpenBSD. Using the following patch I was
able to build Qemu us
** Description changed:
Let's assume we have some physical host A. This host runs qemu guest B
locally without any options like "-vnc" etc.
Then I connect from some physical host C to the host A via VNC or Teamviewer
( www.teamviewer.com ). And then I try to remote control (via this vnc
con
Public bug reported:
Let's assume we have some physical host A. This host runs qemu guest B locally
without any options like "-vnc" etc.
Then I connect from some physical host C to the host A via VNC or Teamviewer (
www.teamviewer.com ). And then I try to remote control (via this vnc
connection
The overflow computation of nego and subf*o instructions has been broken
in commit ffe30937. This patch fixes it.
With this change the PPC emulation passes the Gwenole Beauchesne
testsuite again.
Cc: Alexander Graf
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-ppc/translate.c
On Sat, Mar 30, 2013 at 08:54:03AM -0700, Richard Henderson wrote:
> On 03/30/2013 08:33 AM, Aurelien Jarno wrote:
> > +static inline void tcg_out_add2(TCGContext *s, TCGArg retl, TCGArg reth,
> > +TCGArg arg1l, TCGArg arg1h,
> > +TCGA
On Sat, Mar 30, 2013 at 09:00:40AM -0700, Richard Henderson wrote:
> On 03/30/2013 08:33 AM, Aurelien Jarno wrote:
> > +if (const_arg1 && arg1 != 0) {
> > +opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
> > + TCG_REG_R2, arg1, TCG_REG_R0);
> > +} else if (is_sig
On 30 March 2013 21:19, Richard Henderson wrote:
> On 2013-03-30 14:14, Peter Maydell wrote:
>>
>> If you're doing a sub sp, sp, #n anyway, you might as well
>> add 4 to that and drop the save/load of r12 from the stmdb/ldmia.
>> It was only in there to save having an extra sub/add insn.
>
> Fair
On 2013-03-30 14:14, Peter Maydell wrote:
If you're doing a sub sp, sp, #n anyway, you might as well
add 4 to that and drop the save/load of r12 from the stmdb/ldmia.
It was only in there to save having an extra sub/add insn.
Fair enough, not that it ought to make a difference to the cycle coun
On 30 March 2013 20:43, Richard Henderson wrote:
> static void tcg_target_qemu_prologue(TCGContext *s)
> {
> -/* Calling convention requires us to save r4-r11 and lr;
> - * save also r12 to maintain stack 8-alignment.
> - */
> +int frame_size;
>
> +/* Calling convention requi
Work better with branch predition when we have movw+movt,
as the size of the code is the same. Perhaps re-evaluate
when we have a proper constant pool.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm
Use even more primitive helper functions to avoid lots of duplicated code.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 235 ---
1 file changed, 111 insertions(+), 124 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-tar
Make the code more readable by only having one copy of the magic
numbers, swapping registers as needed prior to that. Speed the
compiler by not applying the rd == rn avoidance for v6 or later.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 85 +++
We get to re-use the _rIN and _rIK subroutines to handle the various
combinations of add vs sub. Fold the << 21 into the opcode enum values
so that we can explicitly add TO_CPSR as desired.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 106 -
Move the slow path out of line, as the TODO's mention.
This allows the fast path to be unconditional, which can
speed up the fast path as well, depending on the core.
Signed-off-by: Richard Henderson
---
configure | 2 +-
include/exec/exec-all.h | 17 +++
tcg/arm/tcg-target.c
Use tcg_out_movi32 when it's profitable, which is always for v7.
Simplify the logic around tcg_out_goto, now that we're sure that
it won't generate a multi-insn branch.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 19 +--
1 file changed, 9 insertions(+), 10 deletio
R12 is call clobbered, while R8 is call saved. This change
gives tcg one more call saved register for real data.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 32ed9f
This allows the generation of RSB instructions.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index dbd8ecc..5ea6d6c 100644
--
The schedule was fully serial, with no possibility for dual issue.
The old schedule had a minimal issue of 7 cycles; the new schedule
has a minimal issue of 5 cycles.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 110 ++-
1 file chang
Don't hard-code R8.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 122 ++-
1 file changed, 62 insertions(+), 60 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index d1fcd7c..32ed9f2 100644
--- a/tcg/arm/tcg-tar
This greatly improves the code we can produce for deposit
without armv7 support.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 52 ++--
tcg/arm/tcg-target.h | 2 --
2 files changed, 42 insertions(+), 12 d
Share code between qemu_ld and qemu_st to process the tlb.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 169 +--
1 file changed, 70 insertions(+), 99 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 4ad484
Try fully rotated arguments to mov and mvn before trying movt
or full decomposition. Begin decomposition with mvn when it
looks like it'll help. Examples include
-:mov r9, #0x0fa0
-:orr r9, r9, #0x000ee000
-:orr r9, r9, #0x0ff0
-:orr r9, r9, #0xf00
An armv7 extension implements division, present on Cortex A15.
Signed-off-by: Richard Henderson
---
disas/arm.c | 4
tcg/arm/tcg-target.c | 36
tcg/arm/tcg-target.h | 7 ++-
3 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/di
We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that
any helper with more than 4 arguments would clobber the saved regs.
Realizing that we're supposed to have this memory pre-allocated means
we can clean up the tcg_out_arg functions, which were trying to do
more stack allocation.
A
We have BFI and BFC available for implementing it.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 36
tcg/arm/tcg-target.h | 5 -
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
inde
This allows us to emit CMN instructions.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 5ea6d6c
This greatly improves code generation for addition of small
negative constants.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c | 41 +++--
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/tcg/arm/tcg-target
Changes v3-v4:
* Local stack frame fix has been reworked to be independant of the rest
of the change set, making it possible to cherry-pick to stable.
* While doing that, I've dropped the patch that pulled the epilogue
into the exit_tb expansion, as the stated reason (one insn in the
Thanks, applied.
On Fri, Mar 29, 2013 at 5:20 PM, Stefan Weil wrote:
> The cross i586-mingw32msvc-gcc 4.4.4 from Debian Squeeze does not support
> __sync_val_compare_and_swap by default.
>
> Using -march=i686 fixes that and should also result in better code.
>
> Signed-off-by: Stefan Weil
> ---
Thanks, applied.
On Sun, Mar 24, 2013 at 8:04 AM, Stefan Weil wrote:
> The type cast must use tcg_target_long instead of long.
> This makes a difference for hosts where sizeof(long) != sizeof(void *).
>
> Cc: Anthony Green
> Cc: Blue Swirl
> Signed-off-by: Stefan Weil
> ---
> target-moxie/tra
From: Stuart Yoder
Signed-off-by: Stuart Yoder
---
hw/ppc/e500plat.c |5 +
1 file changed, 5 insertions(+)
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 25ac4b1..2cd7cad 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -16,6 +16,7 @@
#include "sysemu/device_tree.h"
Fallthough into abort = oops.
Cc: qemu-triv...@nongnu.org
Cc: Alexander Graf
Signed-off-by: Richard Henderson
---
target-s390x/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index a4f2194..0c3cf68 100644
--- a/target-s390x/tra
On 03/23/2013 05:52 PM, Aurelien Jarno wrote:
> #endif
> break;
> +case INDEX_op_muls2_i32:
> +tcg_out_opc_reg(s, OPC_MULT, 0, args[2], args[3]);
> +tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
> +tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0);
> +break;
Ping 3. Come on, we're nearly a month out and not a peep...
r~
On 03/19/2013 05:17 PM, Richard Henderson wrote:
> Ping 2.
>
> On 2013-03-11 23:41, Richard Henderson wrote:
>> Ping.
>>
>> On 2013-03-04 16:32, Richard Henderson wrote:
>>> Additional patches since V1:
>>>* Handle constant inp
On 03/30/2013 08:33 AM, Aurelien Jarno wrote:
> +if (const_arg1 && arg1 != 0) {
> +opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
> + TCG_REG_R2, arg1, TCG_REG_R0);
> +} else if (is_signed) {
> +opc2 = tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, ar
On 03/30/2013 08:33 AM, Aurelien Jarno wrote:
> +static inline void tcg_out_add2(TCGContext *s, TCGArg retl, TCGArg reth,
> +TCGArg arg1l, TCGArg arg1h,
> +TCGArg arg2l, TCGArg arg2h,
> +int cmp4)
> +{
>
On 03/29/2013 07:16 PM, Aurelien Jarno wrote:
> This patch series adds the PCLMULQDQ and AES-NI instructions to the x86
> emulation. Along with the SSE4.1 and SSE4.2 series, this brings the
> instructions emulation to the level of a Westmere CPU.
>
> It has been tested with the valgrind testsuite
Il 30/03/2013 14:20, Kevin O'Connor ha scritto:
> On Fri, Mar 29, 2013 at 02:49:12PM +0100, Paolo Bonzini wrote:
>> Il 29/03/2013 14:33, Kevin O'Connor ha scritto:
>>> On Fri, Mar 29, 2013 at 04:18:44PM +0800, Hu Tao wrote:
pvpanic device is used to notify host(qemu) when guest panic happens.
Add 32-bit and 64-bit mulu2 and muls2 TCG ops.
On IA64, 32-bit ops should just ignore the 32 most significant bits of
registers, and can leave them with non-zero values. This means registers
should be zero/sign extended before doing the actual multiplying. This
leave some slots in the bundle to po
Add 32-bit and 64-bit add2 and sub2 TCG ops.
On IA64, 32-bit ops should just ignore the 32 most significant bits of
registers, and can leave them with non-zero values. This means a 32-bit
comparison instruction should be used for add2_i32 and sub32_i32.
Signed-off-by: Aurelien Jarno
---
tcg/ia6
> -Original Message-
> From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
> Sent: 2013年3月29日 20:37
> To: Hanweidong
> Cc: Tim (Xen.org); George Dunlap; Andrew Cooper; Yanqiangjun; qemu-
> de...@nongnu.org; xen-de...@lists.xen.org; Gonglei (Arei); Anthony
> Perard; Wangzheng
The QEMU icon which is already used for SDL
is now also loaded by GTK.
Signed-off-by: Stefan Weil
---
ui/gtk.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/ui/gtk.c b/ui/gtk.c
index a5a8156..c15023b 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -1363,6 +1363,7 @@ static const D
On Sat, Mar 30, 2013 at 01:45:26PM +, Blue Swirl wrote:
> On Fri, Mar 29, 2013 at 9:44 PM, wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-microblaze/translate.c | 15 +++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/translate.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index a74da8e..06d2346 100644
--- a/target-microblaze/translate.c
+
On Thu, Mar 28, 2013 at 7:00 PM, Anthony Green wrote:
> Hi Stefan,
>
> This change is fine by me.
>
> It's not clear to me, as the author/maintainer of the moxie port, what
> my responsibility/authority is. Do I simply reply to patches like
> this with...
>
> Looks good to me.
> Signed-off-by: An
On 30 March 2013 13:44, Blue Swirl wrote:
> On Fri, Mar 29, 2013 at 5:58 PM, Peter Maydell
> wrote:
>> On 29 March 2013 17:20, Stefan Weil wrote:
>>> Maybe this modification is also needed for native gcc-4.4 and older
>>> on Linux i386. If yes, we can move the new script code out of the
>>> Min
On Fri, Mar 29, 2013 at 9:44 PM, wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-microblaze/translate.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index a74da
On Fri, Mar 29, 2013 at 5:58 PM, Peter Maydell wrote:
> On 29 March 2013 17:20, Stefan Weil wrote:
>> Maybe this modification is also needed for native gcc-4.4 and older
>> on Linux i386. If yes, we can move the new script code out of the
>> MinGW conditional code.
>
> There are at least a few pe
On Thu, Mar 28, 2013 at 7:20 PM, Mark Cave-Ayland
wrote:
> On 22/03/13 05:19, Rob Landley wrote:
>
>> If I do this:
>>
>> qemu-system-sparc -nographic -no-reboot -kernel image -hda hda.sqf
>> -append 'root=/dev/sda rw init=/sbin/init.sh panic=1
>> PATH=/usr/distcc:/bin:/sbin console=ttyS0 HOST=spa
On Fri, Mar 29, 2013 at 02:49:12PM +0100, Paolo Bonzini wrote:
> Il 29/03/2013 14:33, Kevin O'Connor ha scritto:
> > On Fri, Mar 29, 2013 at 04:18:44PM +0800, Hu Tao wrote:
> >> pvpanic device is used to notify host(qemu) when guest panic happens.
> >
> > Thanks. However, we're planning a move of
On Thu, Mar 28, 2013 at 11:46 AM, Mark Cave-Ayland
wrote:
>
> On 27/03/13 16:43, Artyom Tarasenko wrote:
>
>>> So as a stepping stone, should we create an FCode ROM for TCX?
>>
>>
>> Sounds reasonable to me, but
>> - afaik the current TCX implementation is written in C, no Forth. So
>> maybe it's
于 2013-3-30 7:04, Eric Blake 写道:
On 03/22/2013 08:19 AM, Wenchao Xia wrote:
This function will simply call qmp interface qmp_query_snapshots()
added in last commit and then dump information in monitor console.
To get snapshot info, Now qemu and qemu-img both call block layer
function bdrv_
于 2013-3-30 4:10, Eric Blake 写道:
On 03/22/2013 08:19 AM, Wenchao Xia wrote:
This is a code move patch, except in qmp_query_block bdrv_next(bs)
is used instead of direct traverse of global array 'bdrv_states'.
Mixing code motion and a code change isn't always the best, but at least
you were
Hello, everyone
I found a problem about "loadvm", when I use Spice.
Host OS: Fedora 17
Qemu: 1.4.0
Spice: 0.12.2
Quest OS: WinXP
1) Use the following command to start the VM:
qemu-kvm -enable-kvm -name winxp -M pc-0.15 -m 1024 -smp 2 -boot c -device
piix3-usb-uhci,id=usb,bus=pci.0,addr=0x1.
On 30 March 2013 06:25, Brad Smith wrote:
> init_get_clock() already indicates to get_clock() to utilize
> clock_gettime() with a monotonic clock but OpenBSD was missing
> from the list of OS's to use a monotonic clock on.
>
> What I don't understand is why is init_get_clock() not called
> anywher
On Mon, Mar 04, 2013 at 07:01:32PM +1000, Peter Crosthwaite wrote:
> Hi All. The clock controller module in the Zynq platform has the ability to
> halt
> and reset arbitrary devices, including the CPU. We use this feature to
> implement
> SMP Linux - the kernel halts CPU1 then rewrites the vector
On Mon, Mar 04, 2013 at 07:01:34PM +1000, Peter Crosthwaite wrote:
> Set up the Device level halting API to halt cpus. This allows holders of a
> pointer to the CPU to halt it from the TYPE_DEVICE abstraction. (i.e. they
> can halt it even if they dont know its a CPU).
>
> Signed-off-by: Peter Cro
On Sat, Mar 30, 2013 at 03:16:29AM +0100, Aurelien Jarno wrote:
> This patch series adds the PCLMULQDQ and AES-NI instructions to the x86
> emulation. Along with the SSE4.1 and SSE4.2 series, this brings the
> instructions emulation to the level of a Westmere CPU.
>
> It has been tested with the v
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