Il 09/10/2012 22:22, Richard Henderson ha scritto:
> On 10/06/2012 05:30 AM, Paolo Bonzini wrote:
>> +static inline void gen_setcc1(DisasContext *s, int b, TCGv reg)
>> {
>> +int inv, jcc_op, size, cond;
>> +TCGv t0;
>> +
>> +inv = b & 1;
>> jcc_op = (b >> 1) & 7;
>> +
>> swi
Il 09/10/2012 22:07, Richard Henderson ha scritto:
>> > +case CC_OP_ADCB:
>> > +case CC_OP_ADCW:
>> > +case CC_OP_ADCL:
>> > +case CC_OP_ADCQ:
>> > +/* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
>> > +size = (s->cc_op - CC_OP_ADDB) & 3;
>> > +t1 = gen_ext_tl(c
On Wed, Oct 10, 2012 at 01:17:36PM +0900, Yeongkyoon Lee wrote:
> On 2012년 10월 10일 02:09, Aurelien Jarno wrote:
> >On Tue, Oct 09, 2012 at 06:55:58PM +0200, Paolo Bonzini wrote:
> >>Il 09/10/2012 18:19, Aurelien Jarno ha scritto:
> >Instead of calling the MMU helper with an additional argument
Il 09/10/2012 21:16, Richard Henderson ha scritto:
>> > +int size = (s->cc_op - CC_OP_ADDB) & 3;
>> > +gen_ext_tl(reg, cpu_cc_dst, size, false);
>> > +tcg_gen_setcondi_tl(TCG_COND_EQ, reg, cpu_cc_dst, 0);
> I take that back. Should be (EQ, reg, reg, 0) here;
> you've droppe
Il 10/10/2012 04:11, Chen HanXiao ha scritto:
>> >
>> > On Tue, Oct 09, 2012 at 05:42:01PM +0800, Chen HanXiao wrote:
>>> > > When we use SCSI generic device as disk image, function lseek could
>>> > > not get the size of this kind of device.
>>> > > So try to use SCSI command Read Capacity(10) wh
This simplifies some code and error checking, and also fixes a bug.
bdrv_find_backing_image() should only be passed absolute filenames,
or filenames relative to the chain. In the QMP message handler for
block commit, when looking up the base do so from the determined top
image, so we know it is r
Eric reported some bugs with relative pathnames and block-commit.
These patches attempt to fix those issues, by changing how we do
some filename and path comparisons. There is also some minor
simplication of error checking for block-commit as well.
Jeff Cody (2):
block: make bdrv_find_backing
Currently, bdrv_find_backing_image compares bs->backing_file with
what is passed in as a backing_file name. Mismatches may occur,
however, when bs->backing_file and backing_file are both not
absolute or relative.
Use path_combine() to make sure any relative backing filenames are
relative to the c
Hi,
all files in fsdev still use GNU GPL version 2 only instead of
GNU GPL version 2 or later.
Can this be fixed? If not, we should addtext like this:
* Contributions after 2012-10-10 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
Is it possibl
Hello,
Still not compile clean, also on the build servers. Who is responsible
for the fix?
Ciao,
Gerhard
On 16.09.2012 18:25, Gerhard Wiesinger wrote:
Hello,
qemu is currently not compile clean on Fedora 17:
CC fsdev/virtfs-proxy-helper.o
fsdev/virtfs-proxy-helper.c: In function ‘setfsugid
On 2012년 10월 10일 03:49, Richard Henderson wrote:
On 10/09/2012 05:37 AM, Yeongkyoon Lee wrote:
+#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
+/* Initialize qemu_ld/st labels to assist code generation at the end of TB
+ for TLB miss cases at the end of TB */
+
On 2012년 10월 10일 02:09, Aurelien Jarno wrote:
On Tue, Oct 09, 2012 at 06:55:58PM +0200, Paolo Bonzini wrote:
Il 09/10/2012 18:19, Aurelien Jarno ha scritto:
Instead of calling the MMU helper with an additional argument (7), and
then jump back (8) to the next code (4), what about pushing the add
Hi
> -Original Message-
> From: Christoph Hellwig [mailto:h...@lst.de]
> Sent: Wednesday, October 10, 2012 1:21 AM
> To: Chen HanXiao
> Cc: qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH] Use SCSI command to get size of SG
device
>
> On Tue, Oct 09, 2012 at 05:42:01PM +0800, Chen
On 10/09/2012 04:31 PM, Stefan Hajnoczi wrote:
> On Tue, Oct 09, 2012 at 10:27:26AM +0800, Dave Young wrote:
>> On 10/05/2012 04:14 PM, Stefan Hajnoczi wrote:
>>
>>> On Sun, Sep 23, 2012 at 10:37:09AM +0800, Dave Young wrote:
For the serial number decreasing issue, I think there's only these
On Wed, Oct 10, 2012 at 10:46:33AM +1000, Peter Crosthwaite wrote:
> The following changes since commit 4bb26682f70a5f626cad3e0ac82bf4b6252ea7a4:
> Blue Swirl (1):
> Merge branch 'master' of git.qemu.org:/pub/git/qemu
>
> are available in the git repository at:
>
> git://developer.pet
From: Peter A. G. Crosthwaite
Added device model for the Xilinx Zynq SPI controller (SPIPS).
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Peter Maydell
---
hw/arm/Makefile.objs |1 +
hw/xilinx_spips.c| 352 ++
2 files changed, 353 i
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, October 10, 2012 4:08 AM
> To: Bhushan Bharat-R65777
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; ag...@suse.de;
> afaer...@suse.de;
> Bhushan Bharat-R65777
> Subject: Re: [Qemu-devel] [PATCH 2/2 v2] Adding BAR0 for e
From: Peter A. G. Crosthwaite
Added maintainership for SSI, M25P80 and the Xilinx SPI controllers.
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Peter Maydell
---
MAINTAINERS |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 78d
From: Peter A. G. Crosthwaite
Device model for xilinx XPS SPI controller (v2.0)
Signed-off-by: Peter A. G. Crosthwaite
---
hw/microblaze/Makefile.objs |1 +
hw/xilinx_spi.c | 383 +++
2 files changed, 384 insertions(+), 0 deletions(-)
c
From: Peter A. G. Crosthwaite
Added default CS behaviour for SSI slaves. SSI devices can set a property
to enable CS behaviour which will create a GPIO on the device which is the
CS. Tristating of the bus on SSI transfers is implemented.
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Peter Ma
Added helper function to automatically connect SPI slaves based on the QOM child
nodes of a device. A SSI master device can call this routine to automatically
hook-up all child nodes to its SPI bus.
Signed-off-by: Peter Crosthwaite
Acked-by: Peter Maydell
---
hw/ssi.c | 33 ++
From: Peter A. G. Crosthwaite
Allow multiple qdev_init_gpio_in() calls for the one device. The first call will
define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled
with different handlers. Needed when two levels of the QOM class heirachy both
define GPIO functionality,
From: Peter A. G. Crosthwaite
Added SPI controller to the reference design, with two n25q128 spi-flashes
connected.
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Peter Maydell
---
hw/petalogix_ml605_mmu.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
From: Peter A. G. Crosthwaite
Added device model for m25p80 style SPI flash family.
Signed-off-by: Peter A. G. Crosthwaite
---
default-configs/arm-softmmu.mak |1 +
default-configs/microblaze-softmmu.mak |2 +
default-configs/microblazeel-softmmu.mak |2 +
hw/Makefile.ob
From: Peter A. G. Crosthwaite
Added the two SPI controllers to the zynq machine model. Attached two SPI flash
devices to each controller.
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Peter Maydell
---
hw/xilinx_zynq.c | 34 ++
1 files changed, 34 insertio
From: Peter A. G. Crosthwaite
Removed the explicit SSI mux and wired the CS line directly up to the SSI
devices.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/ssd0323.c |1 +
hw/ssi-sd.c|1 +
hw/stellaris.c | 94 +--
3 files c
From: Peter A. G. Crosthwaite
Added a FIFO API that can be used to create and operate byte FIFOs.
Signed-off-by: Peter A. G. Crosthwaite
---
hw/Makefile.objs |1 +
hw/fifo.c| 78 ++
hw/fifo.h| 99 ++
From: Peter A. G. Crosthwaite
Slave creation function that can be used to create an SSI slave without
qdev_init() being called. This give machine models a chance to set properties.
Signed-off-by: Peter A. G. Crosthwaite
Acked-by: Peter Maydell
---
hw/ssi.c |9 +++--
hw/ssi.h |1 +
From: Peter A. G. Crosthwaite
Removed assertion that only one device is attached to the SSI bus.
When multiple devices are attached, all slaves have their transfer function
called for transfers. Each device is responsible for knowing whether or not its
CS is active, and if not returning 0. The r
The following changes since commit 4bb26682f70a5f626cad3e0ac82bf4b6252ea7a4:
Blue Swirl (1):
Merge branch 'master' of git.qemu.org:/pub/git/qemu
are available in the git repository at:
git://developer.petalogix.com/public/qemu.git for-upstream/spi-initial.9
Peter A. G. Crosthwaite (1
On Tue, Oct 09, 2012 at 05:24:29PM +0100, Peter Maydell wrote:
> On 9 October 2012 13:53, David Gibson wrote:
> > Well, the place I've used this (in patches yet to be posted) is saving
> > the state of the pseries machine itself. Specifically, I use
> > VMSTATE_TPA_EQUAL to sanity check that the
On 10/09/2012 01:19:10 PM, Bharat Bhushan wrote:
+static int e500_ccsr_initfn(SysBusDevice *dev)
+{
+PPCE500CCSRState *pci_ccsr;
+
+pci_ccsr = CCSR(dev);
+memory_region_init(&pci_ccsr->ccsr_space, "e500-ccsr",
+ MPC8544_CCSRBAR_SIZE);
+return 0;
+}
Is this
And initialize it such that it (may) write directly to rd.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5b7e82b..8559cc3 100644
--- a/target-sparc
We don't need another temporary here. Load directly into the
register we want to set.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 53 +++-
1 file changed, 21 insertions(+), 32 deletions(-)
diff --git a/target-sparc/translate.c b/t
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5296a37..5013aee 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/tran
Remove the last uses of cpu_tmp32. Unify the code between sparc64
and sparc32 by using the proper "tl" functions.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 37 +
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/target-spar
On Mon, Oct 08, 2012 at 03:53:37PM -0500, Anthony Liguori wrote:
> Peter Maydell writes:
>
> > On 8 October 2012 21:23, Anthony Liguori wrote:
> >> It may be possible to cheat and compile the TCG + CPU code multiple
> >> times as dynamic libraries. You can then load the libraries with
> >> dlop
All users of gen_movl_{reg_TN,TN_reg} are removed. At the same time,
make cpu_val a local variable for load/store disassembly.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 58 +---
1 file changed, 20 insertions(+), 38 deletions(-)
This means we can avoid the incoming temporary, though the cleanup
of the existing temporaries is not performed in this patch.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 75 +++-
1 file changed, 29 insertions(+), 46 deletions(-)
d
Now that get_temp_tl is used for get_src[12], we don't need to
pre-allocate these temporaries.
Fallout from this is moving some assignments around cas/casx to
avoid uninitialized variable warnings.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 16 +++-
1 file chang
Only handle the easy cases directly within disas_sparc_insn.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 420 ---
1 file changed, 177 insertions(+), 243 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
Use a locally allocated temporary instead.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 73 +---
1 file changed, 44 insertions(+), 29 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index ed341b8..9b7bb
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index f4ab6cc..8a2e914 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -20
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 64feaa3..16cf8de 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/tran
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index e3e4256..5296a37 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/tra
The primary goal of this patch set is to have all references to windowed
registers to go through new routines that have access to DisasContext.
This is a prerequisite to any change in how windowed registers might be
managed.
Since such a goal must of course touch get_src[12], and therefore touch
t
The use of "tl" functions and a tmp64 is logically incompatible.
Use cpu_tmp0 instead.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 00ceb9d.
Infrastructure to be used to clean up handling of temporaries.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 52
1 file changed, 52 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 6cef96b..ee
No need to copy to a temporary to store 32 bits.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 56 +---
1 file changed, 24 insertions(+), 32 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 43e44d5.
Use cpu_tmp0 for other stuff, like Write Priv Register.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 52
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 1
Subroutines do their own local temporary management.
Within disas_sparc_insn we limit the existance of the variable
to OP=2 insns, and delay initialization as late as is reasonable
for the specific XOP.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 200 +
In all cases we don't have write-before-read problems.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 9b7bbef..00ceb9d 1
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 2a95c1f..e3e4256 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask the
address.
Signed-off-by: Aurelien Jarno
---
target-mips/op_helper.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 6ce27c1..ad5d1c2 100644
--- a/target-mi
Push the DisasContext down so that we can use gen_load/store_gpr
in sode gen_ldda_asi, gen_stda_ast, gen_cas_asi, gen_casx_asi.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 61 +---
1 file changed, 32 insertions(+), 29 deletions(-)
Operations with side effects (in practice qemu_ld/st ops), only need to
synchronize globals to make sure the CPU state is consistent in case of
exception.
Signed-off-by: Aurelien Jarno
---
tcg/tcg.c | 33 -
tcg/tcg.h |4 ++--
2 files changed, 26 insertions(+
Store conditional operations only need local temps in user mode. Fix
the code to use temp local only in user mode, this spares two memory
stores in system mode.
At the same time remove a wrong a wrong copied & pasted comment,
store operations don't have a register destination.
Signed-off-by: Aure
The first patch is a bug fix for the previous series,
already posted.
The second patch improves the common cases of using
andcc or orcc to test bits in a register. It also
just so happens to show potential cleanup value in
the ALWAYS and NEVER conditions. ;-)
The third patch is one that I th
Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 91 ---
1 file changed, 31 insertions(+), 60
Now that the liveness analysis provides more information, rewrite
tcg_reg_alloc_mov(). This changes the behaviour about propagating
constants and memory accesses. We now take the assumption that once
a value is loaded into a register (from memory or from a constant),
it's better to keep it there th
Signed-off-by: Richard Henderson
Tested-by: Aurelien Jarno
---
target-sparc/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 472eb51..71b9d65 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1120,6 +
Avoid speculatively computing flags before every potentially trapping
operation and instead do the flags computation when a trap actually
occurs. This gives approximately 30% speedup in emulation.
Signed-off-by: Richard Henderson
---
linux-user/main.c | 5 +
target-sparc/int32_he
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-alpha/helper.h | 176 -
1 file changed, 88 insert
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 58 +---
1 file changed, 40 insertions(+), 18 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 71b9d65..4409f69 100644
--- a/target-sparc/translate.c
+++
Now that save_state never ends a BB, we don't need to copy
values into local temps around it.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 30 +-
1 file changed, 9 insertions(+), 21 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.
Signed-off-by: Aurelien Jarno
---
target-i386/helper.h |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-i386/helper.h b/target-i3
Remove suboptimal register shifting in qemu_ld/st ops, introduced at the
CONFIG_TCG_PASS_AREG0 time.
As mem_idx is now loaded in register R58/R59 for the slow path, we have
to make sure to do it last, to not add additional register constraints.
Signed-off-by: Aurelien Jarno
---
tcg/ia64/tcg-tar
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.
Cc: Edgar E. Iglesias
Signed-off-by: Aurelien Jarno
---
target-cris/helper.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --g
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.
Cc: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target-ppc/helper.h | 38 +++---
1 file changed, 19 insertions(+), 19 dele
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.
Signed-off-by: Aurelien Jarno
---
target-mips/helper.h | 106 +-
1 file changed, 53 insertions(+), 53 deletions(-
Only allocate t1 when needed.
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c1438ff..f7d9467 100644
--- a/target-mips/translate.c
+++ b/targ
Add a pickNaNMulAdd function for MIPS, implementing NaN propagation
rules for MIPS fused multiply-add instructions.
Cc: Peter Maydell
Signed-off-by: Aurelien Jarno
---
fpu/softfloat-specialize.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/fpu/softfloat-spe
Start with local temps in TEMP_VAL_MEM state, to make possible a later
check that all the temps are correctly saved back to memory.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/tcg.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.
Cc: Max Filippov
Signed-off-by: Aurelien Jarno
---
target-xtensa/helper.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/
Mapping a memory address using a global and accessing it through
ld/st operations is currently broken. As it doesn't make any sense
to do that performance wise, let's forbid that.
Update the TCG documentation, and remove partial support for that.
Signed-off-by: Aurelien Jarno
---
tcg/README
Now that the liveness analysis might mark some output temps as dead, call
temp_dead() if needed.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/tcg.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 400581f..328df56 100644
--- a/tcg/tcg
load/store microMIPS helpers are reinventing the wheel. Call do_lw,
do_ll, do_sw and do_sl instead of using a macro calling the cpu_*
load/store functions.
Signed-off-by: Aurelien Jarno
---
target-mips/op_helper.c | 73 ++-
1 file changed, 9 insertio
For each FPU instruction that can trigger an FPU exception, it is needed
to reset the softfloat status before and call update_fcr31() after.
Remove the manual NaN assignment in case of float to float operation, as
softfloat is already taking care of that. However for float to int
operation, the va
Always mark dead input arguments as dead, even if the op is at the basic
block end. This will allow to check that all temps are correctly saved.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/tcg.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
dif
This patch series improve the IA64 backend by adding the movcond
instruction and optimizing the qemu_ld/st ops.
It also includes a patch from Blue Swirl posted more than a year
ago to use stack for TCG temps.
Aurelien Jarno (3):
tcg/ia64: implement movcond_i32/64
tcg/ia64: remove suboptimal r
tcg_out_goto_label is only used inside a TB, so there is no reason
for not using 24-bit branches even for COND_AL.
Cc: Andrzej Zaborowski
Cc: Peter Maydell
Signed-off-by: Aurelien Jarno
---
tcg/arm/tcg-target.c |7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tcg/ar
Use ldr pc, [pc, #-4] kind of branch for direct jump. This removes the
need to flush the icache on TB linking, and allow to remove the limit
on the code generation buffer.
This improves the boot-up speed of a MIPS guest by 11%.
Cc: Andrzej Zaborowski
Cc: Peter Maydell
Signed-off-by: Aurelien Ja
Implement movcond_i32/64 on ia64 hosts. It is not possible to have
immediate compare arguments without adding a new bundle, but it is
possible to have 22-bit immediate value arguments.
Signed-off-by: Aurelien Jarno
---
tcg/ia64/tcg-target.c | 38 ++
tcg/ia64
The TCG arm backend considers likely that the offset to the TLB
entries does not exceed 12 bits for mem_index = 0. In practice this is
not true for at list the MIPS target.
The current patch fixes that by loading the bits 23-12 with a separate
instruction, and using loads with address writeback, i
The liveness analysis ensures that globals and temps are at the correct
state at a basic block end or with an op with side effects. Avoid
looping on all temps, this can be time consuming on targets with a lot
of globals. Keep an assert in debug mode.
Signed-off-by: Aurelien Jarno
---
tcg/tcg.c |
The result of a division by 0, or a division of INT_MIN by -1 in the
signed case, is unpredictable. Just replace 0 by 1 in that case so that
it doesn't trigger a floating point exception on the host.
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 89 ++-
I am seeing more or less the same thing. I am trying to boot Puppy Linux
from Gentoo with qemu-kvm-1.1.1-r3 and gentoo-sources-3.6.0.
Interestingly, I also found that AROS crashed when using "-cpu host" but
I initially chalked that up to AROS being flakey - perhaps not.
Obviously I can't enable tho
Some branch related ops are marked with TCG_OPF_SIDE_EFFECTS, some other
not. In practice they don't need to, as they are all marked with
TCG_OPF_BB_END, which is handled specifically in all the code.
The call op is marked as TCG_OPF_SIDE_EFFECTS, which might be not true
as there is are specific f
From: Blue Swirl
Use stack instead of temp_buf array in CPUState for TCG temps.
Signed-off-by: Blue Swirl
Signed-off-by: Aurelien Jarno
---
tcg/ia64/tcg-target.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 7
On 9 October 2012 21:30, Aurelien Jarno wrote:
> The TCG arm backend considers likely that the offset to the TLB
> entries does not exceed 12 bits for mem_index = 0. In practice this is
> not true for at list the MIPS target.
>
> The current patch fixes that by loading the bits 23-12 with a separa
Add a new function temp_sync() to synchronize the canonical location
of a temp with the value in the corresponding register, but without
freeing the associated register. Rewrite temp_save() to call
temp_sync() followed by temp_dead().
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Rusty Russell wrote:
> I don't think it'll be that bad; reset clears the device to unknown,
> bar0 moves it from unknown->legacy mode, bar1/2/3 changes it from
> unknown->modern mode, and anything else is bad (I prefer being strict so
> we catch bad implementations from the beginning).
Will that w
This patch series does some bug fixes and code cleanup in the MIPS
target, and then does some optimizations.
Aurelien Jarno (14):
softfloat: implement fused multiply-add NaN propagation for MIPS
target-mips: use the softfloat floatXX_muladd functions
target-mips: fix FPU exceptions
target-
Avoid the branches in movn/movz implementation and replace them with
movcond. Also update a wrong command.
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/target-mips/translate.c b/targe
Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the
previous names was to keep the macros simple.
Signed-off-by: Aurelien Jarno
---
It is possible to slightly optimize the TLB access code, by replacing
the movi + and instructions by a deposit instruction.
Signed-off-by: Aurelien Jarno
---
tcg/ia64/tcg-target.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/tcg/ia64/tcg-target.c
Add a new function tcg_reg_sync() to synchronize the canonical location
of a temp with the value in the associated register, but without freeing
it. Rewrite tcg_reg_free() to first call tcg_reg_sync() and then to free
the register.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
The current helper flags, TCG_CALL_CONST and TCG_CALL_PURE might be
confusing and doesn't provide enough granularity for some helpers (FP
helpers for example).
This patch changes them into the following helpers flags:
- TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals,
either
The bswap16 TCG opcode assumes that the high bytes of the temp equal
to 0 before calling it. The ARM backend implementation takes this
assumption to slightly optimize the generated code.
The same implementation is called for implementing the cross-endian
qemu_st16 opcode, where this assumption is
On an ARM host, the registers definitions from cpu.h clash
with /usr/include/sys/ucontext.h. As there are unused, just remove
them.
Cc: Jia Liu
Cc: qemu-sta...@nongnu.org
Signed-off-by: Aurelien Jarno
---
target-openrisc/cpu.h | 18 --
1 file changed, 18 deletions(-)
diff --g
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