Il 13/09/2012 23:45, Jeff Cody ha scritto:
> While there are more changes this way, I think it cleans up the code a
> bit. The advantage is that bs->open_flags actually reflects the open
> flags that are currently in use. One disadvantage I see is that it
> seems a bit odd to have BDRV_O_CACHE_WC
Il 14/09/2012 00:27, Nicholas A. Bellinger ha scritto:
> *) Keep vhost-scsi as a backend to virtio-scsi-pci
>
> - Reduces duplicated code amongst multiple virtio-scsi backends.
>
> - Follows the split for what existing vhost-net code already does.
>
> So that said, two quick questions for
On Fri, Sep 14, 2012 at 01:23:16AM +0200, Alexander Graf wrote:
>
> On 11.09.2012, at 20:47, Aurelien Jarno wrote:
>
> > From: Max Filippov
> >
> > Flags passed into float{32,64}_muladd are treated as bits; assign
> > independent bits to float_muladd_negate_* to allow precise control over
> > w
Am 14.09.2012 00:20, schrieb Richard Henderson:
On 09/13/2012 03:03 PM, Peter Maydell wrote:
Hard to come up with a snappy name for "register which is the Nth
input argument if input args are in registers, but an arbitrary
temp reg otherwise, and which is in the forbidden list for the L
constrai
Thanks for the feedback. I'll see about getting things updated once I have
the chance. I wasn't too terribly concerned with performance as the target
processor being emulated is much slower than the host (about 100MHz). Even
the way things are now, Linux runs several times faster in emulation that
Thanks for the feedback. Nothing jumps out at me that I disagree with. I'll
get it updated and another patch out once I get the chance to incorporate
the info.
> +#include "hw/sysbus.h"
> +#include "dyngen-exec.h"
> +#include "cpu.h"
> +
> +struct altera_iic {
CamelCase
Yep. I missed that one
From: Jason Wang
Add a link status chang callback and change the link status bit in BMSR
& MSR accordingly. Tested in Linux/Windows guests.
The LinkDown bit of MediaStatus is inverse with link status.
Signed-off-by: Jason Wang
Signed-off-by: Amos Kong
---
v2: don't add MediaState in RTL8139St
Hi,
about the OOM issue, I plan to drop the OOM request for now in
implemention, and at next step use rpc to wrap these APIs, then
user can select to link directly against the library or the wrapped
API, what do you think about it?
> 于 2012-9-11 5:07, Eric Blake 写道:
>> On 09/10/2012 02:26 AM, Wen
Original conversation about this issue on osdev.org:
http://forum.osdev.org/viewtopic.php?f=1&t=25795
** Description changed:
Hi,
I have been getting a GPF when I enable interrupts, working on
implementing processes and a scheduler. When I comment out the scheduler
code, I still get th
Public bug reported:
Hi,
I have been getting a GPF when I enable interrupts, working on
implementing processes and a scheduler. When I comment out the scheduler
code, I still get the GPF. I used the following QEMU command line to
capture a log:
qemu-system-i386 -smp 4 -monitor stdio -cpu core2du
** Attachment added: "Test case for bug..."
https://bugs.launchpad.net/bugs/1050694/+attachment/3313662/+files/harddisk.img
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1050694
Title:
Interrup
Hi,
Any comments about that?
Regards,
Marcelo
On Tue, Sep 11, 2012 at 02:13:38PM -0400, Corey Bryant wrote:
> Are there any other requirements that need to be taken care of to
> enable execution of QEMU guests under separate unprivileged user IDs
> (ie. DAC isolation)?
>
> At this point, this p
On 13/09/12 20:29, Stefan Hajnoczi wrote:
On Thu, Sep 13, 2012 at 9:51 AM, Amos Kong wrote:
From: Jason Wang
Add a link status chang callback and change the link status bit in BMSR
& MSR accordingly. Tested in Linux/Windows guests.
The link status bit of MediaStatus is infered from BasicMode
The Buildbot has detected a new failure on builder default_i386_rhel61 while
building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_i386_rhel61/builds/364
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_rhel61_32bit
From: Greg Ungerer
Fill out the code support for the move to/from usp instructions. They are
being decoded, but there is no code to support their actions. So add it.
Current versions of Linux running on the ColdFire 5208 use these instructions.
Signed-off-by: Greg Ungerer
---
target-m68k/tran
Hi Richard,
On 14/09/12 03:34, Richard Henderson wrote:
On 09/12/2012 11:33 PM, g...@snapgear.com wrote:
+uint32_t HELPER(move_from_usp)(CPUM68KState * env)
+{
+return env->sp[M68K_USP];
+}
You don't need helpers for these.
DISAS_INSN(move_from_usp)
{
+TCGv reg;
if (IS_USE
On 11.09.2012, at 20:47, Aurelien Jarno wrote:
> From: Max Filippov
>
> Flags passed into float{32,64}_muladd are treated as bits; assign
> independent bits to float_muladd_negate_* to allow precise control over
> what gets negated in float{32,64}_muladd.
>
> Cc: Alexander Graf
> Cc: Peter Ma
On 13.09.2012, at 22:12, Jason Baron wrote:
> Hi,
>
> Qemu bits for q35 support, I'm posting the seabios changes separately. The
> patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
> qemu command line. Hopefully, we can make it the default for x86 at some
> future
> point
On 2012-09-13 21:56, Hervé Poussineau wrote:
> Jan Kiszka a écrit :
>> On 2012-09-13 07:55, Hervé Poussineau wrote:
>>> This option is described in RFC 1783. As this is only an optional field,
>>> we may ignore it in some situations and handle it in some others.
>>>
>>> However, MS Windows 2003 PXE
On Tue, 2012-09-11 at 18:07 +0300, Michael S. Tsirkin wrote:
> On Tue, Sep 11, 2012 at 08:46:34AM -0500, Anthony Liguori wrote:
> > On 09/10/2012 01:24 AM, Michael S. Tsirkin wrote:
> > >On Mon, Sep 10, 2012 at 08:16:54AM +0200, Paolo Bonzini wrote:
> > >>Il 09/09/2012 00:40, Michael S. Tsirkin ha
On 09/13/2012 03:03 PM, Peter Maydell wrote:
> Hard to come up with a snappy name for "register which is the Nth
> input argument if input args are in registers, but an arbitrary
> temp reg otherwise, and which is in the forbidden list for the L
> constraint"...
I'm more than happy to let "registe
On 13 September 2012 22:47, Aurelien Jarno wrote:
> On Thu, Sep 13, 2012 at 02:30:36PM -0700, Richard Henderson wrote:
>> On 09/13/2012 02:21 PM, Aurelien Jarno wrote:
>> >> > #if TCG_TARGET_REG_BITS == 32
>> >> > tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
>> >> > (A
Paolo,
Awesome!!! I just tried your patch, and it works beautifully.
I've been struggling with the lack of '--cache=writeback' for
months now with many work-arounds/kludges.
Thank you again for responding.
Qemu rocks!
Best regards,
Mark Trumpold
> -Original Message-
> From: Paolo Bon
On Thu, Sep 13, 2012 at 02:30:36PM -0700, Richard Henderson wrote:
> On 09/13/2012 02:21 PM, Aurelien Jarno wrote:
> >> > #if TCG_TARGET_REG_BITS == 32
> >> > tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
> >> > (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
> >> >
On Thu, 2012-09-13 at 12:15 -0300, Erlon Cruz wrote:
> >> > lack of experience in the internals of the arch we would like you guys
> >> > to give us some design directions
> >> > and confirm if we going in the right direction. Our first idea is:
> >> >
> >> > 1 - to patch 'spapr.c' so it can
On 09/13/2012 04:29 PM, Paolo Bonzini wrote:
> Il 13/09/2012 21:44, Paolo Bonzini ha scritto:
>> Il 13/09/2012 21:04, Jeff Cody ha scritto:
> Perhaps we _should_ preserve that in bs->open_flags, while still using
> the initial value of BDRV_O_CACHE_WB to initialize bs->enable_write_cache.
>
On 09/13/2012 02:21 PM, Aurelien Jarno wrote:
>> > #if TCG_TARGET_REG_BITS == 32
>> > tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
>> > (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
>> > -tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[1], TCG_REG_ESP,
>
On Thu, Sep 13, 2012 at 07:37:43PM +0200, Stefan Weil wrote:
> TCG uses 6 registers for function arguments on 64 bit Linux hosts,
> but only 4 registers on W64 hosts.
>
> Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the number
> of arguments for some important helper functions from 4
On Thu, Sep 13, 2012 at 07:37:44PM +0200, Stefan Weil wrote:
> While 64 bit hosts use the first three registers which are also used
> as function input parameters, 32 bit hosts use TCG_REG_EAX and
> TCG_REG_EDX which are not used in parameter passing.
>
> After defining new register macros for the
On Thu, Sep 13, 2012 at 07:37:46PM +0200, Stefan Weil wrote:
> The TCG targets no longer need individual implementations.
>
> Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,
> 'flags' is no longer used in tcg_target_get_call_iarg_regs_count.
>
> The remaining tcg_target_get_call_iarg_regs_
On Thu, Sep 13, 2012 at 07:37:45PM +0200, Stefan Weil wrote:
> 32 bit x86 hosts don't need registers for helper function arguments
> because they use the default stack based calling convention.
>
> Removing the registers allows simpler code for function
> tcg_target_get_call_iarg_regs_count.
>
>
From: Isaku Yamahata
Introduce a helper function which initializes the ahci port with ide devices.
It will be used by q35 support.
Cc: Alexander Graf
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/ide.h |3 +++
hw/ide/ahci.c | 16
2 files changed,
Rebase q35 to 1.2 - memory api updates, acpi updates, qom...
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 65
hw/acpi_ich9.h |9 +-
hw/pc.h|2 +
hw/pc_piix.c |4 +-
hw/pc_q35.c| 189 +++---
hw/q35.c | 477 +++
Add piix style acpi hotplug to q35.
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 173 +++-
hw/acpi_ich9.h | 10 +++
2 files changed, 182 insertions(+), 1 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 570ce0c..ba463a0 10
From: Isaku Yamahata
Pass opaque argument to pci_map_irq_fn like pci_set_irq_fn.
ICH9 irq routing is not static, but configurable by chipset configuration
registers, so the corresponding irq mapping function of pci_map_irq_fn
needs to know the pointer to ich9.
[jba...@redhat.com: minor tweaks]
S
From: Isaku Yamahata
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jba...@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |1 +
hw/pam.c | 121 +
From: Isaku Yamahata
This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.
Reported-by: Jan Kiszka
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/q3
From: Jan Kiszka
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pc_q35.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 9d58519..b8c1196 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -69,6 +69,7 @@
#include "mc146818rtc.
From: Jan Kiszka
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pci.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 55e4ad3..3727afa 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1203,6 +1203,7 @@ static const pci_class_desc pci_clas
From: Isaku Yamahata
Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c | 1
From: Isaku Yamahata
Adds pci id constants which will be used by q35.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci_ids.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 301bf1c..6deeac0 100644
--- a/hw/pci_ids.
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Signed-off-by: Jason Baron
---
hw/pc.c | 24
hw/pc.h |2 ++
hw/pc_piix.c | 25 +
3 files changed, 27 insertions(+), 24
If -L is specified, and qemu does not find the bios file in , then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Signed-off-by: Jason Baron
---
vl.c | 28 +---
1 files changed, 21 insertions(+
"Michael S. Tsirkin" writes:
> On Tue, Sep 11, 2012 at 01:00:13PM -0400, Don Slutz wrote:
>> +if (next_chain_offset) {
>> +MptSGEntryChain sgec;
>> +cpu_physical_memory_read(seg_start_pa + next_chain_offset,
>> +&sgec, sizeof(Mpt
The Advanced Error Interrupt Message Number (bits 31:27 of the Root
Error Status Register) is updated when the number of msi messages assigned to a
device changes. Migration of windows 7 on q35 chipset failed because the check
in get_pci_config_device() fails due to cmask being set on these bits. I
Add support for ahci migration. This patch builds upon the patches originally
posted by Andreas Färber.
These patches have been tested by migrating Windows 7 and Fedora 16 guests on
both piix with ahci attached and on q35 (which has a built-in ahci controller).
Signed-off-by: Andreas Färber
Cc:
From: Isaku Yamahata
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pc.c | 15 +++
hw/pc.h |1 +
hw/pc_piix.c |
From: Isaku Yamahata
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 4d95984..b348596 1
From: Jan Kiszka
Both bits are added to the write-1-to-clear mask by default. As the
smbus device does not allow writes at all, we have to remove it from
that mask, also to avoid triggering a runtime assertion.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/q35_smbus.c |4 +++
On 09/13/2012 04:35 PM, Paolo Bonzini wrote:
> Il 13/09/2012 17:49, Jeff Cody ha scritto:
>> +typedef QSIMPLEQ_HEAD(BlockReopenQueue, BlockReopenQueueEntry)
>> BlockReopenQueue;
>> +
>> +typedef struct BDRVReopenState {
>> +BlockDriverState *bs;
>> +int flags;
>> +void *opaque;
>> +
Hi,
Qemu bits for q35 support, I'm posting the seabios changes separately. The
patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
qemu command line. Hopefully, we can make it the default for x86 at some future
point when we feel comfortable with it.
Since q35 patches have be
Let's use PCIExpressHost with QOM.
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 14 ++
hw/pcie_host.h |4
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index e2fd276..027ba05 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_hos
While testing q35, I found that windows 7 (specifically, windows 7 ultimate
with sp1 x64), wouldn't install because it can't find the cdrom or disk drive.
The failure message is: 'A required cd/dvd device driver is missing. If you
have a driver floppy disk, CD, DVD, or USB flash drive, please inser
From: Jan Kiszka
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi
Il 13/09/2012 21:44, Paolo Bonzini ha scritto:
> Il 13/09/2012 21:04, Jeff Cody ha scritto:
Perhaps we _should_ preserve that in bs->open_flags, while still using
the initial value of BDRV_O_CACHE_WB to initialize bs->enable_write_cache.
>> That would work. Part of the problem is that BD
Il 13/09/2012 17:49, Jeff Cody ha scritto:
> +typedef QSIMPLEQ_HEAD(BlockReopenQueue, BlockReopenQueueEntry)
> BlockReopenQueue;
> +
> +typedef struct BDRVReopenState {
> +BlockDriverState *bs;
> +int flags;
> +void *opaque;
> +BlockReopenQueue *queue;
Do we need the queue pointer
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron
---
hw/pc_q35.c | 26 ++
1 files changed, 26 insertions(+), 0 deletions(-)
diff
While testing q35 live migration, I found that the migration would abort with
the following error: "Unknown savevm section type 76".
The error is due to this check failing in 'vmstate_load_state()':
while(field->name) {
if ((field->field_exists &&
field->field_exists(opaq
From: Jan Kiszka
Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
an assertion.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/q35.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/q35.c b/hw/q35.c
index 09e8bd7..8b6a2e5 10
This allows q35 to pass/set the size of the pcie window in its update routine.
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 21 -
hw/pcie_host.h |8 +---
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index 28bbe7
On Tue, 2012-09-11 at 12:36 +0800, Asias He wrote:
> Hello Nicholas,
>
Hello Asias!
> On 09/07/2012 02:48 PM, Nicholas A. Bellinger wrote:
> > From: Nicholas Bellinger
> >
> > Hello Anthony & Co,
> >
> > This is the fourth installment to add host virtualized target support for
> > the mainlin
Enabled for all softmmu guests supporting PCI on Linux hosts. Note
that currently only x86 hosts have the kernel side VFIO IOMMU support
for this. PPC (g3beige) is the only non-x86 guest known to work.
ARM (veratile) hangs in firmware, others untested.
Signed-off-by: Alex Williamson
---
MAINT
Based on Linux as of 1a95620.
Signed-off-by: Alex Williamson
---
linux-headers/linux/vfio.h | 368
1 file changed, 368 insertions(+)
create mode 100644 linux-headers/linux/vfio.h
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
Signed-off-by: Alex Williamson
---
scripts/update-linux-headers.sh |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index a639c5b..605102f 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update-lin
Here's an updated version of the VFIO PCI device assignment series.
Now that we're targetting QEMU 1.3, I've opened up support so that
vfio-pci is added to all softmmu targets supporting PCI on Linux
hosts. Only some printf format changes were required to make this
build.
I also added a workaroun
Gleb Natapov writes:
>> That's a bug.
>>
>> The next period calculation should not be based on the last period +
>> length of period but rather on the current time + delta to next period
>> boundary.
>>
> I disagree that this is a bug. This is by design to account for timer
> signals that was d
Jan Kiszka a écrit :
On 2012-09-13 07:55, Hervé Poussineau wrote:
This option is described in RFC 1783. As this is only an optional field,
we may ignore it in some situations and handle it in some others.
However, MS Windows 2003 PXE boot client requests a block size of the MTU
(most of the tim
Argh. And of course I send out the version from _before_ the compile test,
instead of the one after! I am not used to caffeine any more and have had
way too much tea...
---8<---
Make the "skip ahead" logic in compaction resistant to compaction
wrapping around to the end of the zone. This can lea
On Wed, 12 Sep 2012 17:46:15 +0100
Richard Davies wrote:
> Mel Gorman wrote:
> > I see that this is an old-ish bug but I did not read the full history.
> > Is it now booting faster than 3.5.0 was? I'm asking because I'm
> > interested to see if commit c67fe375 helped your particular case.
>
> Yes
Make the "skip ahead" logic in compaction resistant to compaction
wrapping around to the end of the zone. This can lead to less
efficient compaction when one thread has wrapped around to the
end of the zone, and another simultaneous compactor has not done
so yet. However, it should ensure that we
Il 13/09/2012 21:04, Jeff Cody ha scritto:
>> > Perhaps we _should_ preserve that in bs->open_flags, while still using
>> > the initial value of BDRV_O_CACHE_WB to initialize bs->enable_write_cache.
> That would work. Part of the problem is that BDRV_O_CACHE_WB seems
> overloaded; maybe bdrv_parse
On 09/13/2012 02:53 PM, Paolo Bonzini wrote:
> Il 13/09/2012 19:02, Jeff Cody ha scritto:
>> I kept the stubs for them for completeness,
>> however (I can remove them if that causes heartburn for others).
>
> The point of making them optional is to avoid stubs, isn't it? ;)
>
> Paolo
>
Fair poi
On 09/13/2012 02:56 PM, Paolo Bonzini wrote:
> Il 13/09/2012 19:17, Jeff Cody ha scritto:
Why does this matter? If raw-posix was opened directly (i.e. without
the bs->file indirection) this would cause a writethrough file to be
incorrectly opened as writeback.
Paolo
>
Changes from v2:
- remove the use of getnameinfo
- remove errp for inet_connect_addr
- remove QemuOpt "block"
- fix errors in wait_for_connect
- pass ConnectState as a parameter to allow concurrent connect ops
getaddrinfo can give us a list of addresses, bu
No need to add non blocking parameters to the blocking inet_connect
add block parameter for inet_connect_opts instead of using QemuOpt "block".
Signed-off-by: Orit Wasserman
---
migration-tcp.c |2 +-
nbd.c |2 +-
qemu-char.c |2 +-
qemu-sockets.c | 28 ++
getaddrinfo can give us a list of addresses, but we only try to
connect to the first one. If that fails we never proceed to
the next one. This is common on desktop setups that often have ipv6
configured but not actually working.
To fix this make inet_connect_nonblocking retry connection with a di
From: "Michael S. Tsirkin"
refactor address resolution code to fix nonblocking connect
remove getnameinfo call
Signed-off-by: Michael S. Tsirkin
Signed-off-by: Amos Kong
Signed-off-by: Orit Wasserman
---
qemu-sockets.c | 144 +++
1 files c
Il 13/09/2012 19:17, Jeff Cody ha scritto:
>> >
>> > Why does this matter? If raw-posix was opened directly (i.e. without
>> > the bs->file indirection) this would cause a writethrough file to be
>> > incorrectly opened as writeback.
>> >
>> > Paolo
>> >
> The problem this patch was trying to w
On Thu, Sep 13, 2012 at 01:33:31PM -0500, Anthony Liguori wrote:
> Gleb Natapov writes:
>
> > On Thu, Sep 13, 2012 at 10:56:56AM -0500, Anthony Liguori wrote:
> >> Gleb Natapov writes:
> >>
> >> > On Thu, Sep 13, 2012 at 09:35:18AM -0500, Anthony Liguori wrote:
> >> >> Gleb Natapov writes:
> >
Il 13/09/2012 19:02, Jeff Cody ha scritto:
> I kept the stubs for them for completeness,
> however (I can remove them if that causes heartburn for others).
The point of making them optional is to avoid stubs, isn't it? ;)
Paolo
On 09/12/12 13:55, Marcelo Tosatti wrote:
The problem with integrating this is that it has little or
no assurance from documentation. The Linux kernel source is a good
source, then say "accordingly to VMWare guest support code in version xyz"
in the changelog.
I will work on getting a list of the
Gleb Natapov writes:
> On Thu, Sep 13, 2012 at 10:56:56AM -0500, Anthony Liguori wrote:
>> Gleb Natapov writes:
>>
>> > On Thu, Sep 13, 2012 at 09:35:18AM -0500, Anthony Liguori wrote:
>> >> Gleb Natapov writes:
>> >>
>> >> > On Thu, Sep 13, 2012 at 09:06:29AM -0500, Anthony Liguori wrote:
>>
Avi Kivity writes:
> On 09/13/2012 06:50 PM, Anthony Liguori wrote:
> This may not work for really old server oriented guests.
S3 requires guest cooperation, period. But so does qemu-ga. It's
better than nothing, and we can't get perfection without guest cooperation.
>
On 09/13/2012 10:37 AM, Stefan Weil wrote:
> [PATCH 1/4] w64: Fix TCG helper functions with 5 arguments (unchanged)
> [PATCH 2/4] tcg/i386: Add shortcuts for registers used in L (new)
> [PATCH 3/4] tcg/i386: Remove unused registers from (unchanged)
> [PATCH 4/4] tcg: Remove tcg_target_get_call_iarg
The TCG targets no longer need individual implementations.
Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,
'flags' is no longer used in tcg_target_get_call_iarg_regs_count.
The remaining tcg_target_get_call_iarg_regs_count is trivial and only
called once. Therefore the patch eliminates it
While 64 bit hosts use the first three registers which are also used
as function input parameters, 32 bit hosts use TCG_REG_EAX and
TCG_REG_EDX which are not used in parameter passing.
After defining new register macros for the registers used in L
constraint, the patch replaces most occurrences of
TCG uses 6 registers for function arguments on 64 bit Linux hosts,
but only 4 registers on W64 hosts.
Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the number
of arguments for some important helper functions from 4 to 5
which triggered a bug for W64 hosts: QEMU aborts when executing
he
32 bit x86 hosts don't need registers for helper function arguments
because they use the default stack based calling convention.
Removing the registers allows simpler code for function
tcg_target_get_call_iarg_regs_count.
Signed-off-by: Stefan Weil
---
tcg/i386/tcg-target.c | 10 ++
1
These patches replace the 4 patches which I sent yesterday.
Thanks to Aurelien, Peter and Richard for their feedback.
Function tcg_target_get_call_iarg_regs_count was wrong for w64 hosts
and can be removed completely (no more implementations for each TCG target):
[PATCH 1/4] w64: Fix TCG helper
On 09/12/2012 11:33 PM, g...@snapgear.com wrote:
> +uint32_t HELPER(move_from_usp)(CPUM68KState * env)
> +{
> +return env->sp[M68K_USP];
> +}
You don't need helpers for these.
> DISAS_INSN(move_from_usp)
> {
> +TCGv reg;
> if (IS_USER(s)) {
> gen_exception(s, s->pc - 2, EX
On 09/13/2012 09:49 AM, Jeff Cody wrote:
> Code motion, to move allocating aligned_buf and setting aligned_buf_size
> into a helper function.
>
> Signed-off-by: Jeff Cody
> ---
> block/raw-posix.c | 31 ++-
> 1 file changed, 22 insertions(+), 9 deletions(-)
>
> +
On 09/13/2012 04:22 PM, Markus Armbruster wrote:
> Orit Wasserman writes:
>
>> getaddrinfo can give us a list of addresses, but we only try to
>> connect to the first one. If that fails we never proceed to
>> the next one. This is common on desktop setups that often have ipv6
>> configured but n
On 09/13/2012 12:12 PM, Paolo Bonzini wrote:
> Il 13/09/2012 17:49, Jeff Cody ha scritto:
>> Block drivers should always open the files in writeback mode (see commit
>> e1e9b0ac), so raw-posix/raw-win32 should not parse the BDRV_O_CACHE_WB
>> flag.
>>
>> Signed-off-by: Jeff Cody
>> ---
>> block/r
On 09/13/2012 08:58 AM, Christian Theune wrote:
> I saw that 0.13 does have block migration available. However, looking at
> the code, it's an "either or" situation: migrate all block devices or none.
Migrating disks during live migration has proven to be hard to get
right; the current code is mo
On 09/12/12 02:58, Gerhard Wiesinger wrote:
On 11.09.2012 19:00, Don Slutz wrote:
Add LSI53C1030, SAS1068, SAS1068e. Based on code from "VirtualBox
Open Source Edition".
Based on QEMU MegaRAID SAS 8708EM2.
This is a common VMware disk controller.
SEABIOS change for booting is in the works.
On 09/13/2012 12:05 PM, Paolo Bonzini wrote:
> Il 13/09/2012 17:49, Jeff Cody ha scritto:
>> +/* We have nothing to do for raw reopen, stubs just return
>> + * success */
>> +static int raw_reopen_prepare(BDRVReopenState *state, Error **errp)
>> +{
>> +return 0;
>> +}
>> +
>> +static void raw_r
On 09/13/2012 12:02 PM, Paolo Bonzini wrote:
> Il 13/09/2012 17:49, Jeff Cody ha scritto:
>> +
>> +/*
>> + * If we didn't have BDRV_O_NOCACHE set before, we may not have
>> allocated
>> + * aligned_buf
>> + */
>> +ret = raw_allocate_aligned_buf(&raw_s->aligned_buf,
>> +
On 09/13/2012 03:35 PM, Markus Armbruster wrote:
> Orit Wasserman writes:
>
>> From: Michael S. Tsirkin
>>
>> refactor address resolution code to fix nonblocking connect
>>
>> Signed-off-by: Michael S. Tsirkin
>> Signed-off-by: Amos Kong
>> Signed-off-by: Orit Wasserman
>> ---
>> qemu-socket
Code motion, to move allocating aligned_buf and setting aligned_buf_size
into a helper function.
Signed-off-by: Jeff Cody
---
block/raw-posix.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/block/raw-posix.c b/block/raw-posix.c
index 4a1047c
Avi Kivity writes:
> On 09/13/2012 05:42 PM, Eric Blake wrote:
>> On 09/13/2012 08:34 AM, Avi Kivity wrote:
>>> On 09/13/2012 05:22 PM, Gleb Natapov wrote:
>
> It's much easier for us to call into qemu-ga to do the time correction
> whenever this event occurs than to try and have libv
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