Re: [PATCH] hw/nvme: fix handling of over-committed queues

On Oct 28 09:15, Keith Busch wrote: > On Mon, Oct 28, 2024 at 10:01:50AM +0100, Klaus Jensen wrote: > > On Oct 25 10:45, Keith Busch wrote: > > > On Fri, Oct 25, 2024 at 12:50:45PM +0200, Klaus Jensen wrote: > > > > @@ -1520,9 +1520,16 @@ static void nvme_post_cqes(void *opaque) > > > > nv

[PATCH v2] hw/nvme: fix handling of over-committed queues

From: Klaus Jensen If a host chooses to use the SQHD "hint" in the CQE to know if there is room in the submission queue for additional commands, it may result in a situation where there are not enough internal resources (struct NvmeRequest) available to process the command. For a lack of a better

Re: [PATCH] hw/sd/sdcard: Fix calculation of size when using eMMC boot partitions

On 10/28/24 17:23, Jan Luebbe wrote: The sd_bootpart_offset() function calculates the *runtime* offset which changes as the guest switches between accessing the main user data area and the boot partitions by writing to the EXT_CSD_PART_CONFIG_ACC_MASK bits, so it shouldn't be used to calculate th

Re: [PATCH v3 3/7] qapi: block-job-change: make copy-mode parameter optional

On 22.10.24 15:35, Kevin Wolf wrote: Am 02.10.2024 um 16:06 hat Vladimir Sementsov-Ogievskiy geschrieben: We are going to add more parameters to change. We want to make possible to change only one or any subset of available options. So all the options should be optional. Signed-off-by: Vladimir

[PATCH v5 09/15] gpex: Allow more than 4 legacy IRQs

From: Alexander Graf Some boards such as vmapple don't do real legacy PCI IRQ swizzling. Instead, they just keep allocating more board IRQ lines for each new legacy IRQ. Let's support that mode by giving instantiators a new "nr_irqs" property they can use to support more than 4 legacy IRQ lines.

[PATCH v5 00/15] macOS PV Graphics and new vmapple machine type

This patch set introduces a new ARM and macOS HVF specific machine type called "vmapple", as well as a family of display devices based on the ParavirtualizedGraphics.framework in macOS. One of the display adapter variants, apple-gfx-mmio, is required for the new machine type, while apple-gfx-pci ca

[PATCH v5 03/15] hw/display/apple-gfx: Adds PCI implementation

This change wires up the PCI variant of the paravirtualised graphics device, mainly useful for x86-64 macOS guests, implemented by macOS's ParavirtualizedGraphics.framework. It builds on code shared with the vmapple/mmio variant of the PVG device. Signed-off-by: Phil Dennis-Jordan --- v4: * Th

[PATCH v5 12/15] hw/vmapple/cfg: Introduce vmapple cfg region

From: Alexander Graf Instead of device tree or other more standardized means, VMApple passes platform configuration to the first stage boot loader in a binary encoded format that resides at a dedicated RAM region in physical address space. This patch models this configuration space as a qdev dev

[PATCH v5 10/15] hw/vmapple/aes: Introduce aes engine

From: Alexander Graf VMApple contains an "aes" engine device that it uses to encrypt and decrypt its nvram. It has trivial hard coded keys it uses for that purpose. Add device emulation for this device model. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jordan --- v3: * Rebased

[PATCH v5 11/15] hw/vmapple/bdif: Introduce vmapple backdoor interface

From: Alexander Graf The VMApple machine exposes AUX and ROOT block devices (as well as USB OTG emulation) via virtio-pci as well as a special, simple backdoor platform device. This patch implements this backdoor platform device to the best of my understanding. I left out any USB OTG parts; they

[PATCH v5 01/15] ui & main loop: Redesign of system-specific main thread event handling

macOS's Cocoa event handling must be done on the initial (main) thread of the process. Furthermore, if library or application code uses libdispatch, the main dispatch queue must be handling events on the main thread as well. So far, this has affected Qemu in both the Cocoa and SDL UIs, although in

[PATCH v5 06/15] hw: Add vmapple subdir

From: Alexander Graf We will introduce a number of devices that are specific to the vmapple target machine. To keep them all tidily together, let's put them into a single target directory. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jordan Reviewed-by: Akihiko Odaki --- MAINTAIN

[PATCH v5 14/15] hw/block/virtio-blk: Replaces request free function with g_free

The virtio_blk_free_request() function has been a 1-liner forwarding to g_free() for a while now. We may as well call g_free on the request pointer directly. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Akihiko Odaki --- hw/block/virtio-blk.c | 43 +++---

Re: [PATCH v1 3/8] hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600

On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote: > According to the datasheet of AST2600 description, interrupt status > set by HW > and clear to "0" by software writing "1" on the specific bit. > > Therefore, if firmware set the specific bit "1" in the interrupt > status > register(0x34), the

Re: [PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin inverted property

On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote: > The Write Protect pin of SDHCI model is default active low to match > the SDHCI > spec. So, write enable the bit 19 should be 1 and write protected the > bit 19 > should be 0 at the Present State Register (0x24). However, some board > are > desi

[PATCH v5 08/15] hvf: arm: Ignore writes to CNTP_CTL_EL0

From: Alexander Graf MacOS unconditionally disables interrupts of the physical timer on boot and then continues to use the virtual one. We don't really want to support a full physical timer emulation, so let's just ignore those writes. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jo

Re: [PATCH v4 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On Tue, 29 Oct 2024 at 08:42, Akihiko Odaki wrote: > On 2024/10/29 6:06, Phil Dennis-Jordan wrote: > > > > > > On Mon, 28 Oct 2024 at 17:06, Akihiko Odaki > > wrote: > > > > On 2024/10/28 23:13, Phil Dennis-Jordan wrote: > > > > > > > > > On Mo

[PATCH v5 05/15] MAINTAINERS: Add myself as maintainer for apple-gfx, reviewer for HVF

I'm happy to take responsibility for the macOS PV graphics code. As HVF patches don't seem to get much attention at the moment, I'm also adding myself as designated reviewer for HVF and x86 HVF to try and improve that. I anticipate that the resulting workload should be covered by the funding I'm r

[PATCH v5 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

MacOS provides a framework (library) that allows any vmm to implement a paravirtualized 3d graphics passthrough to the host metal stack called ParavirtualizedGraphics.Framework (PVG). The library abstracts away almost every aspect of the paravirtualized device model and only provides and receives c

[PATCH v5 15/15] hw/vmapple/vmapple: Add vmapple machine type

From: Alexander Graf Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device additions and a vastly different boot chain. This

RE: [PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin inverted property

Hi Andrew, > Subject: Re: [PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin > inverted property > > On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote: > > The Write Protect pin of SDHCI model is default active low to match > > the SDHCI spec. So, write enable the bit 19 should be

Re: [PATCH v1 7/8] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs

On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote: > The Write Protect pin of SDHCI model is default active low to match > the SDHCI > spec. So, write enable the bit 19 should be 1 and write protected the > bit 19 > should be 0 at the Present State Register (0x24). > > According to the design of

Re: [PATCH v3 00/14] macOS PV Graphics and new vmapple machine type

On Thu, 3 Oct 2024 at 10:06, Alex Bennée wrote: > > > There are currently a few limitations to this which aren't intrinsic, > > just imperfect emulation of the VZF, but it's good enough to be just > > about usable for some purposes: > > > > * macOS 12 guests only. Versions 13+ currently fail dur

[PATCH v5 04/15] hw/display/apple-gfx: Adds configurable mode list

This change adds a property 'display_modes' on the graphics device which permits specifying a list of display modes. (screen resolution and refresh rate) The property is an array of a custom type to make the syntax slightly less awkward to use, for example: -device '{"driver":"apple-gfx-pci", "di

[PATCH v5 07/15] hw/misc/pvpanic: Add MMIO interface

From: Alexander Graf In addition to the ISA and PCI variants of pvpanic, let's add an MMIO platform device that we can use in embedded arm environments. Signed-off-by: Alexander Graf Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Phil Dennis-Jordan Revie

[PATCH v5 13/15] hw/vmapple/virtio-blk: Add support for apple virtio-blk

From: Alexander Graf Apple has its own virtio-blk PCI device ID where it deviates from the official virtio-pci spec slightly: It puts a new "apple type" field at a static offset in config space and introduces a new barrier command. This patch first creates a mechanism for virtio-blk downstream c

RE: [PATCH v1 7/8] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs

Hi Andrew, > Subject: Re: [PATCH v1 7/8] hw/arm/aspeed: Invert sdhci write protected pin > for AST2600 and AST2500 EVBs > > On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote: > > The Write Protect pin of SDHCI model is default active low to match > > the SDHCI spec. So, write enable the bit 19 s

Re: [PATCH 0/2] arm: Add collie and sx functional tests

On 10/28/24 01:41, Jan Lübbe wrote: On Sun, 2024-10-27 at 20:32 -0700, Guenter Roeck wrote: On 10/27/24 15:26, Cédric Le Goater wrote: On 10/27/24 23:11, Guenter Roeck wrote: On 10/27/24 14:13, Cédric Le Goater wrote: On 10/26/24 17:32, Guenter Roeck wrote: On 10/26/24 03:02, Cédric Le Goate

Re: [PATCH] hw/sd/sdcard: Allow user creation of eMMCs

On Fri, 18 Oct 2024 at 16:42, Peter Maydell wrote: > > On Tue, 15 Oct 2024 at 14:57, Jan Luebbe wrote: > > > > For testing eMMC-specific functionality (such as handling boot > > partitions), it would be very useful to attach them to generic VMs such > > as x86_64 via the sdhci-pci device: > > ..

Re: [PATCH v4 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On 2024/10/29 6:06, Phil Dennis-Jordan wrote: On Mon, 28 Oct 2024 at 17:06, Akihiko Odaki > wrote: On 2024/10/28 23:13, Phil Dennis-Jordan wrote: > > > On Mon, 28 Oct 2024 at 15:02, Akihiko Odaki mailto:akihiko.od...@daynix.com> > <

[PATCH v1 0/8] Support RTC for AST2700

change from v1: 1. Support RTC for AST2700. 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. 3. Introduce Capabilities Register 2 for SD slot 0 and 1. 4. Support create flash devices via command line for AST1030. Jamin Lin (8): aspeed/soc: Support RTC for AST2700 hw/timer

[PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin inverted property

The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some board are design Write Protected pin active high. In other words, write enable t

[PATCH v1 7/8] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs

The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2500 and AST2600 EVBs, the Write Protected pin is active high b

[PATCH v1 4/8] hw/sd/sdhci: Fix coding style

Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin --- hw/sd/sdhci.c | 64 +-- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..db7d547156 100644 --- a/hw/sd/sdhci.c ++

[PATCH v1 3/8] hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600

According to the datasheet of AST2600 description, interrupt status set by HW and clear to "0" by software writing "1" on the specific bit. Therefore, if firmware set the specific bit "1" in the interrupt status register(0x34), the specific bit of "s->irq_sts" should be cleared 0. Signed-off-by:

[PATCH v1 1/8] aspeed/soc: Support RTC for AST2700

The RTC controller between AST2600 and AST2700 are identical. Add RTC model for AST2700 RTC support. The RTC controller registers base address is start at 0x12C0_F000 and its alarm interrupt is connected to GICINT13. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 11 +++ 1 file c

[PATCH v1 2/8] hw/timer/aspeed: Fix coding style

Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin --- hw/timer/aspeed_timer.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index b1f860ecfb..5af268ea9e 100644 --- a/hw/timer/aspeed_timer.c ++

[PATCH v1 6/8] hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1

The size of SDHCI capabilities register is 64bits, so introduces new Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244). Signed-off-by: Jamin Lin --- hw/sd/aspeed_sdhci.c | 40 +--- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git

[PATCH v1 8/8] aspeed: Support create flash devices via command line for AST1030

Add a "if-statement" in aspeed_minibmc_machine_init function. If users add "-nodefaults" in command line, the flash devices should be created by users setting. Otherwise, the flash devices are created at machine init. Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 22 -- 1 fi

Re: [PATCH v6 0/3] hw/{i2c,nvme}: mctp endpoint, nvme management interface model

On Oct 14 10:36, Jonathan Cameron via wrote: > On Wed, 20 Sep 2023 09:36:34 -0500 > Corey Minyard wrote: > > > On Wed, Sep 20, 2023 at 06:31:25AM -0700, Klaus Jensen wrote: > > > On Sep 20 07:54, Corey Minyard wrote: > > > > On Wed, Sep 20, 2023 at 12:48:03PM +0100, Jonathan Cameron via wrote: