On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote:
> According to the datasheet of AST2600 description, interrupt status
> set by HW
> and clear to "0" by software writing "1" on the specific bit.
>
> Therefore, if firmware set the specific bit "1" in the interrupt
> status
> register(0x34), the specific bit of "s->irq_sts" should be cleared 0.
>
> Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Hah, the datasheet table for the register uses `RW` to describe the
bits and not `W1C`, but there's a foot-note in the table that says
they're W1C bits.
Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on the
AST2600")
Reviewed-by: Andrew Jeffery <and...@codeconstruct.com.au>
Thanks,
Andrew
