e/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> index cbeacb214c..879bdb96ee 100644
> --- a/include/hw/arm/aspeed.h
> +++ b/include/hw/arm/aspeed.h
> @@ -39,6 +39,7 @@ struct AspeedMachineClass {
> uint32_t macs_mask;
> void (*i2c_init)(AspeedMachineState *bmc);
> uint32_t uart_default;
> + bool sdhci_wp_invert;
Other than also calling this `sdhci_wp_inverted` to match my comment on
the earlier patch about the model property and devicetree bindings,
Reviewed-by: Andrew Jeffery
On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote:
> The Write Protect pin of SDHCI model is default active low to match
> the SDHCI
> spec. So, write enable the bit 19 should be 1 and write protected the
> bit 19
> should be 0 at the Present State Register (0x24). However, some board
> are
> desi
x27;re W1C bits.
Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on the
AST2600")
Reviewed-by: Andrew Jeffery
Thanks,
Andrew
On Mon, 2024-10-21 at 14:39 +0200, Cédric Le Goater wrote:
> On 10/18/24 07:31, Jamin Lin wrote:
> > Currently, these test cases used the hardcode offset 0x140 (0x14000 *
> > 256)
> > which was beyond the 16MB flash size for flash page read/write command
> > testing.
> > However, the default
ation :)
Reviewed-by: Andrew Jeffery
> ---
> hw/i2c/smbus_master.c | 26 ++
> include/hw/i2c/smbus_master.h | 2 ++
> 2 files changed, 28 insertions(+)
>
> diff --git a/hw/i2c/smbus_master.c b/hw/i2c/smbus_master.c
> index 6a53c3
@huawei.com/
> [2]:
> https://lore.kernel.org/qemu-devel/20221121080445.ga29...@codeconstruct.com.au/
>
> Tested-by: Jonathan Cameron
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Klaus Jensen
Nice!
Reviewed-by: Andrew Jeffery
fprintf(stderr, "nmi command 0x%x not handled\n", request->opc);
> +
> +break;
> +}
> +}
> +
> +static void nmi_reset(MCTPI2CEndpoint *mctp)
> +{
> +NMIDevice *nmi = NMI_I2C_DEVICE(mctp);
> +nmi->len = 0;
> +}
> +
>
Hi Klaus,
On Thu, 2023-09-14 at 08:51 +0200, Klaus Jensen wrote:
> On Sep 12 13:50, Andrew Jeffery wrote:
> > Hi Klaus,
> >
> > On Tue, 2023-09-05 at 10:38 +0200, Klaus Jensen wrote:
> > > >
> > > > +static void nmi_handle_mi_config_ge
Hi Klaus,
On Tue, 2023-09-05 at 10:38 +0200, Klaus Jensen wrote:
> >
> > +static void nmi_handle_mi_config_get(NMIDevice *nmi, NMIRequest
> > *request)
> > +{
> > + uint32_t dw0 = le32_to_cpu(request->dw0);
> > + uint8_t identifier = FIELD_EX32(dw0,
> > NMI_CMD_CONFIGURATION_GET_DW0,
> > +
On Sun, 31 Jul 2022, at 06:48, Cédric Le Goater wrote:
> On 7/29/22 19:30, Peter Delevoryas wrote:
>> Certainly we'd like to use IRQ's instead, but she ran into correctness
>> problems. Maybe we can investigate that further and fix it.
Yes, let's not work around problems that we have the abilit
On Mon, 25 Jul 2022, at 16:02, Cédric Le Goater wrote:
> On 7/25/22 04:08, Andrew Jeffery wrote:
>>
>>
>> On Fri, 22 Jul 2022, at 16:06, Cédric Le Goater wrote:
>>> aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
>>> mc-&
On Fri, 22 Jul 2022, at 16:06, Cédric Le Goater wrote:
> A mx25l25635f chip model is generally found on these machines. It's
> newer and uses 4B opcodes which is better to exercise the support in
> the Linux kernel.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/arm/aspeed.c | 6 +++---
> 1 fi
On Mon, 22 Jun 2020, at 18:13, Philippe Mathieu-Daudé wrote:
> On 6/22/20 2:21 AM, Andrew Jeffery wrote:
> > On Wed, 17 Jun 2020, at 13:11, Philippe Mathieu-Daudé wrote:
> >> Hi Andrew,
> >>
> >> On 6/17/20 3:18 AM, Andrew Jeffery wrote:
> >>>
On Wed, 17 Jun 2020, at 13:11, Philippe Mathieu-Daudé wrote:
> Hi Andrew,
>
> On 6/17/20 3:18 AM, Andrew Jeffery wrote:
> > On Tue, 16 Jun 2020, at 17:21, Philippe Mathieu-Daudé wrote:
> >> The current implementation uses nano-second precision, while
> >> the
On Tue, 16 Jun 2020, at 17:21, Philippe Mathieu-Daudé wrote:
> The current implementation uses nano-second precision, while
> the watchdog can not be more precise than a micro-second.
What's the basis for this assertion? It's true for the AST2500 and AST2600, but
the AST2400 can run the watchd
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