On Jul 29, 11:23 pm, Henrique Dante de Almeida <[EMAIL PROTECTED]>
wrote:
> On Jul 28, 6:49 pm, Svenn Are Bjerkem <[EMAIL PROTECTED]>
> wrote:
>
>
>
> > Hi again,
>
> > when I get far enough to parse the VHDL (which is not currently the
> > fact, but I have to look at the work coming up downstream)
On Jul 28, 6:49 pm, Svenn Are Bjerkem <[EMAIL PROTECTED]>
wrote:
> Hi again,
>
> when I get far enough to parse the VHDL (which is not currently the
> fact, but I have to look at the work coming up downstream) I will have
> to put it into an internal data structure and then write some classes
> to
On Jul 21, 12:09 pm, Svenn Are Bjerkem <[EMAIL PROTECTED]>
wrote:
> Hi,
> I am in the need to write an application for PyQt to visualise the
> structure of a VHDL project I am working on. Looking for a sensible
> way to parse VHDL files and putting them into a data structure that
> PyQt can represe
On Jul 29, 5:14 pm, Wolfgang Grafen <[EMAIL PROTECTED]>
wrote:
> For me it is not very clear what you intend to do. After years of
> parsing parts of VHDL from time to time the rapid parsing way for me is
> using regular expressions instead of one of the parser frame works
> because of following r
Svenn Are Bjerkem schrieb:
Hi again,
when I get far enough to parse the VHDL (which is not currently the
fact, but I have to look at the work coming up downstream) I will have
to put it into an internal data structure and then write some classes
to handle the MVC between whatever data I have and
Hi again,
when I get far enough to parse the VHDL (which is not currently the
fact, but I have to look at the work coming up downstream) I will have
to put it into an internal data structure and then write some classes
to handle the MVC between whatever data I have and the PyQt4 widget
that is goi
On Jul 23, 1:03 pm, [EMAIL PROTECTED] (c d saunter)
wrote:
> How much of VHDL are you looking to parse? Are you just looking at files
> intended for synthesis, or at simulation/testbench files as well?
As a start I want to parse VHDL which is going to be synthesised, and
I am limiting myself to t
Svenn Are Bjerkem ([EMAIL PROTECTED]) wrote:
: Hi,
: I am in the need to write an application for PyQt to visualise the
: structure of a VHDL project I am working on. Looking for a sensible
: way to parse VHDL files and putting them into a data structure that
: PyQt can represent as a tree (or what
Hi,
I am in the need to write an application for PyQt to visualise the
structure of a VHDL project I am working on. Looking for a sensible
way to parse VHDL files and putting them into a data structure that
PyQt can represent as a tree (or whatever the MVC is supporting)
through search engines does
