On Jul 29, 5:14 pm, Wolfgang Grafen <[EMAIL PROTECTED]> wrote: > For me it is not very clear what you intend to do. After years of > parsing parts of VHDL from time to time the rapid parsing way for me is > using regular expressions instead of one of the parser frame works > because of following reasons: > > - It is hard for me to understand those frameworks > - They are very slow > - It is too much work for me to bring them up to work in a sensible way > - Compared with regular expression matching they usually need a lot of > extra work.
I agree with frameworks being difficult to understand and that is why I also have been using regular expressions in tcl to parse spice netlists before. Now I want to parse spice, vhdl and also maybe verilog. I think I will end up with regular expressions unless I get a grip on SimpleParse. The rationale for the whole project has been to finally be able to view spice and specially vhdl code for projects I work on. This has been something I have wanted to have for years, without having the ressources to complete it. There are commercial tools available, but I was looking for something more open/free that could be maintained independently of what tools I have at work. > PyQt as a widget framework is not useful until here, but of course you > could display your results in arbitrary graphical ways with PyQt, if you > rally need to. You should know, printing out an ASCII or XML > representation is so much more easy and quicker to code so I always > prefer that. There are even editors/visualizers ready to display XML... PyQt4 doesn't help me parse my sources, but it helps me visualise them. I did something in tcl/tk to get hierarchical spice netlists into a tree structure, but extending that app was too much hassle. PyQt4 offers a lot of functionality once the threshold of learning it has been passed. It also installs nicely on windows and most linux distributions offer it ready to install. And I like Qt. -- Svenn -- http://mail.python.org/mailman/listinfo/python-list
