In article <4b9f7414$0$2887$ba620...@news.skynet.be>,
Jan Decaluwe wrote:
>
>I am proud to report on the first ASIC product designed with MyHDL
>(afaik).
>
>http://www.jandecaluwe.com/hdldesign/digmac.html
Congrats!
--
Aahz (a...@pythoncraft.com)
I am proud to report on the first ASIC product
designed with MyHDL (afaik).
http://www.jandecaluwe.com/hdldesign/digmac.html
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design
Stef Mientki wrote:
hello Jan,
Jan Decaluwe wrote:
Hello:
MyHDL is a Python package for using Python as a
Hardware Description Language.
A new release is upcoming, and on this occasion
we have prepared a page about why MyHDL may
be useful to you:
http://www.myhdl.org/doku.php/why
Very
hello Jan,
Jan Decaluwe wrote:
Hello:
MyHDL is a Python package for using Python as a
Hardware Description Language.
A new release is upcoming, and on this occasion
we have prepared a page about why MyHDL may
be useful to you:
http://www.myhdl.org/doku.php/why
Very Interesting,
I'
Hello:
MyHDL is a Python package for using Python as a
Hardware Description Language.
A new release is upcoming, and on this occasion
we have prepared a page about why MyHDL may
be useful to you:
http://www.myhdl.org/doku.php/why
Regards,
Jan
--
Jan Decaluwe - Resources bvba - http
Dear Mr. Polo,
Yes, I believe that there may indeed be a problem with MyHDL module
running under python 2.5 under the windows environment. I have been
having extensive problems with importing the MyHDL module. I will
provide additional information if required. Thank you very much for all
of
From: Dan Fabrizio [mailto:[EMAIL PROTECTED]
Sent: Friday, February 08, 2008 2:56 PM
To: Blubaugh, David A.
Subject: Re: MyHDL project !
David,
No problem with the mailing list, others might have some experience that
could be useful. Let me know how
On 2008-02-08, Dan Upton <[EMAIL PROTECTED]> wrote:
> I don't know, I'm inclined to agree with him. Repeatedly
> replying to bash his use of grammar or punctuation is
> unnecessary. Replying to the list to mock repeatedly is
> doubly unnecessary.
While c.l.p is exceptionally polite and tolerant
On Feb 7, 2008 8:59 PM, ajaksu <[EMAIL PROTECTED]> wrote:
> On Feb 7, 10:05 pm, "Blubaugh, David A." <[EMAIL PROTECTED]> wrote:
> > I do not understand why people such as yourself cannot construct
> > anything but insults and complaints.
>
> I can help with that. People asked politely a few days ag
On Feb 7, 10:05 pm, "Blubaugh, David A." <[EMAIL PROTECTED]> wrote:
> I do not understand why people such as yourself cannot construct
> anything but insults and complaints.
I can help with that. People asked politely a few days ago. Didn't you
see it? It happens because you're not following basic
ridiculous at best. thanks.
David
-Original Message-
From: ajaksu [mailto:[EMAIL PROTECTED]
Sent: Thursday, February 07, 2008 5:49 PM
To: python-list@python.org
Subject: Re: Dear David (was: MyHDL project)
On Feb 7, 4:48 pm, "Blubaugh, David A." <[EMAIL PROTECTED]&g
On Feb 7, 4:48 pm, "Blubaugh, David A." <[EMAIL PROTECTED]> wrote:
> sir,
>
> Is there still a possibility to collaborate???
>
> David Blubaugh
Dear David A. Blubaugh,
Could you please make it a little less painful to read your messages?
You're giving a bad name to Belcan, too.
Daniel
--
http:/
sir,
Is there still a possibility to collaborate???
David Blubaugh
-Original Message-
From: Blubaugh, David A.
Sent: Friday, February 01, 2008 10:44 AM
To: 'chewie54'
Cc: 'python-list@python.org'
Subject: MyHDL project !
Dan,
I would be honored to sta
edded processors ,such as the Power PC on Xilinx FPGAS. I believe
that a marriage between Python, ImpulseC, MyHDL, SciPy, Gene Expression
Programming, and GNU Plot will develop into a very interesting and
powerful algorithm development environment for FPGAS. I will also need
a way to develop flo
On 2008-02-01, Blubaugh, David A. <[EMAIL PROTECTED]> wrote:
> I would be honored to start a project such as that in mind.
> How do we begin ??
You need to get the punctuation keys on your keyboard fixed.
They're sticking, and it's making your posts look like they
come from a hyperactive 4th
chewie54 wrote:
>> Dan,
>>
>> I would be honored to start a project such as that in mind. How do we
>> begin ??
>>
>> David Blubaugh
>>
>>
>> Why not use MyHDL which is written in Python and translates to Verilog.
>> I assume Impulse
> Dan,
>
> I would be honored to start a project such as that in mind. How do we
> begin ??
>
> David Blubaugh
>
>
> Why not use MyHDL which is written in Python and translates to Verilog.
> I assume ImpulseC is a commercial product and costs a log. MyHD
sters thesis. Is anyone willing to help in this
endeavor?
>
> David Blubaugh
>
Why not use MyHDL which is written in Python and translates to Verilog.
I assume ImpulseC is a commercial product and costs a log. MyHDL is
free.
If you have any interests in combining MyHDL with SciPy a
Neal Becker wrote:
> I was not aware of MyHDL, sounds interesting.
>
> But, last release was May 2006. I wonder if it still active?
Certainly, but I'm so busy doing designs with it that
there 's no time for new releases :-)
Seriously, I'm working hard on conversion to V
I was not aware of MyHDL, sounds interesting.
But, last release was May 2006. I wonder if it still active?
--
http://mail.python.org/mailman/listinfo/python-list
rgely independent of the HDL you use.
The primary (and advertized) goal of MyHDL conversion to Verilog is
implementation through synthesis. However, succesful conversion
doesn't provide any guarantee on synthesizability. Indeed, the
convertor's constraints are much less severe than syn
a
>> feeling as to how much work would be needed for it to be synthesisable?
>
> This is a fairly "old" project (2003). At that time, MyHDL didn't
> yet have conversion to Verilog.
>
> After reviewing the code again, it's clear that it's written in
&g
Randall Parker wrote:
> Jan,
>
> What do you see as the main advantage for using MyHDL rather than VHDL
> for coding up a chip design?
The fact that MyHDL is technically just another Python application.
So it makes all typical Python advantages available to hardware
designers
Jan,
What do you see as the main advantage for using MyHDL rather than VHDL
for coding up a chip design?
--
http://mail.python.org/mailman/listinfo/python-list
Michael wrote:
> Jan Decaluwe wrote:
>
>
>>I'm pleased to announce the release of MyHDL 0.5.
>>
>>MyHDL is an open-source package for using Python as a hardware
>>description and verification language. Moreover, it can convert
>>a design to Verilog.
Jan Decaluwe wrote:
> I'm pleased to announce the release of MyHDL 0.5.
>
> MyHDL is an open-source package for using Python as a hardware
> description and verification language. Moreover, it can convert
> a design to Verilog. Thus, MyHDL provides a complete path
> from
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