> Dan, > > I would be honored to start a project such as that in mind. How do we > begin ?????? > > David Blubaugh > > > Why not use MyHDL which is written in Python and translates to Verilog. > I assume ImpulseC is a commercial product and costs a log. MyHDL is > free. > If you have any interests in combining MyHDL with SciPy and NumPy I > would be interested in getting involved. > > Dan Fabrizio >
David, Let's start by discussing your masters thesis subject in more detail. We can take a project from conception to hardware using MyHDL, NumPy and SciPy. Maybe you could use this project as a proof for your thesis showing this methodology warrants consideration compared other ASIC/FPGA flows. Let's discuss some of your ideas and decide how to proceed. Dan -- http://mail.python.org/mailman/listinfo/python-list
