Re: Generator Frustration

pong yield statements, but that solutions seems even uglier than having a very flat, single main routine with repeating sequences. In MyHDL, this is supported by the possibility to yield generators, which are then handled by the simulation engine. Jan -- Jan Decaluwe - Resources b

The first ASIC designed with MyHDL

I am proud to report on the first ASIC product designed with MyHDL (afaik). http://www.jandecaluwe.com/hdldesign/digmac.html -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design

Re: global name 'self' is not defined - noob trying to learn

ly set value. I'm really cornfused now. In the past, someone referred you to the intbv class in MyHDL. You mentioned that it does "more than you want". However, it seems to me that what intbv really does, is to solve the kind of issues that you are struggling with. Perhaps you want to

Integer arithmetic in hardware descriptions

x27;s native integer type, int. I have written an essay that explores these issues in detail: http://www.jandecaluwe.com/hdldesign/counting.html -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a hardware description language: http://www.myhdl.org -- http://mail.pytho

Re: Why MyHDL?

Stef Mientki wrote: hello Jan, Jan Decaluwe wrote: Hello: MyHDL is a Python package for using Python as a Hardware Description Language. A new release is upcoming, and on this occasion we have prepared a page about why MyHDL may be useful to you: http://www.myhdl.org/doku.php/why Very

Why MyHDL?

Hello: MyHDL is a Python package for using Python as a Hardware Description Language. A new release is upcoming, and on this occasion we have prepared a page about why MyHDL may be useful to you: http://www.myhdl.org/doku.php/why Regards, Jan -- Jan Decaluwe - Resources bvba - http

Re: MyHDL (was Re: Will Python on day replace MATLAB...)

HDL which is a major new feature. This is mostly done and available from development releases (which I put on the website, not on SourceForge). Still have to write a significant amount of new documentation though. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermans

Re: [ANNOUNCE] MyHDL 0.5 released

RTL) synthesizable. > Maybe I should continue this conversation on the MyHDL list, since I'd be > interested in getting started in this in a simple way. You're welcome! Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium Fro

Re: MyHDL 0.5 released

believe it is :-) Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com -- http://mail.python.org/mailman/listinfo/python-list

Re: [ANNOUNCE] MyHDL 0.5 released

Michael wrote: > Jan Decaluwe wrote: > > >>I'm pleased to announce the release of MyHDL 0.5. >> >>MyHDL is an open-source package for using Python as a hardware >>description and verification language. Moreover, it can convert >>a design to Verilog.

Puzzled by py.test output

pwatch/test.py:7] _ == tests finished: 2 failed in 0.02 seconds == Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com -- http://mail.python.org/mailman/listinfo/python-list