On 06/04/2011 08:27 PM, TommyVee wrote:
I'm using the SimPy package to run simulations. Anyone who's used this package knows that the way it simulates process concurrency is through the clever use of yield statements. Some of the code in my programs is very complex and contains several repeating sequences of yield statements. I want to combine these sequences into common functions. The problem of course, is that once a yield gets put into a function, the function is now a generator and its behavior changes. Is there any elegant way to do this? I suppose I can do things like ping-pong yield statements, but that solutions seems even uglier than having a very flat, single main routine with repeating sequences.
In MyHDL, this is supported by the possibility to yield generators, which are then handled by the simulation engine. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com -- http://mail.python.org/mailman/listinfo/python-list
