Seongbae Park wrote:
membar #storestore is effectively a nop on all existing sparc processors
because they only support TSO mode. So there's no performance penalty.
On SPARC, yes. Not so on x86 or amd64 unfortunately with sfence.
Is there any chance that cpu_mstate_gen wraps around
betwe
Ethan Solomita wrote:
There have been several changes to the webrev for 5062435, and so I'm
putting it out for a second review. The most important was my
ass*u*mption that just because the CPU obeyed TSO rules, that the
compiler couldn't screw it up. Unfortunately it's almost impossible to
I've been playing around with the tools on a Stinger box and I think their pretty cool!
The one question I have is whether ISM (Intimate Shared Memory)
segments are immune to being coerced to relocate via pmadvise(3c)? I've
tried it without success. A quick look at the seg_spt.c code seemed to
ind
There have been several changes to the webrev for 5062435, and so
I'm putting it out for a second review. The most important was my
ass*u*mption that just because the CPU obeyed TSO rules, that the
compiler couldn't screw it up. Unfortunately it's almost impossible to
prevent a compiler from
