Hi Roger,
how many ethernet ports does this product has? 1 or 2?
Ubiquity add a switch chip to it's new nanostation m (xw).
I would say this product has only one port.
Can you try this init please?
static void __init ubnt_rocket_m_xw_setup(void)
{
ubnt_xw_init();
ath79_register_mdio(0, ~BIT
Signed-off-by: Roman Yeryomin
---
...ath79-make-chipselect-logic-more-flexible.patch | 89 --
.../patches-3.18/603-MIPS-ath79-ap121-fixes.patch | 40 +-
.../patches-3.18/605-MIPS-ath79-db120-fixes.patch | 10 +--
.../607-MIPS-ath79-ubnt-xm-fixes.patch | 1
Signed-off-by: Roman Yeryomin
---
...ath79-make-chipselect-logic-more-flexible.patch | 21 -
.../patches-3.18/604-MIPS-ath79-ap81-fixes.patch | 50 ++
...614-MIPS-ath79-ap81-remove-mtd-partitions.patch | 49 -
3 files changed, 3 insertions(+), 117
i also love two more names:
* drivers delight
* dozen daiquiri
the first one is without alcohol :-/
but there are at least some openwrt-users who are under-age!
the second one would be nice to scare barkeepers, but its a COMMON
cocktail! it really means: please, 12 drinks...
especially within o
It was reported that OM5P-AN needs not only a delay setting of 1 for RXD/RDV
but 2. These was found when testing with a NetGear GS752TP POE switch with a
cable length of 50ft and 250ft.
Signed-off-by: Sven Eckelmann
---
target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c | 5 ++---
1 file chan
The ETH_RXDV_DELAY (17:16) and ETH_RXD_DELAY (15:14) are currently not cleared
by the function ath79_setup_ar934x_eth_cfg. Clearing these in the
ath79_setup_ar934x_eth_cfg may cause problems on some hardware because they
rely on the preset value by the bootloader.
Instead another function is intro
The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X
register file") introduced definitions for some bits in the RDV/RXD part of the
ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is
specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The orig
The tx/rx delay bits in the ETH_XMII_CONTROL register have to be unset when the
enable_rgmii_rx_delay/enable_rgmii_tx_delay will be set in the AT803x PHY.
Othwise the throughput in gigabit mode is heavily reduced.
Signed-off-by: Sven Eckelmann
---
target/linux/ar71xx/files/arch/mips/ath79/mach-o
In other words: "welcome to the team" :)
On 2015-04-15 04:23, Javier Domingo Cansino wrote:
> As far as I know, regarding documentation, there is no a specific group of
> people. I just edit the wiki whenever I see something is not contained and I
> can
> explain it correctly.
>
> On Tue, Apr
Hi,
I've been working on supporting the new XW version of Ubiquiti's Rocket M5
devices. The hardware is very similar to the NanoStation [Loco] M5 XW, so
the images for these devices work on the Rocket *except* for the Ethernet
interface. I posted some information about the device in the forum
As far as I know, regarding documentation, there is no a specific group of
people. I just edit the wiki whenever I see something is not contained and
I can explain it correctly.
On Tue, Apr 14, 2015 at 10:20 PM Eric Schultz
wrote:
> All,
>
> I'm looking to improve some of the documentation aroun
On Wed, 2015-04-15 at 09:01 +0200, Rafał Miłecki wrote:
> On 15 April 2015 at 07:37, Ian Kent wrote:
> > On Sun, 2015-04-12 at 19:01 +0200, Rafał Miłecki wrote:
> >> Newer revisions (5+) of BCM53011 and probably all revs of BCM53012
> >> require overriding CPU port to work. So far we were handling
On 15 April 2015 at 07:37, Ian Kent wrote:
> On Sun, 2015-04-12 at 19:01 +0200, Rafał Miłecki wrote:
>> Newer revisions (5+) of BCM53011 and probably all revs of BCM53012
>> require overriding CPU port to work. So far we were handling it only for
>> CPU port 8, but some devices may use e.g. port 5
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