I think that the problem is because of stripboard PCB with a little bit lengthy
wires. There might be some interference...
>
> If the svf file is generated by the xilinx tools, then 1MHz should be OK.
> Does JTAG pins have too long latency?
> I'll check th
If the svf file is generated by the xilinx tools, then 1MHz should be OK.
Does JTAG pins have too long latency?
I'll check the speed later when my board arrived.
2010/2/16 Vaclav Peroutka
> Hello Simon,
>
> yes, lowering the TCK frequency helped! Default TCK speed of 1MHz made
> problems, but no
Hello Simon,
yes, lowering the TCK frequency helped! Default TCK speed of 1MHz made
problems, but now I use 500kHz and programming is ok.
Thank you for help,
Vaclav
>
> According to the log file, the svf parser should be running OK.
> The command below c
I have ordered a XC9572XL board. It will be sent to me after Chinese New
Year holiday.
I'll mail you when there is a result.
2010/2/16 simon qian
> According to the log file, the svf parser should be running OK.
> The command below can run success with the right TDO value:
> SDR 32 TDI (00
According to the log file, the svf parser should be running OK.
The command below can run success with the right TDO value:
SDR 32 TDI () SMASK () TDO (F9604093) MASK (0FFF)
But one command after that will fail, not fail to do JTAG, but fail to
receive the right TDO valu
Try adding '-d3' option, and post the log info.
2010/2/14 Vaclav Peroutka
> Hello all,
>
> I compiled git HEAD revision of openocd today and try to program XC9572
> with SVF generated by Xilinx ISE 10.1. I use following openocd.cfg:
> telnet_port
> gdb_port
> interface ft2232
> ft2232_
