Re: [Openocd-development] [Patch] TAR autoincrement block size and alignment

> >> Hi > >> > >> The number of bits used for TAR autoincrement when using > >> CSW_ADDRINC_PACKED must be at least 10 according to ARM ADI > >> specifications. Cortex-M3 uses 12 bits (4k blocks) and > OMAP35xx uses > >> 10 bits (1k blocks). > >> > >> This patch adds support for different T

Re: [Openocd-development] [Patch] TAR autoincrement block size and alignment

Zach Welch wrote: On Thu, 2009-06-04 at 12:49 +0200, Magnus Lundin wrote: Hi The number of bits used for TAR autoincrement when using CSW_ADDRINC_PACKED must be at least 10 according to ARM ADI specifications. Cortex-M3 uses 12 bits (4k blocks) and OMAP35xx uses 10 bits (1k blocks). Th

Re: [Openocd-development] [Patch] TAR autoincrement block size and alignment

On Thu, 2009-06-04 at 12:49 +0200, Magnus Lundin wrote: > Hi > > The number of bits used for TAR autoincrement when using > CSW_ADDRINC_PACKED must be at least 10 according to ARM ADI > specifications. Cortex-M3 uses 12 bits (4k blocks) and OMAP35xx uses 10 > bits (1k blocks). > > This patch

[Openocd-development] [Patch] TAR autoincrement block size and alignment

Hi The number of bits used for TAR autoincrement when using CSW_ADDRINC_PACKED must be at least 10 according to ARM ADI specifications. Cortex-M3 uses 12 bits (4k blocks) and OMAP35xx uses 10 bits (1k blocks). This patch adds support for different TAR autotincrement sizes and sets it to 12